A semiconductor processing apparatus

Abstract

The application provides a semiconductor processing device, which comprises a first chamber part, a second chamber part movable relative to the first chamber part between an open position and a closed position, and a semiconductor wafer placed between the first chamber part and the second chamber part. A plurality of adjustable wafer positioning mechanisms are dispersedly mounted on the first chamber part or the second chamber part, each adjustable wafer positioning mechanism comprising a driving mechanism and a positioning head mounted on the driving mechanism, the positioning head having a positioning slope, the driving mechanism being capable of driving the positioning head to move, the positioning slope being capable of contacting the edge of the semiconductor wafer during the movement of the positioning head, and the positioning head being capable of continuously moving to push the semiconductor wafer inwardly by the positioning slope when the positioning head continues to move. The position of the positioning head of each adjustable wafer positioning mechanism can be adjusted to position the semiconductor wafer. Thus, the accurate positioning of the semiconductor wafer can be realized.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor wafer processing, and particularly to semiconductor processing apparatus. [Background Technology]

[0002] Precise edge etching of semiconductor wafers is a challenging process. It requires achieving micron-level precision etching at the wafer edge without damaging or contaminating the remaining thin film. In epitaxial wafer fabrication and advanced integrated circuit manufacturing processes, wafer edge etching is a crucial step in ensuring thin film formation quality and improving chip yield.

[0003] Please refer to Figures 1a to 1d ,in: Figure 1a A schematic diagram of the structure of a semiconductor wafer 400 is shown. Figure 1b for Figure 1a EE sectional view; Figure 1c A partial cross-sectional view of the outer edge of a semiconductor wafer before edge processing; Figure 1d This is a cross-sectional view of the outer edge of a semiconductor wafer after edge treatment. (Example:) Figures 1a to 1d As shown, the semiconductor wafer 400 includes a substrate layer 401 and a thin film layer 402 formed on a first edge surface and a second edge surface of the substrate layer 401. After selective etching of the first edge surface 404, the second wafer surface 406, and the outer edge bevel 408 of the outer edge portion of the semiconductor wafer 400, the thin film layer 402 of the outer edge portion of the semiconductor wafer 400 is removed, and the first edge surface and the second edge surface of the substrate layer 401 are exposed.

[0004] Existing wafer edge etching equipment can be broadly categorized into dry and wet methods. Dry methods are mainly divided into plasma etching and polishing. Plasma edge etching equipment is expensive and complex, primarily used in integrated circuit chip manufacturing. Polishing removes the contact film by rotating the wafer and utilizing physical friction and a combination of chemical gases and liquids. Polishing equipment is less expensive, but it is prone to damage and contamination of the retained film, and is mainly used in wafer manufacturing processes smaller than 200mm. Wet methods mainly include film-coating and vacuum adsorption. Film-coating uses a pure, corrosion-resistant plastic film such as PTFE or PE to protect the portion of the film to be retained, then exposes the entire wafer to a chemical etching gas environment or immerses it in a chemical etching solution to etch away the exposed portion. Film-coating involves multiple steps and requires various equipment, including equipment for film coating, wet etching, cleaning, and film removal. Vacuum adsorption uses a vacuum suction head to hold the wafer. The function of the vacuum suction head is to hold the wafer, protecting the portion of the film to be retained inside the suction head, while exposing the portion of the film to be removed outside the suction head. Then, the vacuum suction head and wafer are immersed together in a chemical etching solution to etch away the exposed film portion. The vacuum adsorption method has simple process steps and low equipment cost, but it is prone to damage and contamination of the retained film portion, and is mainly used in wafer manufacturing processes smaller than 200mm.

[0005] Chinese patent application number 201821459515.8, entitled "A Semiconductor Processing Apparatus," discloses an edge processing scheme for a semiconductor wafer. For this edge processing scheme, the accuracy of the center positioning of the semiconductor wafer is crucial; if the center positioning is inaccurate, the edge processing result will have a significant error.

[0006] Therefore, it is necessary to propose an improved semiconductor processing apparatus that can improve the accuracy of center positioning of the semiconductor wafer. [Summary of the Invention]

[0007] The purpose of this invention is to provide a semiconductor processing apparatus that can flexibly and precisely adjust the position of a wafer to achieve precise edge etching of the wafer.

[0008] To achieve the above objectives, according to a first aspect of the present invention, a semiconductor processing apparatus is provided, comprising: a first chamber portion; a second chamber portion movable relative to the first chamber portion between an open position and a closed position, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a micro-chamber is formed between the first chamber portion and the second chamber portion, a semiconductor wafer can be accommodated in the micro-chamber, and when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be removed or placed in; a plurality of adjustable wafer positioning mechanisms distributedly mounted on the first chamber portion or the second chamber portion, each adjustable wafer positioning mechanism including a drive mechanism and a positioning head mounted on the drive mechanism, the positioning head having a positioning bevel, the drive mechanism being capable of driving the positioning head to move, during the movement of the positioning head causing the positioning bevel to contact the edge of the semiconductor wafer, and at this time, continued movement of the positioning head causing the positioning bevel to push the semiconductor wafer inward, and the semiconductor wafer can be positioned by adjusting the position of the positioning head of each adjustable positioning mechanism.

[0009] Compared with the prior art, the present invention includes multiple adjustable positioning mechanisms that are distributed and installed on the first chamber or the second chamber. By adjusting the position of the positioning head of each adjustable positioning mechanism, the semiconductor wafer can be centered. [Attached Image Description]

[0010] The invention will be more readily understood in conjunction with the accompanying drawings and the following detailed description, wherein the same reference numerals correspond to the same structural components, wherein:

[0011] Figure 1a This is a schematic diagram of the structure of a semiconductor wafer;

[0012] Figure 1b for Figure 1a EE sectional view;

[0013] Figure 1c A cross-sectional view of the outer edge portion of a semiconductor wafer before edge processing;

[0014] Figure 1d This is a cross-sectional view of the outer edge portion of a semiconductor wafer after edge treatment.

[0015] Figure 2a This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the first embodiment of the present invention;

[0016] Figure 2b for Figure 2a An enlarged diagram of circle A in the diagram;

[0017] Figure 3a for Figure 2aA bottom view of the first chamber portion of the semiconductor processing device;

[0018] Figure 3b for Figure 2a A top view of the second chamber portion of the semiconductor processing device;

[0019] Figure 4 This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the second embodiment of the present invention;

[0020] Figure 5 for Figure 4 An enlarged diagram of circle B in the diagram;

[0021] Figure 6a for Figure 4 A bottom view of the first chamber portion of the semiconductor processing device;

[0022] Figure 6b for Figure 4 A top view of the second chamber portion of the semiconductor processing device;

[0023] Figure 7 This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the third embodiment of the present invention;

[0024] Figure 8 for Figure 7 An enlarged diagram of circle D in the diagram.

Detailed Implementation Methods

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic associated with that embodiment that is included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it necessarily a single or alternative embodiment that is mutually exclusive with other embodiments. "A plurality of" or "several" in this invention means two or more. "And / or" in this invention means "and" or "or".

[0027] First embodiment:

[0028] Please refer to Figures 2a to 3b It shows a schematic diagram of the structure of a semiconductor processing apparatus 100 provided in the first embodiment of the present invention, wherein: Figure 2a This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the first embodiment of the present invention; Figure 2b for Figure 2a An enlarged diagram of circle A in the diagram; Figure 3a for Figure 2aA bottom view of the first chamber portion of the semiconductor processing device; Figure 3b for Figure 2a A top view of the second chamber of the semiconductor processing device.

[0029] Please refer to Figures 2a to 3b The semiconductor processing apparatus 100 includes a first chamber portion 110 and a second chamber portion 120. The first chamber portion 110 includes a first chamber plate 119 and a flange 118 extending from the periphery of the first chamber plate 119. The second chamber portion 120 includes a second chamber plate 129 and a flange 128 extending from the periphery of the second chamber plate 129.

[0030] The first chamber portion 110 is movable relative to the second chamber portion 120 between an open position and a closed position. It should be noted that the movement of the first chamber portion 110 and the second chamber portion 120 is relative. The first chamber portion 110 can be fixed while the second chamber portion 120 moves relative to it; the second chamber portion 120 can be fixed while the first chamber portion 110 moves relative to it; or both the first chamber portion 110 and the second chamber portion 120 can move simultaneously, as long as they can move relative to each other. When the first chamber portion 110 is in the closed position relative to the second chamber portion 120, the flange 118 and the flange 128 cooperate to form a micro-cavity 140 between the first chamber plate 118 and the second chamber plate 128. The semiconductor wafer 400 to be processed can be accommodated within the micro-cavity 140, awaiting subsequent processing. When the first chamber portion 110 is in the open position relative to the second chamber portion 120, the flange 118 separates from the flange 128, and the semiconductor wafer 400 to be processed can be removed or placed into the microchamber 140.

[0031] An annular first channel 116 is formed on the side of the first chamber portion 110 facing the microchamber 140, and a second channel 126 is formed on the side of the second chamber portion 120 facing the microchamber 140. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is housed in the microchamber, the first channel 116 and the second channel 126 together form an edge microprocessing space 130, and the outer edge of the semiconductor wafer 400 housed in the microchamber extends into the edge microprocessing space 130.

[0032] like Figures 2a to 3bAs shown, in this embodiment, the first channel 116 and the second channel 126 are annular channels. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is accommodated in the micro-cavity, the wall surface 117 of the first chamber portion 110 located inside the first channel 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber portion 120 located inside the second channel 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed. The first channel 116 and the second channel 126 together form a closed, annular outer edge microprocessing space 130, and the outer edge portion of the semiconductor wafer 400 to be processed is accommodated within the edge microprocessing space 130.

[0033] Therefore, in this embodiment, the edge microprocessing space 130 can selectively process the entire outer edge of the semiconductor wafer 400 to be processed.

[0034] Of course, the first channel 116 and the second channel 126 can also be configured as arc-shaped channels with an arc degree less than 360 degrees. In this case, a closed, arc-shaped outer edge microprocessing space 130 with an arc degree less than 360 degrees is formed between the first channel 116 and the second channel 126. Correspondingly, a portion of the arc segment of the outer edge of the semiconductor wafer 400 to be processed is accommodated within the edge microprocessing space 130. Therefore, the edge microprocessing space 130 at this time only performs selective processing on a portion of the arc segment of the outer edge of the semiconductor wafer 400 to be processed.

[0035] The first chamber portion 110 has at least two edge processing through holes 112 extending from the outside to communicate with the edge microprocessing space 130, wherein at least one edge processing through hole serves as a fluid inlet and at least one edge processing through hole serves as a fluid outlet. In this embodiment, four edge processing through holes are provided. Of course, the second chamber portion 120 may also be provided with edge processing through holes communicating with the edge microprocessing space 130.

[0036] In application, the processing fluid can enter the edge microprocessing space 130 through an edge processing via 112. The fluid entering the edge microprocessing space 130 can flow within it, allowing it to contact and process the outer edge portion of the semiconductor wafer 400 contained within the edge microprocessing space 130. The processed fluid can then flow out through another edge processing via 112, or through an edge processing via on the second chamber portion 120 that communicates with the edge microprocessing space 130. During processing, the processing fluid can be continuously or periodically introduced into the edge microprocessing space 130 through an edge processing via 112, allowing the fluid within the edge microprocessing space 130 to flow, thus accelerating the processing speed.

[0037] Of course, the process may be an etching process on the outer edge of the semiconductor wafer 400 to remove the thin film layer on the outer edge portion of the semiconductor wafer 400, or it may be selective cleaning of only the outer edge of the semiconductor wafer 400, etc.

[0038] Taking the etching and removal of the thin film layer on the outer edge of the semiconductor wafer 400 to be processed as an example. (Refer to reference...) Figures 1a to 1d and Figures 2a to 3b As shown, when it is necessary to etch away the thin film layer on the first and second sides of the outer edge of the semiconductor wafer 400 to be processed, a corresponding processing fluid with an corrosive effect on the thin film layer is simply introduced into the edge microprocessing space 130 through an edge processing via 112. The processing fluid flows within the edge microprocessing space 130 and directly contacts the outer edge portion of the semiconductor wafer 400 to be processed. The processing fluid flows along the edge of the semiconductor wafer 400 to be processed, and undergoes a chemical or physical reaction with the wafer surface contained within the edge microprocessing space, thereby continuously etching away the thin film layer 402 on the first edge surface, the second edge surface, and the bevel of the outer edge of the semiconductor wafer 400 to be processed. Figure 1d As shown, after processing, the portion of the thin film layer 402 contained within the edge microprocessing space 130 at the outer edge of the semiconductor wafer 400 is etched away, exposing the first edge surface, the second edge surface, and the outer bevel of the substrate layer 401 at the outer edge of the semiconductor wafer 400. The fluid that has been processed from the semiconductor wafer 400 flows out through other edge processing vias.

[0039] As can be seen, based on the edge microprocessing space 130, the semiconductor processing device 100 in this embodiment only requires a small amount of processing fluid to achieve selective etching of the outer edge of a semiconductor wafer 400 to be processed, which greatly reduces processing costs and production waste volume. Furthermore, compared with dry processing devices in the prior art, the semiconductor processing device 100 in this embodiment has significant advantages such as simple structure, ease of use, and low skill requirements for operators.

[0040] As can be seen, the semiconductor processing apparatus 100 provided in this embodiment can selectively process the outer edge of the semiconductor wafer 400 to be processed. Furthermore, by controlling the flow rate of the processing fluid within the semiconductor wafer 400 to be processed, the amount of processing fluid can be saved while ensuring processing effectiveness. Continuing to refer to... Figures 2a to 2b As shown, in this embodiment, the first chamber portion 110 further has a first recess 115 formed on the inner wall surface of the first chamber portion 110 facing the microchamber, the first recess being located inside the first channel 116. The second chamber portion 120 further has a second recess 125 formed on the inner wall surface of the second chamber portion 120 facing the microchamber, the second recess being located inside the second channel 126. The first recess 115 and the second recess 125 are also annular. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 to be processed is housed in the micro-cavity, a portion of the second edge surface of the semiconductor wafer 400 to be processed covers the top of the second recess 125 to form a second inner microspace, and a portion of the first edge surface of the semiconductor wafer 400 to be processed covers the top of the first recess 115 to form a first inner microspace. The first inner microspace and the second inner microspace are located inside the edge microprocessing space 130.

[0041] Correspondingly, the first chamber portion 110 has a first inner processing through-hole communicating with the first recess portion 115, and the second chamber portion 120 has a second inner processing through-hole communicating with the second recess portion 125. When etching the edge of the semiconductor wafer 400 using the edge microprocessing space 130, liquid or gas, such as water or nitrogen, can be introduced into the first recess portion 115 and the second recess portion 125, that is, liquid or gas can be introduced into the first inner microspace and the second inner microspace to prevent liquid in the edge microprocessing space 130 from penetrating inward.

[0042] Similarly, the first recess 115 and the second recess 125 can also be arc-shaped.

[0043] Continue to refer to, for example Figures 2a to 2bAs shown, in this embodiment, when the second chamber portion 120 and the first chamber portion 110 are in the closed position, a micro-chamber 140 is also formed in their middle portions. The second chamber portion 120 has a central processing through hole 123 communicating with the micro-chamber 140, and the first chamber portion 110 has a central processing through hole 113 communicating with the micro-chamber 140.

[0044] For reference Figure 2b As shown, the first chamber portion 110 has a sealing engagement portion 210 located outside the first channel 116, and the second chamber portion 120 has an engagement groove 122 corresponding to the sealing engagement portion 210. The sealing engagement portion 210 includes a guide surface 211 at its end and an inner surface 212 at its inner side. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110, the end of the sealing engagement portion 210 extends into the engagement groove 122, and the end portion of its inner surface 212 seals against the groove wall of the engagement groove 122. The upper end portion of its inner surface 212 forms the outer surface of the outer edge microprocessing space 130. Furthermore, the sealing surface of the inner surface 212 of the sealing joint 210 and the groove wall of the joint groove 122 is located below the outer edge microprocessing space 130, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer 400. This arrangement allows the wall surface 117 of the first chamber 110 located inside the first channel 116 to abut more closely with the first edge surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber 120 located inside the second channel 126 to abut more closely with the second edge surface of the semiconductor wafer 400 to be processed, thus preventing the etchant from penetrating inward.

[0045] exist Figure 2b In this embodiment, during the closing of the second chamber portion 120 relative to the first chamber portion 110, the inner surface 212 of the sealing joint portion 210 can achieve center positioning of the semiconductor wafer 400. That is, if the center of the semiconductor wafer 400 deviates from the desired center during placement, the inner edge surface 212 of the sealing joint portion 210 can also be pressed against the semiconductor wafer 140 to correct its center to the desired center. In one example, during edge processing, the center deviation of the semiconductor wafer 400 needs to be no more than 0.2 mm. Using the method of the present invention, the center deviation can be adjusted to within 0.1 mm. The guide surface 211 can guide the sealing joint portion 210 into the engagement groove 122 when the first chamber portion 110 and the second chamber portion 120 are closed. The sealing joint portion 210 can be locked within the engagement groove 122.

[0046] For reference Figure 2aAs shown, the first chamber 110 includes a positioning groove 114, and the second chamber 120 includes a positioning post 124, which allows the first chamber 110 and the second chamber 120 to be correctly positioned when closed. During the closing process of the first chamber 110 and the second chamber 120, the positioning post 124 first engages with the positioning groove 114 to achieve initial positioning, and then the end of the sealing joint 210 extends into the engagement groove 122.

[0047] In one embodiment, the semiconductor processing apparatus 100 of the present invention is used to perform a silicon oxide wafer edge etching process. The specific method may include closing the cavity, HF acid etching, DIW (deionized water) rinsing, IPA (isopropanol) rinsing, nitrogen drying, and opening the cavity. The specific processes of HF acid etching, DIW (deionized water) rinsing, and IPA (isopropanol) rinsing can all be performed according to the procedures described above. Specifically, during the HF acid etching process, liquid or gas, such as water or nitrogen, can be introduced into the first recess 115 and the second recess 125 to prevent liquid from seeping into the edge microprocessing space 130.

[0048] Second Embodiment

[0049] Please refer to Figures 4 to 6b It shows a schematic diagram of the structure of a semiconductor processing apparatus 200 provided in the second embodiment of the present invention, wherein: Figure 4 This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the first embodiment of the present invention; Figure 5 for Figure 4 An enlarged diagram of circle B in the diagram; Figure 6a for Figure 4 A bottom view of the first chamber portion of the semiconductor processing device; Figure 6b for Figure 4 A top view of the second chamber of the semiconductor processing device.

[0050] The semiconductor processing device 200 in the second embodiment has a structure that is mostly the same as that of the semiconductor processing device 100 in the first embodiment. Therefore, the same parts are marked with the same symbols. The main difference between the two is that the sealing joint 310 of the semiconductor processing device 200 and the sealing joint 210 of the semiconductor processing device 100 have some differences in structure.

[0051] like Figure 5 As shown, the first chamber portion 110 has the sealing joint portion 310 located outside the first channel 116, and the second chamber portion 120 has a joint groove 122 corresponding to the sealing joint portion 210.

[0052] The sealing joint 310 includes a guide surface 311 at its end, an inner surface 312 at its upper inner end, and a protrusion 313 at its inner end. When the second chamber 120 is in the closed position relative to the first chamber 110, the end of the sealing joint 310 extends into the engagement groove 122, and its protrusion 313 seals against the groove wall of the engagement groove 122. Its inner surface 312 forms the outer surface of the outer edge microprocessing space 130. The inner surface 312 is still spaced from the outer edge of the semiconductor wafer 400.

[0053] The sealing surface formed by the protrusion 313 of the sealing joint 310 and the groove wall of the joint groove 122 is located below the outer edge microprocessing space 130, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer 400. This arrangement allows the wall surface 117 of the first chamber portion 110 located inside the first channel 116 to abut more closely with the first side surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber portion 120 located inside the second channel 126 to abut more closely with the second side surface of the semiconductor wafer 400 to be processed, thus preventing the etchant from penetrating inward.

[0054] exist Figure 2b In one embodiment, during the closing process of the second chamber portion 120 relative to the first chamber portion 110, the bumps 313 of the sealing joint portion 310 can achieve center positioning of the semiconductor wafer 140. That is, if the center of the semiconductor wafer 140 deviates from the desired center when it is placed, the bumps 313 of the sealing joint portion 310 can also correct its center to the desired center by squeezing the semiconductor wafer 140.

[0055] Because there is still a distance between the inner surface 312 and the outer edge of the semiconductor wafer 400, the semiconductor wafer 400 is less likely to be clamped by the sealing joint 310 when the second chamber portion 120 disengages from the first chamber portion 110.

[0056] In another embodiment, the semiconductor wafer 400 may not be centered using the bump 313, meaning the bump 313 will not contact the edge of the semiconductor wafer 400. Instead, the centering of the semiconductor wafer 400 can be achieved using the edge of the wall of the first channel 116.

[0057] Third Embodiment

[0058] Figure 7 This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the third embodiment of the present invention; Figure 8 for Figure 7 An enlarged diagram of circle D in the diagram.

[0059] like Figure 7 and 8 As shown, the semiconductor processing apparatus includes a first chamber portion 110 and a second chamber portion 120. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110, a microchamber is formed between the first chamber portion 110 and the second chamber portion 120, and a semiconductor wafer 400 can be accommodated in the microchamber. When the second chamber portion 120 is in the open position relative to the first chamber portion 110, the semiconductor wafer 400 can be removed or inserted.

[0060] Similar to the first and second embodiments, the first channel formed on the first chamber portion 110 and the second channel formed on the second chamber portion 120 are connected and can jointly form an edge microprocessing space with the edge of the semiconductor wafer. Edge processing of the semiconductor wafer 400 can be performed using this edge microprocessing space. The relevant structures and descriptions regarding edge processing of the semiconductor wafer 400 using the edge microprocessing space will not be repeated in this embodiment.

[0061] The difference between this embodiment and the first and second embodiments is that the semiconductor processing apparatus in this embodiment further includes a plurality of adjustable positioning mechanisms 150 distributedly mounted on the first chamber portion 110 or the second chamber portion 120. Figure 7 In this embodiment, the adjustable positioning mechanism 150 is mounted on the first chamber portion 110. In other embodiments, the adjustable positioning mechanism 150 may also be mounted on the second chamber portion 120. There are at least three adjustable positioning mechanisms. Figure 7 The adjustable positioning mechanism 150 is four in number. The adjustable positioning mechanisms can be evenly arranged, for example, three can be spaced 120 degrees apart, and four can be spaced 90 degrees apart.

[0062] Each adjustable positioning mechanism 150 includes a drive mechanism (not labeled) and a positioning head 151 mounted on the drive mechanism. The positioning head 151 has a positioning ramp 152. The drive mechanism can drive the positioning head 151 to move linearly. During the movement of the positioning head, the positioning ramp 152 contacts the edge of the semiconductor wafer 400. If the positioning head 151 continues to move, the positioning ramp 152 will push the semiconductor wafer 400 inwards. By adjusting the position of the positioning head 151 of each adjustable positioning mechanism 150, the semiconductor wafer 400 can be precisely centered. The drive mechanism can be a linear stepper motor, which can drive the positioning head 151 to move linearly.

[0063] like Figure 7As shown, the plurality of adjustable positioning mechanisms are distributed and installed on the first chamber portion 110. The positioning head 151 is driven by the driving mechanism to move up and down. During the downward movement of the positioning head 151, the positioning inclined surface 152 contacts the edge of the semiconductor wafer 400. At this time, if the positioning head 151 continues to move downward, the positioning inclined surface 152 will push the semiconductor wafer 400 inward. In another embodiment, the plurality of adjustable positioning mechanisms are distributed and installed on the second chamber portion 120. The positioning head 151 is driven by the driving mechanism to move up and down. During the upward movement of the positioning head, the positioning inclined surface 152 contacts the edge of the semiconductor wafer 400. At this time, if the positioning head 151 continues to move upward, the positioning inclined surface 152 will push the semiconductor wafer inward.

[0064] By adjusting multiple adjustable positioning mechanisms 150 to find the appropriate position of the positioning head 151 of each adjustable positioning mechanism 150, when the positioning head 151 of each adjustable positioning mechanism is in its appropriate position, during the closing process of the first chamber and the second chamber, the semiconductor wafer 400 placed in the microchamber will be precisely centered by each positioning ramp 152. After multiple uses or a period of time, each adjustable positioning mechanism 150 can be readjusted to readjust the appropriate position of each positioning head 151, thereby re-precisely centering the semiconductor wafer 400.

[0065] In another embodiment, after the first chamber and the second chamber are closed, the positioning head 151 can be adjusted to a suitable position to accurately center the semiconductor wafer 400.

[0066] In this embodiment, the relevant structure of the adjustable positioning mechanism 150 is mainly introduced. The semiconductor processing device in the first and second embodiments above can also use the adjustable positioning mechanism 150 to center the semiconductor wafer 400. As long as multiple adjustable positioning mechanisms 150 are set at different positions, the principle of center positioning will not be repeated.

[0067] In the embodiments provided in this invention, the semiconductor processing apparatus is used for edge processing. However, those skilled in the art will know that the semiconductor processing apparatus may also not perform edge processing, may not provide edge microprocessing space or related structures, and may process the entire surface of the semiconductor wafer.

[0068] The adjustable positioning mechanism 150 in this invention improves the center positioning accuracy of the semiconductor wafer 400. In addition, the center positioning effect can be readjusted, and the processing accuracy requirements are greatly reduced.

[0069] The foregoing description has fully disclosed the specific embodiments of the present invention. It should be noted that any modifications made to the specific embodiments of the present invention by those skilled in the art do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the specific embodiments described.

Claims

1. A semiconductor processing apparatus, characterized in that, It includes: First chamber section; A second chamber portion movable between an open position and a closed position relative to a first chamber portion, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a micro-chamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the micro-chamber; when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be removed or placed in. Multiple adjustable positioning mechanisms are distributed and installed on a first chamber or a second chamber. Each adjustable positioning mechanism includes a drive mechanism and a positioning head mounted on the drive mechanism. The positioning head has a positioning ramp. The drive mechanism can drive the positioning head to move in a straight line. During the movement of the positioning head, the positioning ramp comes into contact with the edge of the semiconductor wafer. If the positioning head continues to move, the positioning ramp will push the semiconductor wafer inward. By adjusting the position of the positioning head of each adjustable positioning mechanism, the semiconductor wafer can be positioned. The first chamber is located at the top, and the adjustable positioning mechanism is installed on the first chamber. During the downward movement of the positioning head, the positioning inclined surface will contact the edge of the semiconductor wafer. At this time, if the positioning head continues to move downward, the positioning inclined surface will push the semiconductor wafer inward. or The second chamber is located below, and the adjustable positioning mechanism is installed on the second chamber. During the upward movement of the positioning head, the positioning inclined surface will contact the edge of the semiconductor wafer. At this time, if the positioning head continues to move upward, the positioning inclined surface will push the semiconductor wafer inward.

2. The semiconductor processing apparatus according to claim 1, characterized in that, By adjusting multiple adjustable positioning mechanisms to find the appropriate position of the positioning head of each adjustable positioning mechanism, when the positioning head of each adjustable positioning mechanism is in its appropriate position, during the closing process of the first chamber and the second chamber, the semiconductor wafer placed in the micro-chamber will be positioned by each positioning ramp.

3. The semiconductor processing apparatus according to claim 2, characterized in that, The driving mechanism is a linear stepper motor, and there are at least three adjustable positioning mechanisms.

4. The semiconductor processing apparatus according to any one of claims 1-3, characterized in that, The first chamber portion has a first channel, and the second chamber portion has a second channel. When the second chamber portion is in the closed position relative to the first chamber portion and a semiconductor wafer is housed within the microcavity, the first channel and the second channel communicate with each other and together with the edge of the semiconductor wafer to form an edge microprocessing space. The outer edge of the semiconductor wafer housed within the microcavity extends into the edge microprocessing space. This edge microprocessing space communicates with the outside through edge processing vias, and fluid enters or exits the edge microprocessing space through these vias. The first chamber portion has a sealing joint portion located outside the first channel, and the second chamber portion has a joint groove corresponding to the sealing joint portion. The first edge surface, the second edge surface, and the outer bevel surface of the semiconductor wafer are exposed to the edge microprocessing space. One or more of the edge processing vias serve as fluid inlets and one or more of the edge processing vias serve as fluid outlets. The edge microprocessing space is annular or arc-shaped, and the outer edge of the semiconductor wafer extends into the edge microprocessing space. The edge microprocessing space is a closed space and communicates with the outside through edge processing vias. The top surface of the inner wall portion of the first channel abuts against the first edge surface of the semiconductor wafer near the first chamber portion, and the top surface of the inner wall portion of the second channel abuts against the second edge surface of the semiconductor wafer near the second chamber portion.

5. The semiconductor processing apparatus according to claim 4, characterized in that, The first chamber portion further has a first recessed portion formed on the inner wall surface of the first chamber portion facing the microcavity, the first recessed portion being located inside the first channel. The second chamber portion further has a second recessed portion formed on the inner wall surface of the second chamber portion facing the microcavity, the second recessed portion being located inside the second channel. When the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated in the microcavity, a portion of the second edge surface of the semiconductor wafer covers the top of the second recessed portion to form a second inner microspace. A portion of the first edge surface of the semiconductor wafer covers the top of the first recessed portion to form a first inner microspace. The first inner microspace and the second inner microprocessing space are located inside the edge microprocessing space. The first chamber portion has a first inner surface processing through-hole communicating with the first recessed portion, and the second chamber portion has a second inner surface processing through-hole communicating with the second recessed portion.

6. The semiconductor processing apparatus according to claim 5, characterized in that, The first and second recesses are annular or arc-shaped. When the edge of the semiconductor wafer is etched using the edge microprocessing space, liquid or gas is introduced into the first and second recesses to prevent liquid in the edge microprocessing space from penetrating inward.

7. The semiconductor processing apparatus according to claim 4, characterized in that, The sealing joint includes an inner edge surface located on the inside. When the second chamber is in the closed position relative to the first chamber, the end of the sealing joint extends into the engagement groove, and the end portion of its inner edge surface seals against the groove wall of the engagement groove. The upper portion of its inner edge surface forms the outer surface of the edge microprocessing space.

8. The semiconductor processing apparatus according to claim 7, characterized in that, The end portion of the inner edge surface of the sealing joint and the sealing surface of the groove wall of the joint groove are located below the edge microprocessing space, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer.

9. The semiconductor processing apparatus according to claim 4, characterized in that, The first chamber includes a positioning groove, and the second chamber includes a positioning post. The positioning post and the positioning groove cooperate to ensure that the first chamber and the second chamber can be correctly positioned when closed.

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