Semiconductor device, method of manufacturing the same, and etching method
By employing a passivation layer structure comprising a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer in semiconductor devices, the problem of plasma damage caused by uneven passivation layer thickness is solved, thereby improving the yield and production volume of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2023-03-29
- Publication Date
- 2026-07-10
AI Technical Summary
In the semiconductor device manufacturing process, the top metal layer is damaged during etching due to uneven passivation layer thickness. Existing technologies cannot effectively solve this technical problem, especially the plasma damage caused by uneven thickness of metallization and passivation layers, which affects the yield and production volume of semiconductor devices.
By employing a passivation layer structure comprising a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer, and utilizing the difference in etching rates of different materials, damage to the top metal layer is reduced or avoided through the etching process, thereby improving the yield and production volume of semiconductor devices.
By fabricating a passivation layer comprising a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer, and utilizing the etching rate characteristics of different materials, the subsequent metal interconnect process is ensured to proceed smoothly. This reduces or avoids plasma damage to the top metal layer during the passivation layer etching process, thereby improving the yield and productivity of semiconductor devices.
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Figure CN116230652B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device and its manufacturing and etching methods. Background Technology
[0002] In integrated circuit manufacturing, metallization and passivation of semiconductor device surfaces are essential parts of the semiconductor manufacturing process. Metallization of semiconductor devices is the process of depositing a conductive metal thin film onto the semiconductor device using chemical or physical treatment methods. Surface passivation (PA) of semiconductor devices enhances the device's ability to resist ion contamination, protecting circuits and internal interconnects from mechanical and chemical damage.
[0003] As the size of semiconductor devices continues to shrink, in order to protect the top metal layer of the semiconductor device from damage, it is necessary to increase the relative thickness of the passivation layer (especially the part of the passivation layer located on the sidewall of the top metal layer), thereby providing stronger support and protection for the top metal layer.
[0004] See Figure 1 When the thickness of the passivation layer 20 formed on the surface of the top metal layer 10 increases, the thickness of the photoresist is insufficient to support the etching of the passivation layer. Therefore, the passivation layer 20 needs to be planarized, for example, by chemical mechanical polishing (CMP), to reduce the thickness of the passivation layer 20 on the surface of the top metal layer 10, facilitating subsequent processes. However, see... Figure 2 After the planarization process, film analysis on the wafer revealed significant differences in the thickness of the passivation layer 20 in different regions.
[0005] See Figure 3 In subsequent metal interconnect processes, when the passivation layer 20 is etched to form openings 21 and 22, the passivation layer 20 has a large thickness difference in different regions. The passivation layer 20 at the location of opening 22 is thinner. Therefore, the over-etching amount at the location of opening 22 is large, and the top metal layer 10 exposed by opening 22 will be severely damaged by plasma, which seriously affects the yield and production of semiconductor devices. Summary of the Invention
[0006] The purpose of this invention is to provide a semiconductor device and its manufacturing and etching methods, which reduce or avoid plasma damage to the top metal layer during the etching process of the passivation layer, thereby improving the yield and productivity of the semiconductor device.
[0007] To achieve the above objectives, the present invention provides a semiconductor device comprising:
[0008] Substrate;
[0009] A top metal layer is disposed on the surface of the substrate;
[0010] A passivation layer covering the top metal layer and the substrate surrounding the top metal layer, the passivation layer comprising, from bottom to top, a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer, wherein the first dielectric layer and the second dielectric layer are made of the same material, and the etch stop layer and the hard mask layer are made of different materials than the first dielectric layer.
[0011] Optionally, the first dielectric layer and the second dielectric layer are silicon oxide layers, the etch stop layer is a silicon nitride layer or a silicon oxynitride layer, and the hard mask layer is a silicon nitride layer.
[0012] Optionally, the thickness of the first dielectric layer is less than the thickness of the second dielectric layer, and the thickness of the etch stop layer is less than the thickness of the hard mask layer.
[0013] Optionally, the thickness range of the first dielectric layer is: The thickness range of the etching stop layer is: The thickness range of the second dielectric layer is The thickness range of the hard mask layer is:
[0014] Optionally, the substrate is a silicon substrate or a silicon-on-insulator substrate.
[0015] Accordingly, the present invention also provides a method for manufacturing a semiconductor device, comprising:
[0016] A substrate is provided on which a top metal layer is formed;
[0017] A first dielectric layer is formed, the first dielectric layer covering the top metal layer and the substrate surrounding the top metal layer;
[0018] An etch stop layer is formed on the first dielectric layer;
[0019] A second dielectric layer is formed on the etch stop layer; and,
[0020] A hard mask layer is formed on the second dielectric layer to form a passivation layer covering the top metal layer and the substrate. The passivation layer is a stacked structure composed of the first dielectric layer, the etch stop layer, the second dielectric layer and the hard mask layer.
[0021] Optionally, the first dielectric layer and the second dielectric layer are formed using a plasma-enhanced chemical vapor deposition process.
[0022] Accordingly, the present invention also provides an etching method for a semiconductor device, wherein the etching is performed using the semiconductor device, comprising:
[0023] A patterned photoresist layer is formed on the hard mask layer;
[0024] A first etching process is performed, using the patterned photoresist layer as a mask to etch the hard mask layer and part of the second dielectric layer to form an opening;
[0025] Remove the patterned photoresist layer;
[0026] A second etching process is performed to continue etching the second dielectric layer at the bottom of the opening until the opening exposes the etching stop layer; and...
[0027] A third etching process is performed to remove the etching stop layer exposed by the opening and the first dielectric layer below the opening, so that the opening exposes the top metal layer.
[0028] Optionally, the first etching process, the second etching process, and the third etching process are all plasma etching processes.
[0029] Optionally, the patterned photoresist layer can be removed using an ashing process and a wet cleaning process.
[0030] In summary, this invention provides a semiconductor device and its manufacturing and etching methods. The semiconductor device includes a substrate, a top metal layer, and a passivation layer; wherein the top metal layer is disposed on the surface of the substrate; the passivation layer covers the top metal layer and the substrate surrounding the top metal layer, and the passivation layer includes, from bottom to top, a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer. The first dielectric layer and the second dielectric layer are made of the same material, while the etch stop layer and the hard mask layer are made of different materials than the first dielectric layer. This invention, by fabricating a passivation layer comprising a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer, utilizes the different etching rates of different materials to ensure the smooth progress of subsequent metal interconnect processes, reduces or avoids plasma damage to the top metal layer during the etching process of the passivation layer, and improves the yield and throughput of the semiconductor device. Attached Figure Description
[0031] Figures 1 to 3 This is a schematic diagram of the structure corresponding to some steps in the manufacturing process of a semiconductor device;
[0032] Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;
[0033] Figure 5 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
[0034] Figure 6 A flowchart illustrating an etching method for a semiconductor device according to an embodiment of the present invention;
[0035] Figures 7 to 11 This is a schematic diagram of the structure corresponding to each step in the etching method of a semiconductor device provided in an embodiment of the present invention;
[0036] The reference numerals in the attached figures are as follows:
[0037] 10 - Top metal layer; 20 - Passivation layer; 21, 22 - Openings;
[0038] 100 - Substrate; 200 - Top metal layer; 300 - Passivation layer; 301 - Opening; 310 - First dielectric layer; 320 - Etching stop layer; 330 - Second dielectric layer; 340 - Hard mask layer; 400 - Patterned photoresist layer. Detailed Implementation
[0039] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0040] Figure 4 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. (See attached diagram.) Figure 4 The semiconductor device described in this embodiment includes:
[0041] Substrate 100;
[0042] A top metal layer 200 is disposed on the surface of the substrate 100;
[0043] A passivation layer (PA) 300 covers the top metal layer 200 and the substrate 100 surrounding the top metal layer 200. The passivation layer 300 includes, from bottom to top, a first dielectric layer 310, an etch stop layer 320, a second dielectric layer 330, and a hard mask layer 340. The first dielectric layer 310 and the second dielectric layer 330 are made of the same material, while the etch stop layer 320 and the hard mask layer 340 are made of different materials than the first dielectric layer 310.
[0044] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments of the present invention, the substrate may also be a silicon on insulator (SOI) substrate or other substrates that meet the process requirements. The present invention does not limit this.
[0045] In this embodiment, the first dielectric layer 310 and the second dielectric layer 330 are silicon oxide layers, the etch stop layer 320 is a silicon nitride layer or a silicon oxynitride layer, and the hard mask layer 340 is a silicon nitride layer. Optionally, the first dielectric layer 310 and the etch stop layer 320 form an ON stacked structure, the second dielectric layer and the hard mask layer 340 form an ON stacked structure, and the passivation layer 300 is an ONON stacked structure composed of two ON stacked structures. In other embodiments of the present invention, the materials of the first dielectric layer 310 and the second dielectric layer 330 can be replaced with other oxide materials, such as tetraethyl orthosilicate, according to process requirements. The materials of the etch stop layer 320 and the hard mask layer 340 can also be replaced with other materials, provided that the following condition is met: the materials of the etch stop layer 320 and the hard mask layer 340 have different etching rates than the materials of the first dielectric layer 310 and the second dielectric layer 330.
[0046] In this embodiment, the thickness of the first dielectric layer 310 is less than the thickness of the second dielectric layer 330, and the thickness of the etch stop layer 320 is less than the thickness of the hard mask layer 340. The specific thickness relationship of each film layer in the passivation layer 300 is as follows: the thickness range of the first dielectric layer 310 is... The thickness range of the etching stop layer 320 is: The thickness range of the second dielectric layer 330 is The thickness range of the hard mask layer 340 is
[0047] Accordingly, see Figure 5 This embodiment also provides a method for manufacturing a semiconductor device, used to manufacture the semiconductor device, comprising:
[0048] Step S01: Provide a substrate on which a top metal layer is formed;
[0049] Step S02: Form a first dielectric layer, the first dielectric layer covering the top metal layer and the substrate surrounding the top metal layer;
[0050] Step S03: Form an etch stop layer on the first dielectric layer;
[0051] Step S04: Form a second dielectric layer on the etch stop layer; and,
[0052] Step S05: A hard mask layer is formed on the second dielectric layer to form a passivation layer covering the top metal layer and the substrate. The passivation layer is a stacked structure composed of the first dielectric layer, the etch stop layer, the second dielectric layer and the hard mask layer.
[0053] In this embodiment, the first dielectric layer and the second dielectric layer are formed using plasma-enhanced chemical vapor deposition (PECVD).
[0054] In addition, see Figure 6 This embodiment also provides an etching method for a semiconductor device, which uses the semiconductor device for etching, including:
[0055] Step S06: Form a patterned photoresist layer on the hard mask layer;
[0056] Step S07: Perform a first etching process, using the patterned photoresist layer as a mask to etch the hard mask layer and part of the second dielectric layer to form an opening;
[0057] Step S08: Remove the patterned photoresist layer;
[0058] Step S09: Perform a second etching process to continue etching the second dielectric layer at the bottom of the opening until the opening exposes the etching stop layer; and,
[0059] Step S10: Perform a third etching process to remove the etching stop layer exposed by the opening and the first dielectric layer below the opening, so that the opening exposes the top metal layer.
[0060] Figures 7 to 11 This is a schematic diagram of the structure corresponding to each step in the etching method for the semiconductor device described in this embodiment. The following is in conjunction with... Figures 7 to 11 The etching method for the semiconductor device described in this embodiment is explained in detail.
[0061] First, refer to Figure 7 Step S06 is executed to form a patterned photoresist layer 400 on the hard mask layer 340.
[0062] Next, refer to Figure 8 Step S07 is executed, performing a first etching process to etch the hard mask layer 340 and a portion of the second dielectric layer 330 using the patterned photoresist layer 400 as a mask to form an opening 301. Optionally, the first etching process is a plasma etching process.
[0063] Then refer to Figure 9Then, perform step S08 to remove the patterned photoresist layer 400. Optionally, the patterned photoresist layer 400 can be removed using an ashing process and a wet cleaning process.
[0064] Next, refer to Figure 10 Step S09 is executed to perform a second etching process, continuing to etch the second dielectric layer 330 at the bottom of the opening 301 until the opening 301 exposes the etching stop layer 320. Optionally, the second etching process is a plasma etching process. In the second etching process, the hard mask layer 340 acts as a mask to protect other film layers below the hard mask layer 340 from etching damage.
[0065] Then refer to Figure 11 Step S10 is executed to perform a third etching process, removing the etching stop layer 320 exposed by the opening 301 and the first dielectric layer 310 below the opening 301, so that the opening 301 exposes the top metal layer 200. Optionally, the third etching process is a plasma etching process.
[0066] Compared with existing technologies, the semiconductor device and its manufacturing and etching methods described in this embodiment eliminate the need for planarization when increasing the relative thickness of the passivation layer, thus avoiding the problem of uneven thickness that may occur in the passivation layer after planarization. This embodiment utilizes a hard mask layer in the passivation layer as a mask to etch other layers within the passivation layer, and leverages the different etching rates of different materials to reduce the thickness differences in different regions of the passivation layer. This reduces or avoids plasma damage to the top metal layer caused by uneven thickness in the areas to be etched in the passivation layer, thereby improving the yield and productivity of the semiconductor device.
[0067] In summary, this invention provides a semiconductor device and its manufacturing and etching methods. The semiconductor device includes a substrate, a top metal layer, and a passivation layer; wherein the top metal layer is disposed on the surface of the substrate; the passivation layer covers the top metal layer and the substrate surrounding the top metal layer, and the passivation layer includes, from bottom to top, a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer. The first dielectric layer and the second dielectric layer are made of the same material, while the etch stop layer and the hard mask layer are made of different materials than the first dielectric layer. This invention, by fabricating a passivation layer comprising a first dielectric layer, an etch stop layer, a second dielectric layer, and a hard mask layer, utilizes the different etching rates of different materials to ensure the smooth progress of subsequent metal interconnect processes, reduces or avoids plasma damage to the top metal layer during the etching process of the passivation layer, and improves the yield and throughput of the semiconductor device.
[0068] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. An etching method for a semiconductor device, characterized in that, include: A substrate is provided on which a top metal layer is formed; A first dielectric layer is formed, the first dielectric layer covering the top metal layer and the substrate surrounding the top metal layer; An etch stop layer is formed on the first dielectric layer, wherein the etch stop layer is a silicon oxynitride layer; A second dielectric layer is formed on the etching stop layer, wherein the first dielectric layer and the second dielectric layer are made of the same material, and the thickness of the first dielectric layer is less than the thickness of the second dielectric layer; as well as, A hard mask layer is formed on the second dielectric layer to form a passivation layer covering the top metal layer and the substrate. The passivation layer is a stacked structure composed of the first dielectric layer, the etch stop layer, the second dielectric layer and the hard mask layer. The hard mask layer is a silicon nitride layer. The materials of the etch stop layer and the hard mask layer are different from the materials of the first dielectric layer, and the materials of the etch stop layer and the hard mask layer have different etching rates than the materials of the first dielectric layer and the second dielectric layer. The thickness of the etch stop layer is less than the thickness of the hard mask layer. A patterned photoresist layer is formed on the hard mask layer; A first etching process is performed, using the patterned photoresist layer as a mask to etch the hard mask layer and part of the second dielectric layer to form an opening; Remove the patterned photoresist layer; A second etching process is performed to continue etching the second dielectric layer at the bottom of the opening until the opening exposes the etching stop layer. as well as, A third etching process is performed to remove the etching stop layer exposed by the opening and the first dielectric layer below the opening, so that the opening exposes the top metal layer. The first etching process, the second etching process and the third etching process are all plasma etching processes.
2. The etching method for a semiconductor device as described in claim 1, characterized in that, The thickness of the first dielectric layer ranges from 0.1 kÅ to 10 kÅ, the thickness of the etch stop layer ranges from 0.2 kÅ to 2 kÅ, the thickness of the second dielectric layer ranges from 1 kÅ to 50 kÅ, and the thickness of the hard mask layer ranges from 3 kÅ to 10 kÅ.
3. The etching method for a semiconductor device as described in claim 1, characterized in that, The substrate is a silicon substrate or a silicon-on-insulator substrate.
4. The etching method for a semiconductor device as described in claim 1, characterized in that, The first dielectric layer and the second dielectric layer are formed using a plasma-enhanced chemical vapor deposition process.
5. The etching method for a semiconductor device as described in claim 1, characterized in that, The patterned photoresist layer is removed using an ashing process and a wet cleaning process.