A ferroelectric memory device based on gallium oxide transistors and hafnium zirconium oxide trench capacitors

Abstract

This invention discloses a ferroelectric memory device based on a gallium oxide transistor and a hafnium oxide zirconium trench capacitor. The ferroelectric memory device includes at least 1024 independent memory cells, all disposed on the same gallium oxide substrate, with adjacent memory cells electrically isolated by an Al₂O₃ insulating layer. Each memory cell includes a gallium oxide transistor, a ferroelectric capacitor, and a Ru metal interconnect layer (i.e., a 1T1C structure) between them. The gallium oxide transistor includes an n-type doped gallium oxide epitaxial layer disposed on the gallium oxide substrate, and a discontinuous Al₂O₃ gate dielectric layer, a gate, a drain, and a source formed on the epitaxial layer. The ferroelectric capacitor is disposed within a circular trench in the gallium oxide substrate, and from near the inner wall surface of the trench, it sequentially includes a bottom electrode, a Hf electrode, and a ferroelectric capacitor. 0.5 Zr 0.5 O2 ferroelectric thin film and top electrode. This invention achieves miniaturization, high-density integration, and high reliability of memory devices, and is particularly suitable for non-volatile data storage applications in harsh environments such as high temperatures.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, specifically relating to a ferroelectric memory device based on gallium oxide transistors and hafnium oxide zirconium trench capacitors. Background Technology

[0002] Dynamic Random Access Memory (DRAM), as one of the mainstream technologies in the semiconductor memory field, typically consists of a transistor and a capacitor (1T1C structure) in its memory cell. As integrated circuit process nodes continue to shrink, traditional silicon-based DRAM faces increasingly severe challenges in further improving storage density, reducing power consumption, and adapting to special operating environments such as high temperature and high power.

[0003] Gallium oxide, as a wide-bandgap semiconductor material, possesses a high critical breakdown electric field and good thermal stability, making it suitable for constructing high-temperature, high-voltage, and high-frequency devices, especially power electronic devices and integrated circuits under extreme environmental conditions. Ferroelectric materials, due to their non-volatile polarization properties, can be used to construct storage capacitors with high dielectric constants, low power consumption, and fast read / write capabilities. 0.5 Zr 0.5 O2 ferroelectric thin films, as a type of ferroelectric material, exhibit good compatibility with CMOS semiconductor processes, maintaining excellent ferroelectric performance even at nanoscale thicknesses and in extreme environments. How to integrate gallium oxide transistors with Hf... 0.5 Zr 0.5 The efficient integration of O2 ferroelectric capacitors aims to simultaneously leverage the voltage and temperature resistance of wide-bandgap semiconductors with the non-volatility and low power consumption advantages of ferroelectric memory. However, the challenges in developing 1T1C dynamic random access memory (1T1C) lie in how to further increase capacitor density within a limited chip area to support continuous miniaturization of memory cells, and how to control process temperature and interface reactions during integration to avoid high-temperature processes damaging the performance of ferroelectric materials or causing a decrease in device reliability.

[0004] In the prior art, for example, Chinese patent CN111799264A discloses a three-dimensional trench ferroelectric memory and its fabrication method, which uses an etching-free process to fabricate high-density integrated three-dimensional trench ferroelectric capacitors on first-generation and second-generation semiconductor substrates such as Si and Ge. However, this type of ferroelectric memory is limited by the material system and device structure, and is prone to mismatch and other problems under high-temperature conditions, making it difficult to meet the requirements for use in extreme high-temperature environments.

[0005] To improve the operational stability of ferroelectric memory devices in high-temperature environments, gallium oxide, with its excellent thermal stability, can be used as the semiconductor substrate material. On the other hand, as the integration density of memory devices continues to increase, traditional planar capacitor structures are no longer sufficient to meet the demands of high-density integration, and three-dimensional trench capacitor structures are gradually becoming an important technological development direction. However, the realization of three-dimensional trench capacitor structures on wide-bandgap semiconductor substrates such as gallium oxide still faces technical challenges such as controlling trench etching precision, high-quality dielectric layer deposition, and conformal electrode layer deposition. Therefore, there is an urgent need to provide a high-performance, high-density, and high-reliability ferroelectric memory integration solution on gallium oxide substrates to meet the needs of next-generation memory applications in advanced scenarios such as high temperature and high power. Summary of the Invention

[0006] In view of the aforementioned shortcomings of current ferroelectric memory devices, this invention provides a ferroelectric memory device based on gallium oxide transistors and hafnium zirconium oxide trench capacitors. The ferroelectric memory device adopts a 1T1C structure, using gallium oxide as the substrate material and hafnium zirconium oxide as the ferroelectric functional layer, with a trench structure formed in the gallium oxide substrate to achieve high-density integration. Compared with existing technologies, this invention has advantages such as good thermal stability and excellent high-temperature resistance, meeting the application requirements of high-temperature ferroelectric memory.

[0007] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0008] In a first aspect, the present invention provides a ferroelectric memory device comprising at least 1024 independent memory cells, all of which are disposed on the same gallium oxide substrate, and adjacent memory cells are electrically isolated by an Al2O3 insulating layer; each memory cell comprises a gallium oxide transistor, a ferroelectric capacitor, and a metal interconnect layer (using a 1T1C structure) between the two.

[0009] The ferroelectric capacitor is disposed within a circular trench region of the substrate, including a bottom electrode disposed on the inner surface of the circular trench, and an Hf electrode disposed on the bottom electrode. 0.5 Zr 0.5 O2 thin film, and in Hf 0.5 Zr 0.5 Top electrode disposed on O2 thin film;

[0010] A metal interconnect layer is set along the outer circle of a circular trench as an electrical interconnect region. A gallium oxide transistor is set outside the electrical interconnect region. The transistor includes an n-type doped gallium oxide thin film (epitaxial layer) set on the substrate, on which a discontinuous Al2O3 thin film (gate dielectric layer) and a gate are sequentially set. The source and drain are set in the non-gate dielectric layer region of the epitaxial layer.

[0011] The bottom electrode of the ferroelectric capacitor and the drain of the gallium oxide transistor are electrically interconnected using a metal interconnect layer to form a 1T1C memory cell.

[0012] Multiple memory cells are interconnected via word lines and bit lines to form a ferroelectric memory device.

[0013] In this invention, the width of the circular groove is 50 nm to 600 nm, preferably 200 nm to 600 nm; the depth-to-width ratio is 5:1 to 25:1, preferably 10:1 to 15:1; and the surface roughness Ra of the groove is in the range of 0.5 nm to 3 nm, preferably 0.5 nm to 2 nm.

[0014] In this invention, the thickness of the n-type doped gallium oxide thin film is 100 nm to 300 nm, preferably 150 nm to 250 nm; the thickness of the Al2O3 thin film gate dielectric layer is 5 nm to 20 nm, preferably 8 nm to 15 nm.

[0015] In this invention, the source and drain are composite heterostructures composed of two single metal layers, preferably Ti / Au, wherein the thickness of the Ti metal layer is 10 nm to 30 nm, preferably 15 nm to 25 nm; the thickness of the Au metal layer is 100 nm to 200 nm, preferably 120 nm to 150 nm, and the Ti metal layer is in contact with the epitaxial layer.

[0016] In this invention, the gate is a composite heterostructure composed of two metal single layers, preferably Ni / Au, wherein the thickness of the Ni metal layer is 30 nm to 70 nm, preferably 40 nm to 60 nm; the thickness of the Au metal layer is 100 nm to 200 nm, preferably 120 nm to 180 nm, and the Ni metal layer is in contact with the gate dielectric layer.

[0017] In this invention, the bottom electrode is a composite heterolayer structure consisting of a metal layer and its metal oxide layer, preferably W / WO. x (0.5≤x≤2) or Ru / RuO2; wherein the thickness ratio of the metal layer to the metal oxide layer is 1:1 to 14:1, preferably 5:1 to 14:1; the metal layer of the bottom electrode is in contact with the inner surface of the circular trench, and the metal oxide layer is in contact with Hf. 0.5 Zr 0.5 O2 ferroelectric thin film contact.

[0018] In this invention, the bottom electrode and the top electrode have a symmetrical structure: when the bottom electrode is W / WO x When (0.5≤x≤2), the top electrode is WO. x / W (0.5≤x≤2); when the bottom electrode is Ru / RuO2, the top electrode is RuO2 / Ru; the bottom electrode and the top electrode have the same metal oxide layer, and the metal oxide layer of the top electrode is the same as that of the Hf 0.5 Zr 0.5 O2 ferroelectric thin film contact.

[0019] In this invention, the bottom electrode and Hf 0.5 Zr 0.5 The thickness ratio of O2 ferroelectric thin films is 1:1 to 6:1.

[0020] In this invention, Hf 0.5 Zr 0.5 The thickness of the O2 ferroelectric thin film is 5 nm to 20 nm, preferably 10 nm to 15 nm.

[0021] In this invention, the metal interconnect layer is a Ru metal thin film, and its thickness is the same as that of the bottom electrode.

[0022] In a second aspect, the present invention provides a method for fabricating the ferroelectric storage device described in the first aspect, comprising the following steps:

[0023] S1: Prepare a smooth and flat gallium oxide substrate, and form circular trenches on its surface by dry etching;

[0024] S2: On the gallium oxide planar substrate next to the circular trench, an n-type doped gallium oxide thin film is deposited as an epitaxial layer. Then, a discontinuous Al2O3 thin film is grown on the epitaxial layer as a gate dielectric layer by atomic layer deposition. The gate material is deposited on the gate dielectric layer. Finally, the source material and drain material are deposited on the non-gate dielectric layer area of ​​the epitaxial layer (the remaining n-type doped gallium oxide thin film) respectively, and annealing is performed to complete the fabrication of a gallium oxide transistor.

[0025] S3: On the inner surface of the circular trench, the bottom electrode and Hf are deposited sequentially. 0.5 Zr 0.5 The O2 ferroelectric thin film and top electrode were prepared and then subjected to rapid annealing to complete the fabrication of a ferroelectric capacitor.

[0026] S4: The bottom electrode of the ferroelectric capacitor and the drain of the gallium oxide transistor are electrically interconnected using a Ru metal interconnect layer to form a 1T1C memory cell; an Al2O3 insulating layer is deposited between adjacent memory cells to achieve electrical isolation between memory cells;

[0027] S5: Interconnect multiple memory cells via word lines and bit lines to form a ferroelectric memory device.

[0028] In this invention, Hf 0.5 Zr0.5 The O2 ferroelectric thin film is an orthorhombic polycrystalline thin film; it is grown by atomic layer deposition. During the growth process, the deposition is carried out in a cyclic manner. In each single cycle, the precursor source is sequentially introduced into the growth chamber in the order of oxygen source, hafnium source, zirconium source, oxygen source, zirconium source, and hafnium source to achieve layer-by-layer deposition of the thin film.

[0029] In this invention, after the deposition of the ferroelectric thin film and electrode structure, the device undergoes a post-annealing process. This post-annealing process employs a rapid thermal annealing process, with the annealing temperature controlled within the range of 400℃-500℃ and the annealing time ranging from 30 to 60 seconds. This rapid thermal annealing process promotes the deposition of Hf... 0.5 Zr 0.5 The O2 ferroelectric thin film undergoes a phase transformation to form a stable ferroelectric orthorhombic phase, effectively improving the remanent polarization and ferroelectric switching characteristics of the film. On the other hand, it reduces the internal defect density of the film and improves the interface quality between the ferroelectric layer and the electrode, thereby enhancing the electrical performance and reliability of the device. Simultaneously, due to the use of a rapid thermal annealing process, the thermal budget is low, avoiding thermal damage to the formed gallium oxide transistor structure, thus ensuring the stable and coordinated operation of the ferroelectric memory cell and the gallium oxide transistor.

[0030] Compared with the prior art, the advantages of the present invention are:

[0031] (1) The ferroelectric memory device prepared by the present invention uses gallium oxide as a substrate and performs trench etching on the gallium oxide substrate to form a three-dimensional capacitor with increased surface area, which effectively improves the storage capacity of the memory device.

[0032] (2) The ferroelectric memory device prepared by this invention has good thermal stability, and the remanent polarization intensity is greater than 15 μC / cm when the temperature reaches 200℃. 2 To meet the needs of aerospace applications.

[0033] (3) The ferroelectric capacitor prepared by the present invention adopts a post-annealing process with an annealing temperature of less than 500°C, which is effectively compatible with modern semiconductor processes.

[0034] (4) The ferroelectric capacitor prepared by the present invention uses metals and their oxides as electrode materials, which can effectively reduce the oxygen vacancy concentration of the ferroelectric thin film, reduce leakage current, and effectively improve the durability of the storage device.

[0035] (5) This invention provides a high-performance, high-density and high-reliability ferroelectric memory integration scheme on a gallium oxide substrate, which is beneficial to its practical application in the field of three-dimensional semiconductor memory. Attached Figure Description

[0036] Figure 1This is a schematic diagram of the structure of a single memory cell and a schematic diagram of the memory array circuit of the 1T1C ferroelectric memory device based on gallium oxide transistors and hafnium oxide zirconium trench capacitors according to the present invention. The schematic diagram does not include the insulating layer between adjacent memory cells.

[0037] Figure 2 for Figure 1 The top view of the structure on the left side does not include the insulating layer between adjacent memory cells.

[0038] Figure 3 This is a flowchart illustrating the fabrication process of the 1T1C ferroelectric memory cell described in this invention.

[0039] Figure 1 and Figure 2 In the diagram, 1: Gallium oxide transistor; 11: Ga2O3 epitaxial film; 12: Al2O3 gate dielectric layer; 13: Ti / Au source; 14: Ti / Au drain; 15: Ni / Au gate; 2: Ferroelectric capacitor; 21: Bottom electrode; 22: Hf 0.5 Zr 0.5 O2 ferroelectric thin film; 23: top electrode; 3: lead layer; 31: bit line; 32: word line; 4: Ru metal interconnect layer; 5: β-Ga2O3 single crystal substrate. Detailed Implementation

[0040] The present application will be further described below with reference to specific embodiments.

[0041] It should be noted that terms such as "upper", "lower", "left", "right", and "middle" used in this specification are only for clarity of description and are not intended to limit the scope of implementation. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered as within the scope of this application.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0043] Unless otherwise specified in the examples, the procedures should be performed under standard conditions or conditions recommended by the manufacturer. Reagents or instruments whose manufacturers are not specified are all commercially available products.

[0044] As used herein, the term “about” is used to provide for the flexibility and imprecision associated with a given term, measure, or value. Those skilled in the art can readily determine the degree of flexibility for a particular variable.

[0045] As used herein, the term “at least one of…” is intended to be synonymous with “one or more of…”. For example, “at least one of A, B, and C” explicitly includes only A, only B, only C, and combinations thereof.

[0046] The present invention will be further described below with reference to the accompanying drawings and embodiments. A storage cell of the ferroelectric storage device of the present invention has the following structure: Figure 1 and Figure 2 As shown. This storage unit is a standard 1T1C structure, located in... <010> On a β-Ga2O3 single-crystal substrate 5, a ferroelectric capacitor 2, a Ru metal interconnect layer 4, and a gallium oxide transistor 1 integrated on the same substrate are collectively formed. The ferroelectric capacitor is disposed within a circular trench region of the substrate and includes a bottom electrode 21 and an Hf electrode 22 sequentially disposed on the inner surface of the circular trench. 0.5 Zr 0.5 An O2 ferroelectric thin film 22 and a top electrode 23. The gallium oxide transistor 1 comprises an n-type doped Ga2O3 epitaxial film 11, an Al2O3 gate dielectric layer 12, a Ti / Au source 13, a Ti / Au drain 14, and a Ni / Au gate 15. The β-Ga2O3 single-crystal substrate 5 has a thickness of 650 µm; the n-type doped Ga2O3 epitaxial film 11 has a thickness of 200 nm; the Al2O3 gate dielectric layer 12 has a thickness of 10 nm; the Ti / Au source 13 and Ti / Au drain 14 have thicknesses of 120 nm; and the Ni / Au gate 15 has a thickness of 200 nm. 0.5 Zr 0.5 The thickness of the O2 ferroelectric thin film 22 is 6 nm to 15 nm, preferably 10 nm to 15 nm; the bottom electrode 21 and Hf 0.5 Zr 0.5 The O2 ferroelectric thin film 22 has a thickness ratio of 1:1 to 6:1. The circular trench (cylindrical in shape) has a width of 600 nm and a depth-to-width ratio of 5:1 to 25:1, preferably 10:1 to 15:1; the surface roughness Ra of the trench ranges from 0.5 nm to 3 nm, preferably 0.5 nm to 2 nm.

[0047] Example 1

[0048] A storage cell of the ferroelectric storage device of the present invention has the following structure: Figure 1 and Figure 2 This storage unit is a standard 1T1C structure, located in... <010> On an oriented β-Ga2O3 single-crystal substrate, a ferroelectric capacitor, a Ru metal interconnect layer, and a gallium oxide transistor integrated on the same substrate are combined. The ferroelectric capacitor is disposed within a circular trench region of the substrate and includes a bottom electrode and an Hf electrode sequentially disposed on the inner surface of the circular trench. 0.5 Zr0.5 The GaO ferroelectric thin film and top electrode. The gallium oxide transistor comprises an n-type doped Ga2O3 epitaxial film, an Al2O3 gate dielectric layer, a Ti / Au source, a Ti / Au drain, and a Ni / Au gate.

[0049] The fabrication process of the ferroelectric storage device includes four steps, such as... Figure 3 That is, the circular trench etching step S1, the Ga2O3 transistor fabrication step S2, and the Hf step. 0.5 Zr 0.5 The O2 ferroelectric capacitor fabrication process includes steps S3 and S4, which involve electrical interconnection. Step S1 comprises two steps: etching (S101) and passivation (S102). Step S2 comprises four steps: Ga2O3 substrate annealing (S201), n-type doped β-Ga2O3 single-crystal thin film growth (S202), Al2O3 gate dielectric fabrication (S203), and source / drain / gate electrode fabrication (S204). Step S3 includes W / WO... 0.5 Bottom electrode fabrication S301, Hf 0.5 Zr 0.5 O2 ferroelectric thin film preparation of S3O2, WO 0.5 The process involves four steps: S303 for fabricating the top electrode and S304 for post-annealing. Step S4 is the electrical interconnection and device integration step, namely the formation of the 1T1C memory cell and the integration of the memory device.

[0050] The specific process is as follows:

[0051] S1: In this embodiment, a thickness of 650 μm is selected. <010> Using oriented β-Ga2O3 single crystal as a substrate, periodically arranged circular trenches are formed on the substrate surface through inductively coupled plasma dry etching (ICP). The dry etching process cycle consists of 5 seconds of etching and 4 seconds of passivation.

[0052] S101: The etching process uses a BCl3 / SF6 / Ar mixed gas as the etching medium. Under the guidance of photoresist mask patterning, it achieves layer-by-layer removal of gallium oxide material with high anisotropy and high selectivity.

[0053] S102: The passivation stage uses carbon-containing gas C4F8 at a flow rate of 20 to 50 sccm. A fluorocarbon polymer film is deposited on the etched substrate surface as a passivation layer through plasma-induced deposition, physically isolating the etchant from the sidewalls. Following ICP etching, several cycles of atomic layer etching (ALE) are performed to atomically refine the sidewalls, strictly controlling the roughness Ra to within 2 nm. The opening width (W) of each trench is precisely controlled to 600 nm, and the depth (H) to 15 µm, achieving a high aspect ratio of 25:1. The surface roughness Ra of the trench sidewalls and bottom is strictly controlled to 2 nm. This high aspect ratio three-dimensional structure significantly increases the effective area of ​​the capacitor within a limited planar area, which is key to improving storage density.

[0054] S2: After completing the trench etching, gallium oxide transistors are fabricated in the area surrounding the trench.

[0055] S201: Clean <010> An oriented single-crystal substrate is placed in a reaction chamber and subjected to high-temperature annealing at 800°C to 950°C in an H2 or N2 atmosphere.

[0056] S202: A high-quality n-type doped β-Ga₂O₃ single-crystal thin film with a thickness of 200 nm was selectively epitaxially grown in a designated area using metal-organic chemical vapor deposition (MOCVD) as the channel layer. The temperature was stabilized within the optimal epitaxial window of 750℃ to 900℃, and high-purity nitrogen was used as the carrier gas, with the metal-organic precursor trimethylgallium (TMGa) and high-purity oxygen as the oxygen source precisely introduced. Simultaneously, to achieve precise control of the channel layer carrier concentration and electrical performance, the n-type doped Si precursor TMSi was introduced into the reaction chamber at a controlled flow rate, synchronously with the main precursor, and the molar flow ratio of the dopant source to the gallium source precursor was precisely adjusted to 10. -3 The process involves incorporating Si atoms into the growing crystal lattice. Throughout the growth process, precise control of the total molar flow rate of the precursor, reaction chamber pressure, and total gas flow rate enables synergistic regulation of chemical reaction kinetics, doping uniformity, and film growth rate. Selected area epitaxy (SIE) is used to confine film growth to the designed channel region, precisely controlling the final film thickness to 200 nm. After growth, in-situ annealing is performed in an oxygen-rich environment.

[0057] S203: Next, atomic layer deposition (ALD) is used to alternately introduce trimethylaluminum (TMA) and H2O precursors. Through multiple ALD cycles, each cycle includes: TMA pulse → N2 purging → H2O pulse → N2 purging, a 10 nm thick Al2O3 gate dielectric layer is grown on the channel surface. This dielectric layer has excellent interface quality.

[0058] S204: Source / drain ohmic contact electrodes and gate Schottky contact electrodes are formed sequentially through electron beam evaporation and stripping processes: the source / drain electrodes adopt a Ti (20 nm) / Au (100 nm) metal heterostructure and are annealed at 500°C for 60 seconds in N2 atmosphere to form ohmic contacts; the gate electrode adopts a Ni (50 nm) / Au (150 nm) metal heterostructure.

[0059] S3: After the transistor is fabricated, a three-dimensional ferroelectric capacitor is constructed in a circular trench.

[0060] S301: First, using ALD technology, a W / WO layer is conformally deposited on the substrate surface of the inner wall, bottom, and partially open portion of the trench. 0.5 Composite bottom electrode. The deposition process is carried out in a precisely temperature-controlled ALD reaction chamber, achieved by alternating introduction of high-purity precursors: First, a self-limiting surface reaction cycle consisting of "WF6 pulse → N2 purging → H2 pulse → N2 purging" is executed multiple times. Utilizing the reduction reaction of WF6 and H2, a dense tungsten layer with good conductivity and a thickness of 14 nm is uniformly grown on the three-dimensional surface of the trench. Immediately afterwards, a second oxidation process is performed in the same trench. Through multiple extended cycles of "WF6 pulse → N2 purging → H2 pulse → N2 purging → O3 pulse → N2 purging," the surface of the newly deposited tungsten layer undergoes controlled oxidation with the strong oxidant O3, transforming it into a 1 nm thick layer with a stoichiometric ratio close to WO3. 0.5 A tungsten oxide layer is formed. This results in a total thickness of 15 nm (W and WO3) within the circular trench. 0.5 Nanolayered composite electrode with a thickness ratio of 14:1.

[0061] S302: The W / WO prepared next 0.5 Hf deposited on bottom electrode 0.5 Zr 0.5 An O2 ferroelectric thin film was prepared by alternating introduction of tetra(dimethylamino)hafnium (TEMAHf), tetra(ethylmethylamino)zirconia (TDMAZr), and O3. An innovative atomic layer deposition (ALD) cycle sequence was employed, with each unit cycle consisting of an O3 pulse → a TEMAHf pulse → an N2 purging cycle → a TDMAZr pulse → an N2 purging cycle → an O3 pulse → an N2 purging cycle → a TDMAZr pulse → an N2 purging cycle → a TEMAHf pulse. This design, by alternately introducing different metal precursors and supplementing with intermediate oxidation steps, ensures uniform adsorption and diffusion of Hf and Zr atoms within the deep trenches. At a reaction temperature of 280°C, a 15 nm thick orthorhombic polycrystalline Hf phase was ultimately formed. 0.5 Zr 0.5 O2 ferroelectric thin film.

[0062] S303: In Hf 0.5 Zr 0.5WO3 continued to be deposited on the O2 ferroelectric thin film 0.5 The top electrode uses the same deposition process as the bottom electrode: first depositing a 1 nm thick WO3 layer. 0.5 Layer (with bottom electrode WO) 0.5 (Layer thickness matching), and then fill the remaining trench space through selective tungsten deposition process to form W layer; the ratio of the total thickness of the bottom electrode to the thickness of the ferroelectric film is 1:1, and the thickness uniformity deviation of the electrode and the ferroelectric film in the trench is the same, both are 1%.

[0063] S304: After all thin film deposition is completed, the device undergoes rapid thermal annealing at 480°C for 1 minute in an N2 atmosphere; this low-temperature annealing process activates Hf 0.5 Zr 0.5 The ferroelectricity of the O2 thin film promotes the formation of orthorhombic phases, while avoiding thermal damage to the already formed transistor ohmic contact and gate dielectric interface.

[0064] S4: Finally, back-end interconnect technology is used to achieve functional integration of the device. Specifically, the bottom electrode of the ferroelectric capacitor is exposed through a chemical mechanical polishing planarization process, and then the bottom electrode is electrically connected to the drain of the gallium oxide transistor using a metal interconnect process to form a complete 1T1C memory cell. The metal interconnect layer is a Ru metal thin film with the same thickness as the bottom electrode, 15 nm. An Al2O3 insulating layer is deposited between adjacent memory cells to separate them and achieve electrical isolation between the memory cells. Figure 1 As shown, based on this, multiple 1T1C memory cells are further arrayed and integrated along the row and column directions, and connected by word lines and bit lines to form a ferroelectric memory device.

[0065] S5: After completing the downstream interconnect process and forming a complete 1T1C ferroelectric memory cell, the fabricated device is subjected to systematic electrical performance tests to verify the ferroelectric characteristics, read / write performance, and reliability of the ferroelectric memory device of the present invention. Specifically, this includes transistor transfer characteristic testing S501, ferroelectric polarization characteristic testing S502, memory cell read / write characteristic testing S503, durability testing S504, and data retention characteristic testing S505.

[0066] S501: Perform transfer characteristic testing on the gallium oxide transistor. A semiconductor parameter analyzer is used to test the transistor's on-current and off-current. During the test, the source is grounded, and the drain and gate are connected to the corresponding test ports of the parameter analyzer. While maintaining the drain-source voltage at a preset value, the gate-source voltage is scanned, and the corresponding drain current I is recorded. D The scan range covers both the fully on and off states of the transistor; the corresponding drain current I when the transistor is in the fully on and off states.D This is the maximum on-state current I of the transistor. ON and the turn-off current I OFF .

[0067] S502: For the Hf 0.5 Zr 0.5 The polarization characteristics of O2 ferroelectric capacitors were tested. An electric field was applied to the ferroelectric capacitor using a ferroelectric analyzer, and the polarization-voltage (P–V) ferroelectric loop was measured relative to the actual residual polarization value P of the capacitor. r Characterization was performed. During the test, an electric field with an amplitude of 2 MV / cm was applied, and the test frequency was 1 kHz.

[0068] S503: Perform read / write performance testing on a complete 1T1C ferroelectric memory cell. A word line control voltage is applied to the gate via a semiconductor parameter analysis system to turn on the gallium oxide transistor, while read / write pulses are applied to the ferroelectric capacitor via the bit line.

[0069] S504: Polarization-flipping cycle test is performed on the memory cell to evaluate device durability. The ferroelectric capacitor is repeatedly polarized by periodically applying write and erase pulses of 2MV / cm, and the changes in the polarization window are monitored in real time.

[0070] S505: Perform I / O data retention performance testing on the device. Place the device on a temperature-controlled test platform and perform long-term I / O data retention tests under different temperature conditions, and periodically read the memory status to evaluate polarization stability.

[0071] The actual remanent polarization value P measured at 2 MV / cm in Example 1 r Maximum on-current I ON and the turn-off current I OFF Read / write voltage V r and V w Read and write time t r and t w The holding time and cycle number N at 25℃ and 200℃ are shown in Table 2. This embodiment fully utilizes the high critical breakdown electric field (>8 MV / cm) and excellent thermal stability of gallium oxide material, combined with Hf 0.5 Zr 0.5 The high Curie temperature characteristics of O2 ferroelectric materials have enabled the successful realization of high-performance non-volatile storage solutions suitable for extreme environments such as aerospace and automotive electronics.

[0072] The preparation and measurement methods used in Examples 2 to 108 are the same as those in Example 1. The corresponding structural parameters are shown in Table 1 and the performance parameters are shown in Table 2.

[0073] Table 1 Implementation Example Structure Parameters

[0074]

[0075]

[0076]

[0078]

[0079]

[0080]

[0081] Table 2 Performance Parameters of Implementation Examples

[0082]

[0083]

[0084]

[0085]

[0086]

[0087]

[0088] The above embodiments are merely preferred embodiments of the present invention, but the implementation of the present invention is not limited to the above embodiments. Any changes, modifications, substitutions, or combinations made without departing from the spirit and principle of the present invention, such as various combinations of solutions in the embodiments, should be considered equivalent replacements and are all within the protection scope of the present invention.

Claims

1. A storage cell for a ferroelectric storage device, characterized in that, It includes a gallium oxide transistor, a ferroelectric capacitor, and a Ru metal interconnect layer, with the memory cell disposed on a gallium oxide substrate; the ferroelectric capacitor is disposed within a circular trench region of the substrate, including a bottom electrode and an Hf electrode sequentially disposed on the inner surface of the circular trench. 0.5 Zr 0.5 The O2 thin film and top electrode; the bottom electrode of the ferroelectric capacitor and the drain of the gallium oxide transistor are electrically interconnected using a Ru metal interconnect layer to form a 1T1C memory cell.

2. The storage unit as claimed in claim 1, characterized in that, The aspect ratio of the circular groove is 5:1 to 25:1, preferably 10:1 to 15:1; the surface roughness Ra of the groove is in the range of 0.5 nm to 3 nm, preferably 0.5 nm to 2 nm.

3. The storage unit as described in claim 1, characterized in that, The bottom electrode is a composite heterolayer structure consisting of a metal layer and its metal oxide layer, preferably W / WO. x (0.5≤x≤2) or Ru / RuO2, the metal layer of the bottom electrode is in contact with the inner surface of the circular trench.

4. The storage unit as claimed in claim 1, characterized in that, The bottom electrode and top electrode have a symmetrical structure: when the bottom electrode is W / WO x When (0.5≤x≤2), the top electrode is WO. x / W (0.5≤x≤2); when the bottom electrode is Ru / RuO2, the top electrode is RuO2 / Ru; the bottom electrode and the top electrode have the same metal oxide layer, and the metal oxide layer of the top electrode is the same as that of the Hf 0.5 Zr 0.5 O2 ferroelectric thin film contact.

5. The storage unit as claimed in claim 1, characterized in that, Bottom electrode and Hf 0.5 Zr 0.5 The thickness ratio of O2 ferroelectric thin films ranges from 1:1 to 6:

1.

6. The storage unit as claimed in claim 1, characterized in that, Hf 0.5 Zr 0.5 The thickness of the O2 ferroelectric thin film is 5 nm to 20 nm, preferably 10 nm to 15 nm.

7. A method for fabricating a memory cell as described in any one of claims 1-6, characterized in that, Includes the following steps: S1: Prepare a smooth and flat gallium oxide substrate, and form circular trenches on its surface by dry etching; S2: An n-type doped gallium oxide thin film is deposited as an epitaxial layer on a gallium oxide substrate near the circular trench; then a discontinuous Al2O3 thin film is grown on the epitaxial layer as a gate dielectric layer by atomic layer deposition, and the gate material is deposited on the gate dielectric layer; finally, the source material and drain material are deposited on the non-gate dielectric layer region of the epitaxial layer respectively, and annealing is performed to complete the fabrication of the gallium oxide transistor; S3: Deposit the bottom electrode and Hf sequentially on the inner surface of the circular trench. 0.5 Zr 0.5 The O2 ferroelectric thin film and top electrode were prepared and then subjected to rapid annealing to complete the fabrication of the ferroelectric capacitor. S4: The bottom electrode of the ferroelectric capacitor and the drain of the gallium oxide transistor are electrically interconnected using a Ru metal interconnect layer to form a 1T1C memory cell; an Al2O3 insulating layer is deposited between adjacent memory cells to achieve electrical isolation between memory cells.

8. A ferroelectric storage device, characterized in that, It includes at least 1024 memory cells as described in claims 1-6, with adjacent memory cells electrically isolated by an Al2O3 insulating layer.

9. The ferroelectric storage device as described in claim 8, characterized in that, The memory cells are interconnected via word lines and bit lines to form a ferroelectric memory device.

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