Integrated circuit structure and photomask

Abstract

The application relates to an integrated circuit structure and a photoetching plate, the photoetching plate comprising: an LDMOS device area for forming an LDMOS device; a control circuit area for forming a control circuit; a first isolation structure pattern arranged around the LDMOS device area, the first isolation structure pattern being used for forming a first isolation structure for isolating the LDMOS device from the control circuit. The application can avoid parasitic effects between the LDMOS device and the control circuit by isolating the LDMOS device from the control circuit through the first isolation structure, thereby improving ESD protection failure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to an integrated circuit structure, and also to a photomask. Background Technology

[0002] For chips that integrate high-voltage power laterally diffused metal-oxide-semiconductor field-effect transistors (HV Power LDMOS), control circuits, and other high-voltage (HV) devices, the devices are prone to ESD (electrostatic discharge) protection failure. Summary of the Invention

[0003] Therefore, it is necessary to provide an integrated circuit structure that can improve ESD failure.

[0004] An integrated circuit structure includes a substrate in which an LDMOS device and a control circuit are formed; wherein the integrated circuit structure further includes a first isolation structure disposed between the LDMOS device and the control circuit, the first isolation structure being used to isolate the LDMOS device from the control circuit.

[0005] The aforementioned integrated circuit structure isolates the LDMOS device from the control circuit through the first isolation structure, thereby avoiding parasitic effects between the LDMOS device and the control circuit and improving ESD protection failure.

[0006] In one embodiment, the substrate has a second conductivity type, the LDMOS device includes a first well region, the control circuit includes a second well region, the first well region and the second well region have a first conductivity type; the first isolation structure is disposed between the first well region and the second well region, and the depth of the first isolation structure is greater than the depth of the first well region and the second well region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0007] In one embodiment, the LDMOS device further includes: a second conductivity type well region located within the first well region; a source region having a first conductivity type located within the second conductivity type well region; a lead-out region having a second conductivity type located within the second conductivity type well region; a drain region having a first conductivity type located within the first well region; a field oxide layer; and a gate.

[0008] In one embodiment, the doping concentration of the lead-out region is greater than the doping concentration of the well region of the second conductivity type.

[0009] In one embodiment, the doping concentration of the lead-out region is greater than the doping concentration of the substrate.

[0010] In one embodiment, the doping concentration of the source region is greater than the doping concentration of the first well region.

[0011] In one embodiment, the doping concentration of the source region is greater than the doping concentration of the second well region.

[0012] In one embodiment, the doping concentration of the drain region is greater than the doping concentration of the first well region.

[0013] In one embodiment, the doping concentration of the drain region is greater than the doping concentration of the second well region.

[0014] In one embodiment, a high-voltage device is also formed in the substrate, and the integrated circuit structure further includes a second isolation structure disposed between the high-voltage device and the control circuit, the second isolation structure being used to isolate the high-voltage device from the control circuit.

[0015] In one embodiment, the first isolation structure and the second isolation structure are deep trench isolation structures, which extend downward from the surface of the substrate, and the deep trench isolation structures have silicon oxide formed in the deep trenches to achieve insulation isolation.

[0016] In one embodiment, the integrated circuit structure further includes a third well region, in which the first isolation structure is disposed, the depth of the third well region being greater than the depth of the first isolation structure, and the third well region having a first conductivity type.

[0017] In one embodiment, the first isolation structure is formed by etching the deep trench and filling the deep trench with silicon oxide to form the deep trench isolation structure. Before filling, a first conductivity type ion is implanted around the deep trench to form a first conductivity type doped region. The first conductivity type doped region becomes the third well region after a thermal process.

[0018] In one embodiment, the integrated circuit structure further includes a fourth well region, in which the second isolation structure is disposed, the depth of the fourth well region being greater than the depth of the second isolation structure, and the fourth well region having a first conductivity type.

[0019] In one embodiment, the first isolation structure forms a closed structure around the LDMOS device.

[0020] In one embodiment, the second isolation structure forms a closed structure around the high-voltage device.

[0021] In one embodiment, the LDMOS device and the control circuit are packaged in the same package.

[0022] In one embodiment, the LDMOS device, control circuit, and high-voltage device are packaged in the same package.

[0023] In one embodiment,

[0024] It is also necessary to provide an encapsulation.

[0025] An integrated circuit structure is packaged in a package, the integrated circuit structure including a substrate, wherein an LDMOS device and a control circuit are formed in the substrate; wherein the integrated circuit structure further includes a first isolation structure disposed between the LDMOS device and the control circuit, the first isolation structure being used to isolate the LDMOS device from the control circuit.

[0026] The aforementioned package isolates the LDMOS device from the control circuit through the first isolation structure. Although the LDMOS device and the control circuit are encapsulated in the same package, it can achieve an effect close to that of a separate LDMOS device, thus avoiding parasitic effects between the LDMOS device and the control circuit and improving ESD protection failure.

[0027] In one embodiment, the substrate has a second conductivity type, the LDMOS device includes a first well region, the control circuit includes a second well region, the first well region and the second well region have a first conductivity type; the first isolation structure is disposed between the first well region and the second well region, and the depth of the first isolation structure is greater than the depth of the first well region and the second well region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0028] In one embodiment, a high-voltage device is also formed in the substrate, and the integrated circuit structure further includes a second isolation structure disposed between the high-voltage device and the control circuit, the second isolation structure being used to isolate the high-voltage device from the control circuit.

[0029] In one embodiment, the first isolation structure and the second isolation structure are deep trench isolation structures, which extend downward from the surface of the substrate, and the deep trench isolation structures have silicon oxide formed in the trenches to achieve insulation isolation.

[0030] In one embodiment, the integrated circuit structure further includes a third well region, in which the first isolation structure is disposed, the depth of the third well region being greater than the depth of the first isolation structure, and the third well region having a first conductivity type.

[0031] In one embodiment, the first isolation structure is formed by etching a deep trench and filling the deep trench with silicon oxide to form the deep trench isolation structure. Before filling, a first conductivity type ion is implanted around the deep trench to form a first conductivity type doped region. The first conductivity type doped region becomes the third well region after a thermal process.

[0032] In one embodiment, the integrated circuit structure further includes a fourth well region, in which the second isolation structure is disposed, the depth of the fourth well region being greater than the depth of the second isolation structure, and the fourth well region having a first conductivity type.

[0033] In one embodiment, the first isolation structure forms a closed structure around the LDMOS device.

[0034] In one embodiment, the second isolation structure forms a closed structure around the high-voltage device.

[0035] It is also necessary to provide a photomask.

[0036] A photomask includes: an LDMOS device region for forming an LDMOS device; a control circuit region for forming a control circuit; and a first isolation structure pattern disposed around the LDMOS device region, the first isolation structure pattern being used to form a first isolation structure that isolates the LDMOS device from the control circuit.

[0037] The integrated circuit structure fabricated using the above-mentioned photolithography can isolate the LDMOS device from the control circuit through the first isolation structure, thereby avoiding parasitic effects between the LDMOS device and the control circuit and improving ESD failure.

[0038] In one embodiment, the first isolation structure pattern is arranged around the LDMOS device region.

[0039] In one embodiment, the LDMOS device region is a rectangular area, and the first isolation structure pattern is a square structure.

[0040] In one embodiment, the LDMOS device region includes a first isolation structure pattern, a second conductivity type well region pattern, a lead-out region pattern, and a source region pattern, wherein the first isolation structure pattern, the second conductivity type well region pattern, the lead-out region pattern, and the source region pattern are box structures from the outside to the inside in the layout.

[0041] In one embodiment, the region surrounded by the second conductivity type well region is generally interdigitated, with each interdigitated region having a drain region pattern on the central axis. From the drain region to both sides, there are sequentially a first well region pattern, a second conductivity type well region pattern, a source region pattern, and a lead-out region pattern.

[0042] In one embodiment, the photomask further includes a high-voltage device region and a second isolation structure pattern disposed around the high-voltage device region.

[0043] In one embodiment, the high-voltage device region is a circular area, and the second isolation structure pattern is annular. Attached Figure Description

[0044] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0045] Figure 1 This is a layout of an exemplary integrated circuit structure;

[0046] Figure 2 This is a schematic diagram of a high-resistance indirection between the gate and substrate of a high-voltage power LDMOS device;

[0047] Figure 3 This is a partial cross-sectional schematic diagram of an integrated circuit structure in one embodiment;

[0048] Figure 4 This is a partial cross-sectional schematic diagram of the integrated circuit structure in another embodiment;

[0049] Figure 5 This is a layout of a photomask in one embodiment. Detailed Implementation

[0050] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0055] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0056] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0057] Figure 1 This is a layout of an exemplary integrated circuit structure. The integrated circuit structure includes a high-voltage power LDMOS device 110, a control circuit 120, and a high-voltage device 130. Due to parasitic effects between the high-voltage power LDMOS device 110 and the control circuit 120, and between the high-voltage power LDMOS device 110 and the high-voltage device 130, the entire integrated circuit structure is prone to latch-up and ESD (electrostatic discharge) protection failure. Weak points often appear in... Figure 1 The two double-headed arrows indicate the locations.

[0058] The inventor discovered through experiments that if... Figure 1 The high-voltage power LDMOS device 110 shown is individually packaged, and its state in the circuit is simulated by connecting a high-resistance junction between the gate and the substrate (sub) of the LDMOS (see [link]). Figure 2 ESD performance will be very good.

[0059] This application provides an integrated circuit structure, including a substrate, wherein the following are formed in the substrate:

[0060] LDMOS (Laterally Diffused Metal-Oxide Semiconductor) devices;

[0061] Control circuit;

[0062] The integrated circuit structure further includes a first isolation structure disposed between the LDMOS device and the control circuit, the first isolation structure being used to isolate the LDMOS device from the control circuit. The control circuit is a driving circuit for the LDMOS device, used to drive the LDMOS device to operate, for example, driving the LDMOS device to perform circuit functions such as analog-to-digital conversion (AC-DC).

[0063] The aforementioned integrated circuit structure isolates the LDMOS device from the control circuit through the first isolation structure, thereby avoiding parasitic effects between the LDMOS device and the control circuit and improving ESD protection failure.

[0064] In one embodiment of this application, the substrate has a second conductivity type, the LDMOS device includes a first well region, and the control circuit includes a second well region. The first and second well regions have a first conductivity type. A first isolation structure is disposed between the first and second well regions, and the depth of the first isolation structure is greater than the depth of the first and second well regions. In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0065] Figure 3 This is a partial cross-sectional schematic diagram of an integrated circuit structure in one embodiment. In this embodiment, the control circuit includes a second well region 222. The LDMOS device includes: a first well region 212, a second conductivity type well region 214 within the first well region 212, a source region 218 and a lead-out region 216 within the second conductivity type well region 214, a field oxide layer 211, and a gate 213. A first isolation structure 242 is disposed between the first well region 212 and the second well region 222. In one embodiment of this application, the first isolation structure 242 is a deep trench isolation structure (DTI). The first isolation structure 242 extends downward from the surface of the substrate 10, and the DTI achieves insulating isolation through silicon oxide (e.g., silicon dioxide) formed in the trench. The depth of the first isolation structure 242 is greater than the depth of the first well region 212 and the second well region 222 to achieve better isolation and avoid parasitic effects between the LDMOS device and the control circuit. The substrate 10 has a second conductivity type, the source region 218 has a first conductivity type, and the lead-out region 216 has a second conductivity type. The doping concentration of the lead-out region 216 is greater than the doping concentration of the second conductivity type well region 214 and the substrate 10.

[0066] In one embodiment of this application, the first well region 212 can serve as the drift region of the LDMOS device, and the second conductivity type well region 214 serves as the body region of the LDMOS device. Generally, the doping concentration of the drift region is low, lower than that of the source region 218, which is equivalent to forming a region with higher resistance between the source and drain, thereby improving the breakdown voltage and reducing the parasitic capacitance between the source and drain, which is beneficial to improving the frequency characteristics of the device.

[0067] In one embodiment of this application, the LDMOS device further includes a drain region ( Figure 3 (Not shown in the image). The drain region is located on the side of the gate 213 opposite to the source region 218, and is located in the first well region 212 (drift region).

[0068] In one embodiment of this application, the substrate 10 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 1 In the embodiment shown, the substrate 10 is made of monocrystalline silicon.

[0069] In one embodiment of this application, a gate dielectric layer is further provided between the gate 213 and the substrate 10. Figure 3 (Not shown in the image). In one embodiment of this application, the gate dielectric layer may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxides of nitride having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0070] In one embodiment of this application, the gate 213 is made of polysilicon. In other embodiments, metals, metal nitrides, metal silicides or other similar compounds may also be used as the material of the gate 213.

[0071] In one embodiment of this application, the source region 218 is an N+ region and the lead-out region 216 is a P+ region.

[0072] In one embodiment of this application, the LDMOS device is a high-voltage power LDMOS device.

[0073] Figure 4 This is a partial cross-sectional schematic diagram of the integrated circuit structure in another embodiment. Figure 4 In the illustrated embodiment, the integrated circuit structure further includes a third well region 244. A first isolation structure 242 is disposed within the third well region 244, the depth of the third well region 244 is greater than the depth of the first isolation structure 242, and the third well region 244 has a first conductivity type. Further configuring the third well region 244 provides a better isolation effect compared to simply configuring the first isolation structure 242.

[0074] In one embodiment of this application, the first isolation structure 242 is formed by etching a deep trench and filling the deep trench with silicon oxide to form a deep trench isolation structure. Before filling, ions of a first conductivity type are implanted by an ion implantation process to form a first conductivity type doped region around the deep trench. After undergoing a subsequent thermal process, the first conductivity type doped region becomes the third well region 244.

[0075] In one embodiment of this application, the first isolation structure 242 forms a closed structure around the LDMOS device.

[0076] In one embodiment of this application, a high-voltage device is further formed in the substrate. The integrated circuit structure also includes a second isolation structure disposed between the high-voltage device and the control circuit. The second isolation structure is used to isolate the high-voltage device from the control circuit.

[0077] In one embodiment of this application, the second isolation structure is a deep trench isolation structure. The deep trench isolation structure extends downward from the surface of the substrate, and silicon oxide is formed in the deep trench to achieve insulating isolation.

[0078] In one embodiment of this application, the integrated circuit structure further includes a fourth well region having a first conductivity type. A second isolation structure is disposed within the fourth well region, and the depth of the fourth well region is greater than the depth of the second isolation structure.

[0079] In one embodiment of this application, the second isolation structure is formed by etching a deep trench and filling the deep trench with silicon oxide to form a deep trench isolation structure. Before filling, ions of a first conductivity type are implanted by an ion implantation process, and the implanted first conductivity type ions become the fourth well region after undergoing a subsequent thermal process.

[0080] In one embodiment of this application, the second isolation structure forms a closed structure around the high-voltage device.

[0081] In one embodiment of this application, the LDMOS device and the control circuit are packaged in the same package.

[0082] In one embodiment of this application, the LDMOS device, control circuit, and high-voltage device are packaged in the same package.

[0083] This application provides a package that encapsulates an integrated circuit structure, the integrated circuit structure including a substrate, wherein the substrate has the following formed:

[0084] LDMOS devices;

[0085] Control circuit;

[0086] The integrated circuit structure further includes a first isolation structure disposed between the LDMOS device and the control circuit, the first isolation structure being used to isolate the LDMOS device from the control circuit.

[0087] The aforementioned package isolates the LDMOS device from the control circuit through the first isolation structure. Although the LDMOS device and the control circuit are encapsulated in the same package, it can achieve an effect close to that of a separate LDMOS device, thus avoiding parasitic effects between the LDMOS device and the control circuit and improving ESD protection failure.

[0088] In one embodiment of this application, the substrate has a second conductivity type, the LDMOS device includes a first well region, the control circuit includes a second well region, the first well region and the second well region have a first conductivity type; the first isolation structure is disposed between the first well region and the second well region, and the depth of the first isolation structure is greater than the depth of the first well region and the second well region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0089] In one embodiment of this application, a high-voltage device is further formed in the substrate, and the integrated circuit structure further includes a second isolation structure disposed between the high-voltage device and the control circuit, the second isolation structure being used to isolate the high-voltage device from the control circuit.

[0090] In one embodiment of this application, the first isolation structure and the second isolation structure are deep trench isolation structures. The deep trench isolation structures extend downward from the surface of the substrate, and silicon oxide is formed in the deep trenches to achieve insulation isolation.

[0091] In one embodiment of this application, the integrated circuit structure further includes a third well region, the first isolation structure is disposed within the third well region, the depth of the third well region is greater than the depth of the first isolation structure, and the third well region has a first conductivity type.

[0092] In one embodiment of this application, the first isolation structure is formed by etching a deep trench and filling the deep trench with silicon oxide to form the deep trench isolation structure. Before filling, a first conductivity type ion is implanted around the deep trench to form a first conductivity type doped region. The first conductivity type doped region becomes the third well region after a thermal process.

[0093] In one embodiment of this application, the integrated circuit structure further includes a fourth well region, the second isolation structure is disposed within the fourth well region, the depth of the fourth well region is greater than the depth of the second isolation structure, and the fourth well region has a first conductivity type.

[0094] In one embodiment of this application, the first isolation structure forms a closed structure around the LDMOS device.

[0095] In one embodiment of this application, the second isolation structure forms a closed structure around the high-voltage device.

[0096] This application provides a photomask for forming the aforementioned integrated circuit structure. The photomask includes:

[0097] The LDMOS device region is used to form LDMOS devices.

[0098] The control circuit area is used to form the control circuit.

[0099] A first isolation structure pattern is disposed around the LDMOS device region, and the first isolation structure pattern is used to form a first isolation structure that isolates the LDMOS device from the control circuit.

[0100] The integrated circuit structure fabricated using the above photolithography can isolate the LDMOS device from the control circuit through the first isolation structure, thereby avoiding parasitic effects between the LDMOS device and the control circuit and improving ESD protection failure.

[0101] Figure 5 This is a layout of a photomask in one embodiment, which includes an LDMOS device region 310, a control circuit region 320, and a high-voltage device region 330. A first isolation structure pattern 342 is disposed around the LDMOS device region 310, and a second isolation structure pattern 352 is disposed around the high-voltage device region 330. Figure 5 In the illustrated embodiment, the LDMOS device region 310 is a rectangular area, and the high-voltage device region 330 is a circular area. Figure 5 The cross-sectional view of the integrated circuit structure fabricated according to the layout shown at position A-A' can be referred to Figure 3 .

[0102] Please refer to the above as well. Figure 5 and Figure 3 The first isolation structure 242 (i.e., the first isolation structure pattern 342), the second conductivity type well region 214, the lead-out region 216, and the source region 218 are arranged in a rectangular structure from the outside to the inside in the layout (i.e., all are rectangular and one inside the other). The second isolation structure pattern 352 is annular. The region surrounded by the second conductivity type well region 214 (which is part of the LDMOS device) is generally interdigitated. Each interdigitated region has a drain region pattern on its central axis, and from the drain region to both sides are the patterns of the first well region 212, the second conductivity type well region 214, the source region 218, and the lead-out region 216, respectively.

[0103] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An integrated circuit structure, comprising a substrate, characterized in that, The substrate contains: LDMOS devices; Control circuit; High voltage devices; The integrated circuit structure further includes a first isolation structure and a third well region disposed between the LDMOS device and the control circuit. The first isolation structure is used to isolate the LDMOS device from the control circuit. The first isolation structure is disposed in the third well region. The depth of the third well region is greater than the depth of the first isolation structure. The third well region has a first conductivity type. The substrate has a second conductivity type, the LDMOS device includes a first well region, the control circuit includes a second well region, the first well region and the second well region have a first conductivity type; the first isolation structure and the third well region are disposed between the first well region and the second well region, and the depth of the first isolation structure and the third well region is greater than the depth of the first well region and the second well region; the first conductivity type and the second conductivity type are opposite conductivity types; the first isolation structure is a deep trench isolation structure, the deep trench isolation structure extends downward from the surface of the substrate, and silicon oxide is formed in the deep trench of the deep trench isolation structure to achieve insulating isolation; the third well region is separated from the first well region by the substrate, and the third well region is separated from the second well region by the substrate.

2. The integrated circuit structure according to claim 1, characterized in that, A high-voltage device is also formed in the substrate, and the integrated circuit structure further includes a second isolation structure disposed between the high-voltage device and the control circuit, the second isolation structure being used to isolate the high-voltage device from the control circuit.

3. The integrated circuit structure according to claim 2, characterized in that, The second isolation structure is a deep trench isolation structure.

4. The integrated circuit structure according to claim 1, characterized in that, The first isolation structure is formed by etching the deep trench and filling the deep trench with silicon oxide to form the deep trench isolation structure. Before filling, a first type of conductivity ions are implanted around the deep trench to form a first type of conductivity doped region. The first type of conductivity doped region becomes the third well region after a thermal process.

5. The integrated circuit structure according to claim 2, characterized in that, It also includes a fourth well region, in which the second isolation structure is disposed, the depth of the fourth well region is greater than the depth of the second isolation structure, and the fourth well region has a first conductivity type.

6. The integrated circuit structure according to claim 2, characterized in that, The first isolation structure forms a closed structure around the LDMOS device, and the second isolation structure forms a closed structure around the high-voltage device.

7. The integrated circuit structure according to claim 2, characterized in that, The LDMOS device, control circuit, and high-voltage device are packaged in the same package.

8. A photomask, characterized in that, For forming the integrated circuit structure according to any one of claims 1-7, the photomask comprises: The LDMOS device region is used to form LDMOS devices. The control circuit area is used to form the control circuit. A first isolation structure pattern is disposed around the LDMOS device region, and the first isolation structure pattern is used to form a first isolation structure that isolates the LDMOS device from the control circuit.

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