A communication system

Abstract

The application discloses a communication system, which comprises an antenna, a frequency converter module, a first processing chip and a second processing chip, wherein the second processing chip is connected with the first processing chip, the antenna and the frequency converter module, and is used for receiving a first control instruction sent by a host end, generating a corresponding first control message, and sending the first control message to the antenna and the frequency converter module, so that the antenna and the frequency converter module perform frequency adjustment; and / or the second processing chip is used for receiving a second control instruction sent by the first processing chip, generating a corresponding second control message, and sending the second control message to the antenna and the frequency converter module, so that the antenna and the frequency converter module perform operation, wherein the second control message comprises an angle switching message, a temperature reading message, a power reading message, a polarization mode switching message or a radio frequency switch control message. Through the above system, the communication system provided by the application can realize functions such as frequency switching and angle switching.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a communication system. Background Art

[0002] Frequency hopping (FH) is a commonly used spread spectrum method. It is a communication method that allows the carrier frequency of the transmitted signal between the sender and receiver to change discretely according to a prescribed pattern. FH technology ensures confidentiality and anti-interference capabilities in communications, which is particularly crucial in the military field. However, current communication systems using FH technology can interfere with other operations when switching frequencies, or other operations can interfere with the frequency switching process. Summary of the Invention

[0003] The present application provides a communication system, through which not only frequency switching but also angle switching, temperature reading, etc. can be realized. When frequency switching and angle switching and other operations need to be performed simultaneously, frequency switching is performed first and then angle switching and other operations according to the priority setting, thereby solving the problem of mutual interference when multiple tasks exist at the same time, affecting the efficiency of task execution, and the like.

[0004] In order to solve the above technical problems, the present application provides a communication system, which includes an antenna, a frequency converter module, a first processing chip and a second processing chip, wherein the second processing chip is respectively connected to the first processing chip, the antenna and the frequency converter module, and is used to receive a first control instruction sent by a host end, and generate a corresponding first control message based on the first control instruction, and send the first control message to the antenna and the frequency converter module, so that the antenna and the frequency converter module adjust the frequency according to the first control message; and / or,

[0005] The second processing chip is used to receive the second control instruction sent by the first processing chip, generate a corresponding second control message based on the second control instruction, and send the second control message to the antenna and converter module so that the antenna and converter module operate according to the second control message.

[0006] The second control message includes an angle switching message, a temperature reading message, a power reading message, a polarization switching message or a radio frequency switch control message.

[0007] The second processing chip is based on the logic implementation of FPGA (Field Programmable Gate Array).

[0008] The second processing chip includes: a deserialization circuit, a first processing circuit and a second processing circuit.

[0009] Among them, the deserialization circuit is used to receive the first control instruction and deserialize the first control instruction to obtain frequency information; the first processing circuit is respectively connected to the deserialization circuit and the antenna, and is used to generate a first control message according to the frequency information and send the first control message to the antenna; the second processing circuit is respectively connected to the deserialization circuit and the inverter module, and is used to generate a first control message according to the frequency information and send the first control message to the inverter module.

[0010] The first processing circuit includes: a first state machine, a first framing circuit, a first multiplexer, a first modulation circuit and a first demodulation circuit.

[0011] Among them, the first state machine is connected to the deserialization circuit, used to obtain the frequency information, and receive the trigger pulse sent by the host end or the switching instruction sent by the first processing chip, and perform scheduling operations according to the trigger pulse or switching instruction; the first framing circuit is connected to the first state machine, used to generate a first control message according to the frequency information; the first multiplexer is connected to the first framing circuit; the first modulation circuit is respectively connected to the first multiplexer and the antenna, and is used to receive the first control message when selected by the first multiplexer, and modulate the first control message to obtain a first modulated message, and send the first modulated message to the antenna; the first demodulation circuit is connected to the antenna, and is used to receive the feedback message from the antenna.

[0012] Wherein, when the first state machine is in the IDLE state, the first state machine switches from the IDLE state to the FRAME state in response to receiving the trigger pulse and frequency information sent by the host end. In the FRAME state, the first state machine controls the first framing circuit to perform and issue a framing operation, and issues a frequency switching instruction to the antenna;

[0013] Or, when the first state machine is in the IDLE state, the first state machine switches from the IDLE state to the SEND state in response to receiving the switching instruction sent by the first processing chip. In the SEND state, the first state machine forwards the switching instruction sent by the first processing chip.

[0014] The first processing circuit further includes: a first storage circuit and a second storage circuit.

[0015] Among them, the first storage circuit is respectively connected to the first processing chip, the first state machine and the first multiplexer, and is used to store the second control instruction sent by the first processing chip; the second storage circuit is respectively connected to the first processing chip and the first demodulation circuit, and is used to store the feedback message of the antenna; wherein, the feedback message includes the message actively returned by the antenna and / or the message passively returned by the antenna.

[0016] The first state machine is further configured to acquire a second control instruction and send the second control instruction to the first framing circuit to make the first framing circuit generate a second control packet according to the second control instruction, and the first modulation circuit receives the second control packet and modulates the second control packet to obtain a second modulation packet when selected by the first multiplexer, and sends the second modulation packet to the antenna.

[0017] The first processing circuit is configured to, when the first control instruction and the second control instruction are received simultaneously, first respond to the first control instruction to control the first state machine, the first framing circuit, the first multiplexer and the first modulation circuit to obtain a first modulation packet according to the first control instruction and send the first modulation packet to the antenna; after the first modulation packet is sent, switch the current state of the first state machine to determine whether the complete second control instruction is stored in the first storage circuit, and if so, control the first state machine, the first framing circuit, the first multiplexer and the first modulation circuit to obtain a second modulation packet according to the second control instruction and send the second modulation packet to the antenna.

[0018] The first modulation circuit comprises a configuration unit, a first encoding unit, a first check unit and a first serial unit.

[0019] The configuration unit is configured to receive message configuration information of the first control packet; the first encoding unit is configured to perform 8-bit / 10-bit encoding on the first control packet to obtain a first encoded packet; the first check unit is configured to generate a first check code corresponding to the first control packet; and the first serial unit is connected to the configuration unit, the first encoding unit and the first check unit respectively, and is configured to perform serial conversion on the message configuration information, the first check code and the first encoded packet to obtain a first serial packet, and send the first serial packet to the antenna.

[0020] The first modulation circuit comprises a configuration unit, a first encoding unit, a first check unit and a first serial unit.

[0021] The deserializing unit is connected to the antenna and is configured to perform deserializing operation on the feedback packet to obtain a first parallel packet; the first decoding unit is connected to the deserializing unit and is configured to perform 8-bit / 10-bit decoding on the first parallel packet to obtain a first decoded packet; the second check unit is connected to the first decoding unit and is configured to check the first decoded packet; and the storage unit is connected to the first decoding unit and is configured to store frame information in the first decoded packet.

[0022] The second processing circuit comprises a second state machine, a second framing circuit, a second multiplexer, a second modulation circuit and a second demodulation circuit.

[0023] The second state machine is connected with the deserializing circuit, is used for acquiring frequency information, receiving a trigger pulse sent by a host end or receiving a switching instruction sent by the first processing chip, and performing scheduling operation according to the trigger pulse or the switching instruction; the second group framing circuit is connected with the second state machine, is used for generating a first control message according to the frequency information; the second multiplexer is connected with the second group framing circuit; the second modulation circuit is connected with the second multiplexer and the frequency converter module respectively, is used for receiving the first control message when being selected by the second multiplexer, modulating the second control message to obtain a first modulation message, and sending the first modulation message to the frequency converter module; and the second demodulation circuit is connected with the frequency converter module, is used for receiving a feedback message of the frequency converter module.

[0024] The second processing circuit further includes a third storage circuit and a fourth storage circuit.

[0025] The third storage circuit is connected with the first processing chip, the second state machine and the second multiplexer respectively, and is used for storing a second control instruction sent by the first processing chip; and the fourth storage circuit is connected with the first processing chip and the second demodulation circuit respectively, and is used for storing the feedback message of the frequency converter module.

[0026] The second state machine is further used for acquiring the second control instruction, and sending the second control instruction to the second group framing circuit, so that the second group framing circuit generates a second control message according to the second control instruction, and the second modulation circuit receives the second control message when being selected by the second multiplexer, modulates the second control message to obtain a second modulation message, and sends the second modulation message to the frequency converter module.

[0027] The antenna includes a receiving antenna and a transmitting antenna, and is connected with the second processing chip respectively; and the frequency converter module includes an up-converter and a down-converter, and is connected with the second processing chip respectively.

[0028] The up-converter and the transmitting antenna form a transmitting channel, and the receiving antenna and the down-converter form a receiving channel.

[0029] The second processing chip is connected with the first processing chip through an AXI (Advanced eXtensible Interface) interface, is connected with the frequency converter module through a UART (Universal Asynchronous Receiver / Transmitter) interface, and is connected with the antenna through an SPI (Serial Peripheral Interface) interface.

[0030] The beneficial effects of the present application are: different from the prior art, the communication system provided by the present application comprises an antenna, a frequency converter module, a first processing chip and a second processing chip, wherein the second processing chip is connected to the first processing chip, the antenna and the frequency converter module respectively, is used for receiving a first control instruction sent by a host end, and generating a corresponding first control message based on the first control instruction, and sending the first control message to the antenna and the frequency converter module, so that the antenna and the frequency converter module perform frequency adjustment according to the first control message; and / or, the second processing chip is used for receiving a second control instruction sent by the first processing chip, and generating a corresponding second control message based on the second control instruction, and sending the second control message to the antenna and the frequency converter module, so that the antenna and the frequency converter module perform operation according to the second control message, wherein the second control message comprises an angle switching message, a temperature reading message, a power reading message, a polarization mode switching message or a radio frequency switch control message. Through the above-mentioned communication system, the second processing chip realized based on FPGA resources can perform frequency switching, angle switching and temperature reading operations, and according to the priority setting, when the frequency switching and angle switching, temperature reading instructions exist at the same time, the frequency switching is performed preferentially, and after the frequency switching is completed, the angle switching, temperature reading and other operations are performed, avoiding the problem of mutual interference between the host end and the first processing chip. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. Among them:

[0032] Figure 1 is a structural schematic diagram of a communication system first embodiment provided by the present application;

[0033] Figure 2 is a first interaction schematic diagram of the communication system provided by the present application;

[0034] Figure 3 is a second interaction schematic diagram of the communication system provided by the present application;

[0035] Figure 4 is a structural schematic diagram of the second processing chip provided by the present application;

[0036] Figure 5 is a structural schematic diagram of the first processing circuit provided by the present application;

[0037] Figure 6 is a structural schematic diagram of the first modulation circuit provided by the present application;

[0038] Figure 7 is a structural schematic diagram of a first demodulation circuit provided by the present application;

[0039] Figure 8 is a structural schematic diagram of a second processing circuit provided by the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0041] Reference Figure 1 , Figure 1 is a structural schematic diagram of a first embodiment of a communication system provided by the present application. The communication system 100 includes an antenna 101, a frequency converter module 102, a first processing chip 103, and a second processing chip 104. The second processing chip 104 is connected to the antenna 101, the frequency converter module 102, and the first processing chip 103, respectively.

[0042] In addition, in other embodiments, the communication system can further include a host end.

[0043] Specifically, the second processing chip 104 is in communication connection with the antenna 101 through an SPI interface, the second processing chip 104 is in communication connection with the frequency converter module 102 through a UART interface, the second processing chip 104 is in communication connection with the first processing chip 103 through an AXI interface, and the second processing chip 104 is in communication connection with the host end through a UART interface.

[0044] The UART interface between the frequency converter module 102 and the second processing chip 104 can achieve a transmission rate of 3.125M.

[0045] In some embodiments, the second processing chip 104 is configured to receive a first control instruction sent by the host end, generate a corresponding first control packet based on the first control instruction, and send the first control packet to the antenna 101 and the frequency converter module 102, so that the antenna 101 and the frequency converter module 102 perform frequency adjustment according to the first control packet.

[0046] Specifically, the first control packet is a frequency switching packet. The frequency switching packet issued by the host end can achieve a frequency hopping rate of 5000 hops / second.

[0047] In some embodiments, the second processing chip 104 is configured to receive the second control instruction sent by the first processing chip 103, generate a corresponding second control message based on the second control instruction, and send the second control message to the antenna 101 and the frequency converter module 102, so that the antenna 101 and the frequency converter module 102 operate according to the second control message.

[0048] Optionally, the second control message includes an angle switching message, a temperature reading message, a power reading message, a polarization mode switching message, or a radio frequency switch control message.

[0049] In some embodiments, the antenna 101 includes a receiving antenna and a transmitting antenna, which are respectively connected to the second processing chip 104; the frequency converter module 102 includes an up-converter and a down-converter, which are respectively connected to the second processing chip 104.

[0050] Among them, the up-converter and the transmitting antenna constitute a transmitting channel, and the receiving antenna and the down-converter constitute a receiving channel.

[0051] In some embodiments, the communication system 100 has multiple transmitting channels and multiple receiving channels, such as 4 transmitting and 4 receiving (4T4R).

[0052] In some embodiments, the antenna 101 is a KA phased array antenna, the interface of the KA phased array antenna is a single SPI, and the rate of the KA phased array antenna receiving a radio frequency signal is 20M.

[0053] In some embodiments, the up-converter and the down-converter in the frequency converter module 102 are configured to realize the conversion between intermediate frequency signals and radio frequency signals.

[0054] The following will be described in detail Figure 2 , Figure 2 is the first interaction schematic diagram of the communication system provided by the present application, and the interaction process includes:

[0055] S1: The host sends a first control instruction to the second processing chip.

[0056] S2: The second processing chip receives the first control instruction.

[0057] S3: The second processing chip generates a first control message based on the first control instruction.

[0058] S4: The second processing chip sends the first control message to the antenna.

[0059] S5: The second processing chip sends the first control message to the frequency converter module.

[0060] Steps S4 and S5 do not distinguish the order.

[0061] S6: The antenna adjusts the frequency based on the first control message.

[0062] S7: The inverter module performs frequency adjustment based on the first control message.

[0063] Steps S6 and S7 can be performed simultaneously.

[0064] Different from the existing technology, the communication system 100 provided in this application can enable the second processing chip 104 to generate a first control message by receiving the first control instruction sent by the host end, and then the antenna 101 and the frequency converter module 102 adjust the frequency based on the first control message to achieve frequency hopping.

[0065] The following combination Figure 3 , Figure 3 This is a second interaction diagram of the communication system provided by this application. The interaction process includes:

[0066] S1: The first processing chip sends a second control instruction to the second processing chip.

[0067] S2: The second processing chip receives the second control instruction.

[0068] S3: The second processing chip generates a second control message based on the second control instruction.

[0069] S4: The second processing chip sends the second control message to the antenna.

[0070] S5: The second processing chip sends the second control message to the inverter module.

[0071] There is no order distinction between steps S4 and S5.

[0072] S6: The antenna performs angle switching and other operations based on the second control message.

[0073] S7: The inverter module performs angle switching and other operations based on the second control message.

[0074] Steps S6 and S7 can be performed simultaneously.

[0075] Different from the existing technology, the communication system 100 provided in this application can enable the second processing chip 104 to receive the second control instruction of the first processing chip 103, and then generate a second control message based on the second control instruction, and send the second control message to the antenna 101 and the inverter module 102, so that the antenna 101 and the inverter module 102 perform angle switching, power reading or temperature reading and other operations based on the second control message.

[0076] See Figure 4 , Figure 41 is a schematic diagram of the structure of the second processing chip 104, which includes a deserialization circuit 201, a first processing circuit 202 and a second processing circuit 203, wherein the first processing circuit 202 is connected to the deserialization circuit 201 and the antenna 101, and the second processing circuit 203 is connected to the deserialization circuit 201 and the inverter module 102.

[0077] Specifically, the deserialization circuit 201 is used to receive a first control instruction and deserialize the first control instruction to obtain frequency information; the first processing circuit 202 is used to generate a first control message based on the frequency information and send the first control message to the antenna 101; the second processing circuit 203 is used to generate a first control message based on the frequency information and send the first control message to the inverter module 102.

[0078] In some embodiments, the host terminal and the second processing chip 104 are connected via a UART interface. Therefore, the first control instruction received by the second processing chip 104 is a serial instruction. The deserialization circuit 201 in the second processing chip 104 can deserialize the first control instruction to obtain frequency information, where the frequency information can correspond to the operating frequency of the communication system 100. The first control message is a frequency switching message, which is a message obtained by the first processing circuit 202 after framing and serializing the frequency information. The antenna 101 calculates the phase and performs phase compensation on the received first control message and caches the obtained frequency information. The frequency information can be a specific frequency point. The inverter module 102 obtains the frequency point information corresponding to the first control message through a Flash table lookup and caches the frequency point information. The host side sends a trigger pulse (for example, at a rate of 5000 pulses per second, a pulse with a pulse width of 1us is sent every 200us), and the second processing chip 104 sends a trigger instruction to the antenna 101 and the frequency converter module 102 according to the trigger pulse, so that the antenna 101 and the frequency converter module 102 perform a frequency switching operation, switching the frequency to the frequency corresponding to the frequency point information in the first control message, thereby realizing frequency switching.

[0079] See Figure 5 , Figure 5 3 is a schematic structural diagram of the first processing circuit 202 , which includes a first state machine 301 , a first framing circuit 302 , a first multiplexer 303 , a first modulation circuit 304 , a first demodulation circuit 305 , a first storage circuit 306 and a second storage circuit 307 .

[0080] Among them, the first state machine 301 is connected to the deserialization circuit 201; the first framing circuit 302 is connected to the first state machine 301; the first multiplexer 303 is connected to the first framing circuit 302; the first modulation circuit 304 is connected to the first multiplexer 303 and the antenna 101; the first demodulation circuit 305 is used to connect to the antenna 101; the first storage circuit 306 is respectively connected to the first processing chip 103, the first state machine 301 and the first multiplexer 303; the second storage circuit 307 is respectively connected to the first processing chip 103 and the first demodulation circuit 305.

[0081] Specifically, the first state machine 301 is used to obtain the frequency information, and to receive a trigger pulse sent by the host end or a switching instruction sent by the first processing chip 103, and to perform scheduling operations according to the trigger pulse or the switching instruction; the first framing circuit 302 is used to generate a first control message according to the frequency information; the first modulation circuit 304 is used to receive the first control message when selected by the first multiplexer 303, and to modulate the first control message to obtain a first modulated message, and to send the first modulated message to the antenna 101; the first demodulation circuit 305 is used to receive a feedback message from the antenna 101; the first storage circuit 306 is used to store a second control instruction sent by the first processing chip 103; and the second storage circuit 307 is used to store the feedback message from the antenna 101.

[0082] Specifically, the feedback message of the antenna 101 includes the message actively returned by the antenna 101 and / or the message passively returned by the antenna 101, such as the passively returned response frame, the actively returned fault reporting frame, etc. The feedback message is cached by the second storage circuit 307 in the second processing chip 104, and will be notified to the first processing chip 103 by scanning by the first processing chip 103, or by interrupting the reporting by the second processing chip 104.

[0083] Furthermore, the first processing chip 103 can receive feedback information sent by the antenna 101 at any time.

[0084] In addition, the receiving antenna in antenna 101 can receive feedback messages and obtain the feedback messages through polling by the first processing chip 103, or inform the first processing chip 103 through interrupt reporting by the second processing chip 104. The first processing chip 103 can monitor each received feedback message and ensure that no feedback message is lost through internal scanning.

[0085] In some embodiments, the first state machine 301 is also used to obtain a second control instruction and schedule the second control instruction to be sent to the first framing circuit 302, so that the first framing circuit 302 generates a second control message according to the second control instruction, and the first modulation circuit 304 receives the second control message when selected by the first multiplexer 303, modulates the second control message to obtain a second modulated message, and sends the second modulated message to the antenna 101.

[0086] Specifically, the first state machine 301 includes an IDLE state (idle state), a SEND state (sending state), a FRAME state (master control state) and a JUDGE state (judgment state).

[0087] In some embodiments, when the first state machine 301 is in the IDLE state, the first state machine 301 switches from the IDLE state to the FRAME state in response to receiving the trigger pulse and frequency information sent by the host end. In the FRAME state, the first state machine 301 controls the first framing circuit 302 to perform the framing operation and send it down, and sends a frequency switching instruction to the antenna 101.

[0088] In some embodiments, when the first state machine 301 is in the IDLE state, the first state machine 301 switches from the IDLE state to the SEND state in response to receiving a switching instruction sent by the first processing chip 103. In the SEND state, the first state machine 301 forwards the switching instruction sent by the first processing chip 103.

[0089] In some embodiments, the host sends a trigger pulse and corresponding frequency information. The first state machine 301 receives the frequency information and jumps from the IDLE state (starting point) to the FRAME state. It simultaneously sends a first control instruction to the antenna 101 and the frequency converter module 102 and continues to perform subsequent operations, ultimately achieving frequency switching. When it is detected that the first processing chip 103 needs to perform switching control, the first state machine 301 jumps to the SEND state and forwards the second control instruction issued by the first processing chip 103 in the SEND state.

[0090] It is worth noting that since the interface between the antenna 101 and the second processing chip 104 is an SPI interface, and the interface between the inverter module 102 and the second processing chip 104 is a UART interface, the formats of the first control message and the second control message received by the antenna 101 and the inverter module 102 are different.

[0091] In some embodiments, when the first processing circuit 202 receives the first control instruction and the second control instruction at the same time, the first processing circuit 202 first responds to the first control instruction to control the first state machine 301, the first framing circuit 302, the first multiplexer 303 and the first modulation circuit 304 to obtain the first modulation message according to the first control instruction and send the first modulation message to the antenna 101.

[0092] After the first modulation message is sent to the antenna 101, the current state of the first state machine 301 is switched to determine whether the complete second control instruction is stored in the first storage circuit 306. If yes, the first state machine 301, the first framing circuit 302, the first multiplexer 303 and the first modulation circuit 304 are controlled to obtain the second modulation message according to the second control instruction and send the second modulation message to the antenna 101.

[0093] In some embodiments, when the first state machine 301 detects that the host and the first processing chip 103 both need to be controlled, i.e., the first processing circuit 202 receives the first control instruction and the second control instruction at the same time, the control right is given to the second processing chip 104 according to the priority setting. The first processing circuit 202 first receives the first control instruction issued by the host and completes the corresponding frequency switching. Then, the first state machine 301 jumps to the JUDGE state to determine whether the complete second control instruction is stored in the first storage circuit 306 (i.e., whether the CNT counter of the first storage circuit 306 is equal to the message length set by the first processing chip 103 in advance). If yes, the first state machine jumps to the SEND state to issue the second control instruction to control the first state machine 301, the first framing circuit 302, the first multiplexer 303 and the first modulation circuit 304 to obtain the second modulation message according to the second control instruction and send the second modulation message to the antenna 101. When the sending is completed, the first state machine 301 jumps to the IDLE state and waits for the next first control instruction issued by the host and / or the second control instruction issued by the first processing chip 103. In other words, the first state machine 301 can solve the conflict problem of the first processing chip 103 and the host issuing instructions at the same time.

[0094] It is worth noting that since the first storage circuit 306 stores only one frame of data each time, and the first processing chip 103 writes data to the first storage circuit 306 and the second processing chip 104 reads data from the first storage circuit 306, the first processing chip 103 starts to write one frame of data and informs the second processing chip 104 of the byte length of the corresponding frame of data only when the number of data in the first storage circuit 306 is 0.

[0095] In addition, when it is detected that the data stored in the first storage circuit 306 is empty, the first processing chip 103 can perform write operation of the second control instruction at any time, and is not affected by the second processing chip 104.

[0096] In the above manner, it can be guaranteed that the control instructions issued by the first processing chip 103 and the host can be received and corresponding operations can be performed, and the problem of conflict can be avoided when the two issue instructions at the same time.

[0097] Referring to Figure 6 , Figure 6 is a structural schematic diagram of the first modulation circuit 304. The first modulation circuit 304 includes a configuration unit 401, a first encoding unit 402, a first check unit 403, and a first serial unit 404, wherein the first serial unit 404 is connected to the configuration unit 401, the first encoding unit 402, and the first check unit 403, respectively.

[0098] Specifically, the configuration unit 401 is configured to receive message configuration information of the first control packet; the first encoding unit 402 is configured to perform 8-bit / 10-bit encoding on the first control packet to obtain a first encoded packet; the first check unit 403 is configured to generate a first check code corresponding to the first control packet; and the first serial unit 404 is configured to perform serial conversion on the message configuration information, the first check code, and the first encoded packet to obtain a first serial packet, and send the first serial packet to the antenna 101.

[0099] Referring to Figure 7 , Figure 7 is a structural schematic diagram of the first modulation circuit 304. The first modulation circuit 304 includes a configuration unit 401, a first encoding unit 402, a first check unit 403, and a first serial unit 404, wherein the first serial unit 404 is connected to the configuration unit 401, the first encoding unit 402, and the first check unit 403, respectively.

[0100] Specifically, the configuration unit 401 is configured to receive message configuration information of the first control packet; the first encoding unit 402 is configured to perform 8-bit / 10-bit encoding on the first control packet to obtain a first encoded packet; the first check unit 403 is configured to generate a first check code corresponding to the first control packet; and the first serial unit 404 is configured to perform serial conversion on the message configuration information, the first check code, and the first encoded packet to obtain a first serial packet, and send the first serial packet to the antenna 101.

[0101] Specifically, the configuration unit 401 is configured to receive message configuration information of the first control packet; the first encoding unit 402 is configured to perform 8-bit / 10-bit encoding on the first control packet to obtain a first encoded packet; the first check unit 403 is configured to generate a first check code corresponding to the first control packet; and the first serial unit 404 is configured to perform serial conversion on the message configuration information, the first check code, and the first encoded packet to obtain a first serial packet, and send the first serial packet to the antenna 101.

[0102] In addition, the information input by the first modulation circuit 304 and the information output by the first demodulation circuit 305 are consistent.

[0103] See Figure 8 , Figure 8 2 is a schematic structural diagram of the second processing circuit 203 , which includes a second state machine 501 , a second framing circuit 502 , a second multiplexer 503 , a second modulation circuit 504 , a second demodulation circuit 505 , a third storage circuit 506 and a fourth storage circuit 507 .

[0104] Among them, the second state machine 501 is connected to the deserialization circuit 201; the second framing circuit 502 is connected to the second state machine 501; the second multiplexer 503 is connected to the second framing circuit 502; the second modulation circuit 504 is respectively connected to the second multiplexer 503 and the inverter module 102; the second demodulation circuit 505 is connected to the inverter module 102; the third storage circuit 506 is respectively connected to the first processing chip 103, the second state machine 501 and the second multiplexer 503; the fourth storage circuit 507 is respectively connected to the first processing chip 103 and the second demodulation circuit 505.

[0105] Specifically, the second state machine 501 is used to obtain the frequency information, and to receive a trigger pulse sent by the host end or a switching instruction sent by the first processing chip 103, and to perform scheduling operations according to the trigger pulse or the switching instruction; the second framing circuit 502 is used to generate a first control message according to the frequency information; the second modulation circuit 504 is used to receive the first control message when selected by the second multiplexer 503, and to modulate the second control message to obtain a first modulated message, and to send the first modulated message to the frequency converter module 102; the second demodulation circuit 505 is used to receive a feedback message from the frequency converter module 102; the third storage circuit 506 is used to store the second control instruction sent by the first processing chip 103; and the fourth storage circuit 507 is used to store the feedback message from the frequency converter module 102.

[0106] Specifically, the feedback message of the inverter module 102 includes a passively returned response frame and an actively returned fault reporting frame. The feedback message is cached by the fourth storage circuit 507 in the second processing chip 104 and will be notified to the first processing chip 103 through scanning by the first processing chip 103, or through interrupt reporting by the second processing chip 104.

[0107] Furthermore, the first processing chip 103 can receive feedback information sent by the antenna 101 at any time.

[0108] In some embodiments, the second state machine 501 is further configured to obtain a second control instruction, and send the second control instruction to the second framing circuit 502, so that the second framing circuit 502 generates a second control packet according to the second control instruction, and the second modulation circuit 504 receives the second control packet when selected by the second multiplexer 503, and modulates the second control packet to obtain a second modulation packet, and sends the second modulation packet to the frequency converter module 102.

[0109] In some embodiments, when the second state machine 501 is in the IDLE state, the second state machine 501 switches from the IDLE state to the FRAME state in response to receiving the trigger pulse and the frequency information sent by the host, and the second state machine 501 controls the second framing circuit 502 to perform the framing operation and issue in the FRAME state, and issues the frequency switching instruction to the frequency converter module 102.

[0110] In some embodiments, when the second state machine 501 is in the IDLE state, the second state machine 501 switches from the IDLE state to the SEND state in response to receiving the switching instruction sent by the first processing chip 103, and the second state machine 501 forwards the switching instruction sent by the first processing chip 103 in the SEND state.

[0111] In summary, the communication system provided by the present application can perform frequency switching, angle switching and temperature reading operations based on the second processing chip implemented by FPGA resources, and according to the priority setting, when the frequency switching and angle switching, temperature reading instructions exist at the same time, the frequency switching is performed first, and then the angle switching and temperature reading operations are performed after the frequency switching is completed, thereby avoiding the problem of mutual interference between the host and the first processing chip.

[0112] The above description is only an embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation based on the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A communication system, characterized in that: The communication system comprises: antenna; Inverter module; a first processing chip; a second processing chip, connected to the first processing chip, the antenna, and the inverter module, respectively, for receiving a first control instruction sent by a host end, generating a corresponding first control message based on the first control instruction, and sending the first control message to the antenna and the inverter module, so that the antenna and the inverter module perform frequency adjustment according to the first control message; The second processing chip is used to receive a second control instruction sent by the first processing chip, generate a corresponding second control message based on the second control instruction, and send the second control message to the antenna and the inverter module, so that the antenna and the inverter module operate according to the second control message; wherein the second control message includes an angle switching message, a temperature reading message, a power reading message, a polarization mode switching message, or a radio frequency switch control message; Among them, the second processing chip is implemented based on FPGA logic; the second processing chip is configured to give priority to processing the first control instruction when receiving the first control instruction and the second control instruction at the same time, and then process the second control instruction after completing the frequency adjustment.

2. The communication system according to claim 1, wherein: The second processing chip includes: a deserializing circuit, configured to receive the first control instruction and perform deserializing processing on the first control instruction to obtain frequency information; a first processing circuit, connected to the deserialization circuit and the antenna, respectively, configured to generate the first control message according to the frequency information, and send the first control message to the antenna; The second processing circuit is connected to the deserializing circuit and the inverter module respectively, and is configured to generate the first control message according to the frequency information and send the first control message to the inverter module.

3. The communication system according to claim 2, wherein: The first processing circuit includes: a first state machine, connected to the deserialization circuit, configured to obtain the frequency information, receive a trigger pulse sent by the host end or receive a switching instruction sent by the first processing chip, and perform a scheduling operation according to the trigger pulse or the switching instruction; a first framing circuit, connected to the first state machine, configured to generate the first control message according to the frequency information; a first multiplexer connected to the first set of frame circuits; a first modulation circuit, connected to the first multiplexer and the antenna, respectively, for receiving the first control message, modulating the first control message to obtain a first modulated message, and sending the first modulated message to the antenna when selected by the first multiplexer; The first demodulation circuit is connected to the antenna and is used to receive feedback messages from the antenna.

4. The communication system according to claim 3, wherein: When the first state machine is in the IDLE state, the first state machine switches from the IDLE state to the FRAME state in response to receiving the trigger pulse and the frequency information sent by the host end. In the FRAME state, the first state machine controls the first framing circuit to perform a framing operation and issue a framing instruction, and issues a frequency switching instruction to the antenna; Or, when the first state machine is in the IDLE state, the first state machine switches from the IDLE state to the SEND state in response to receiving the switching instruction sent by the first processing chip, and the first state machine forwards the switching instruction sent by the first processing chip in the SEND state.

5. The communication system according to claim 3, wherein: The first processing circuit further includes: a first storage circuit, connected to the first processing chip, the first state machine, and the first multiplexer, respectively, and configured to store a second control instruction sent by the first processing chip; a second storage circuit, connected to the first processing chip and the first demodulation circuit, respectively, and configured to store the feedback message from the antenna; wherein the feedback message includes a message actively returned by the antenna and / or a message passively returned by the antenna; In which, the first state machine is also used to obtain the second control instruction and schedule the second control instruction to be sent to the first framing circuit, so that the first framing circuit generates the second control message according to the second control instruction, and the first modulation circuit receives the second control message when selected by the first multiplexer, modulates the second control message to obtain a second modulated message, and sends the second modulated message to the antenna.

6. The communication system according to claim 4, wherein: When the first processing circuit receives the first control instruction and the second control instruction at the same time, the first processing circuit first responds to the first control instruction, controls the first state machine, the first framing circuit, the first multiplexer, and the first modulation circuit to obtain the first modulated message according to the first control instruction, and sends the first modulated message to the antenna; After the first modulated message is sent, the current state of the first state machine is switched to determine whether the complete second control instruction is stored in the first storage circuit. If so, the first state machine, the first framing circuit, the first multiplexer and the first modulation circuit are controlled to obtain the second modulated message according to the second control instruction, and the second modulated message is sent to the antenna.

7. The communication system according to claim 3, wherein: The first modulation circuit includes: A configuration unit, configured to receive message configuration information of the first control message; a first encoding unit, configured to perform 8-bit / 10-bit encoding on the first control message to obtain a first encoded message; A first verification unit, configured to generate a first verification code corresponding to the first control message; A first serial unit is connected to the configuration unit, the first encoding unit and the first verification unit respectively, and is used to serially convert the message configuration information, the first verification code and the first encoded message to obtain a first serial message, and send the first serial message to the antenna.

8. The communication system according to claim 3, wherein: The first demodulation circuit includes: a deserializing unit, connected to the antenna, configured to perform a deserializing operation on the feedback message to obtain a first parallel message; a first decoding unit, connected to the deserializing unit, configured to perform 8-bit / 10-bit decoding on the first parallel message to obtain a first decoded message; a second verification unit, connected to the first decoding unit, and configured to verify the first decoded message; A storage unit, connected to the first decoding unit, and configured to store the frame information in the first decoded message.

9. The communication system according to claim 3, wherein: The second processing circuit includes: a second state machine, connected to the deserialization circuit, configured to obtain the frequency information, receive a trigger pulse sent by the host end or receive a switching instruction sent by the first processing chip, and perform a scheduling operation according to the trigger pulse or the switching instruction; a second framing circuit, connected to the second state machine, configured to generate the first control message according to the frequency information; a second multiplexer connected to the second set of frame circuits; a second modulation circuit, connected to the second multiplexer and the frequency converter module, respectively, for receiving the first control message when selected by the second multiplexer, modulating the second control message to obtain a first modulated message, and sending the first modulated message to the frequency converter module; The second demodulation circuit is connected to the inverter module and is used to receive feedback messages from the inverter module.

10. The communication system according to claim 9, wherein: The second processing circuit further includes: a third storage circuit, connected to the first processing chip, the second state machine, and the second multiplexer, respectively, and configured to store a second control instruction sent by the first processing chip; a fourth storage circuit, connected to the first processing chip and the second demodulation circuit, respectively, and configured to store the feedback message of the inverter module; In which, the second state machine is also used to obtain the second control instruction and send the second control instruction to the second frame circuit, so that the second frame circuit generates the second control message according to the second control instruction, and the second modulation circuit receives the second control message when selected by the second multiplexer, modulates the second control message to obtain the second modulated message, and sends the second modulated message to the inverter module.

11. The communication system according to claim 1, wherein: The antenna includes a receiving antenna and a transmitting antenna, each of which is connected to the second processing chip; the frequency converter module includes an up-converter and a down-converter, each of which is connected to the second processing chip; The up-converter and the transmitting antenna form a transmitting channel, and the receiving antenna and the down-converter form a receiving channel.

12. The communication system according to claim 1, wherein: The second processing chip is connected to the first processing chip via an AXI interface, and the second processing chip is connected to the inverter module via a UART interface; the second processing chip is connected to the antenna via an SPI interface.

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