Single carrier signal generation method and system
Through the collaborative work of the baseband processor and the off-chip processor, the problem of low efficiency of single-carrier signal generation of FPGA chips under different satellite communication systems is solved, and a single-carrier signal generation method with fast generation and low-cost maintenance is realized.
Patent Information
- Application Number
- CN202211654618.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-22
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2042-12-22
AI Technical Summary
In the prior art, when using FPGA dedicated chips to implement baseband processors, different codes need to be written for different satellite communication physical layer systems, resulting in low efficiency in single-carrier signal generation and difficulty in maintaining the software and hardware systems.
Through the collaborative work of the baseband processor and the off-chip processor, the off-chip processor is used to generate configuration parameters and write them into the shared memory. The baseband processor performs state jumps and module data processing according to the configuration parameters to generate a single carrier signal, thereby realizing the rapid generation of different communication systems.
It improves the generation efficiency of single-carrier signals, reduces maintenance costs, and saves R&D and labor costs.
Smart Images
Figure CN116232541B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of wireless communication technology, and in particular to a method and system for generating a single-carrier signal based on a baseband processor and an off-chip processor. Background Art
[0002] Currently, wireless communication technology is widely used in scenarios such as satellite communications and mobile communications. Taking satellite communications as an example, across different communication systems, single-carrier physical layer waveforms vary. These waveforms require the generation of physical layer modulation waveforms based on the communication system. Modulation, demodulation, and decoding methods vary across different satellite communication systems. Typically, generating single-carrier modulation signals can be accomplished by a baseband processor.
[0003] For communication systems with slower information rates, the baseband processor can be implemented using a DSP (Digital Signal Processing) chip, etc., while for communication systems with higher information rates, the baseband processor is generally implemented using a dedicated FPGA (Field Programmable Gate Array) chip.
[0004] However, the inventors of this application discovered during their research that when using a dedicated FPGA chip to implement a baseband processor, due to the poor versatility of the FPGA, different codes need to be written for different satellite communication physical layer systems to achieve the generation of a single-carrier modulated signal. Therefore, there are problems such as low efficiency in generating a single-carrier signal and difficulty in maintaining the hardware and software systems. Summary of the Invention
[0005] In response to the above problems, the purpose of the present invention is to provide a single-carrier signal generation method and system, which is based on the collaboration between the baseband processor and the off-chip processor to quickly generate baseband single-carrier modulation signals for different physical layer communication systems, thereby improving the generation efficiency of single-carrier signals. At the same time, it is also beneficial to long-term maintenance and saves R&D and labor costs.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] In a first aspect, the present application provides a method for generating a single carrier signal, the method comprising:
[0008] The off-chip processor determines the data frame structure and time slot structure corresponding to the single carrier signal according to the single carrier signal generated as needed;
[0009] The off-chip processor generates configuration parameters corresponding to the single carrier signal according to the data frame structure and the time slot structure, and writes the configuration parameters into a shared memory between the off-chip processor and the baseband processor, wherein the configuration parameters include a jump state and a jump condition of a data transmission state machine of the baseband processor, and a communication module selection enable switch under each jump state;
[0010] The off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated as needed, and writes the frame header data and the communication module data into the shared memory;
[0011] The baseband processor obtains the data to be sent and reads the configuration parameters and the frame header data from the shared memory to implement state jumps under the data transmission state machine. In each jump state, the baseband processor reads the corresponding communication module data according to the communication module selection enable switch, processes the read communication module data, and generates a single carrier signal with the data frame structure and time slot structure.
[0012] In one implementation of the present application, the method further includes: the baseband processor reports the data transmission status information of the single carrier signal to the off-chip processor through an interrupt signal, so that the off-chip processor can verify whether the baseband processor correctly generates the single carrier signal.
[0013] In one implementation of the present application, the method further includes: when the off-chip processor determines that the baseband processor does not correctly generate a single carrier signal, readjusting the configuration parameters and the communication module data, and writing them into the shared memory for the baseband processor to read and process again.
[0014] In one implementation of the present application, the off-chip processor determines the physical layer single-carrier signal that needs to be generated based on a communication system selection signal sent by a host computer.
[0015] In one implementation of the present application, the shared memory is a dual-port RAM shared by the baseband processor and the off-chip processor, each address of the dual-port RAM shared by the baseband processor and the off-chip processor corresponds to a jump state of the data sending state machine, and the data stored at each address is combined in bits to select an enable switch for the communication module in the jump state.
[0016] In one implementation of the present application, the communication module includes interleaving, scrambling and channel coding.
[0017] In one implementation of the present application, the single carrier form includes FDD or TDD.
[0018] In one implementation of the present application, the single-carrier pilot mode includes continuous pilot or distributed pilot.
[0019] In a second aspect, the present application provides a single-carrier signal generation system, comprising a baseband processor, an off-chip processor, and a shared memory;
[0020] The off-chip processor is configured to determine a data frame structure and a time slot structure corresponding to a single carrier signal generated as needed;
[0021] The off-chip processor is further configured to generate configuration parameters corresponding to the single carrier signal according to the data frame structure and the time slot structure, and write the configuration parameters into a shared memory between the off-chip processor and the baseband processor, wherein the configuration parameters include a jump state and a jump condition of a data transmission state machine of the baseband processor, and a communication module selection enable switch under each jump state;
[0022] The off-chip processor is further configured to generate corresponding frame header data and communication module data according to the single carrier signal generated as needed, and write the frame header data and the communication module data into the shared memory;
[0023] The baseband processor is used to obtain the data to be sent, and read the configuration parameters and the frame header data from the shared memory, to realize the state jump under the data transmission state machine, and in each jump state, read the corresponding communication module data according to the communication module selection enable switch, process the read communication module data, and generate the single carrier signal of the data frame structure and time slot structure.
[0024] In one implementation of the present application, the baseband processor is an FPGA; the off-chip processor is a DSP, a CPU or an MCU outside the FPGA.
[0025] Due to the adoption of the above technical solution, the present invention has the following advantages: the off-chip processor in the application solution of the present invention generates configuration parameters according to the single-carrier signal to be generated as needed, and writes them into the shared memory, and then the baseband processor reads the configuration parameters, realizes the state jump of the data transmission state machine and the processing of the module data in each state according to the configuration parameters, and generates the required single-carrier signal. Compared with the existing technology, there is no need to change the hardware platform and code, which can realize the rapid generation of single-carrier signals of different communication systems, thereby improving efficiency and effectively reducing maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 1 is a schematic structural diagram of a single carrier generation system provided by an embodiment of the present invention;
[0027] Figure 21 is a flow chart of a single carrier generation method provided by an embodiment of the present invention;
[0028] Figure 3 1 is a schematic diagram of the structure and signal flow of a single carrier generation system provided by an embodiment of the present invention;
[0029] Figure 4 yes Figure 3 A schematic diagram of the processing flow of the off-chip processor in the embodiment;
[0030] Figure 5 yes Figure 3 A schematic diagram of a processing flow of a baseband processor in an embodiment;
[0031] Figure 6 yes Figure 3 Schematic diagram of the state transition of the transmitter state machine of the baseband processor;
[0032] Figure 7 yes Figure 3 Schematic diagram of pilot and scrambling code generation in an embodiment;
[0033] Figure 8 This is a schematic diagram of a data frame structure in an embodiment of the present invention;
[0034] Figure 9 This is another schematic diagram of a data frame structure in an embodiment of the present invention. DETAILED DESCRIPTION
[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present invention.
[0036] In the scenario where the existing technology uses FPGA dedicated chips to implement baseband processors, due to the poor versatility of FPGA, different codes need to be written for different satellite communication physical layer systems to achieve the generation of single-carrier modulation signals. Therefore, there are problems such as low efficiency of single-carrier signal generation and difficulty in maintaining software and hardware systems. The present application provides a single-carrier signal generation method and system based on a baseband processor and an off-chip processor, including: the off-chip processor determines the data frame structure and time slot structure corresponding to the single-carrier signal according to the single-carrier signal generated as needed; the off-chip processor generates configuration parameters corresponding to the single-carrier signal according to the data frame structure and time slot structure, and writes the configuration parameters into a shared memory between the off-chip processor and the baseband processor. The memory, the configuration parameters include the jump state and jump conditions of the data transmission state machine of the baseband processor, and the communication module selection enable switch under each jump state; the off-chip processor generates corresponding frame header data and communication module data according to the single-carrier signal generated as needed, and writes the frame header data and the communication module data into the shared memory; the baseband processor obtains the data to be sent, and reads the configuration parameters and the frame header data from the shared memory to realize the state jump under the data transmission state machine, and in each jump state, reads the corresponding communication module data according to the communication module selection enable switch, processes the read communication module data, and generates the single-carrier signal of the data frame structure and time slot structure. The technical solution of the present application can improve the generation efficiency of the single-carrier signal, and is also conducive to long-term maintenance, saving R&D and labor costs.
[0037] As described in the background, satellite communication systems of different architectures employ varying modulation, demodulation, and encoding / decoding methods. Generally, modulation and demodulation in slower communication systems can be implemented on chips such as DSPs or CPUs, while higher-speed communication systems can be implemented on FPGAs. However, FPGA-based systems often suffer from poor general performance and cannot effectively implement single-carrier waveforms at the physical layer for different communication architectures using a unified hardware platform and software code.
[0038] In order to overcome the above-mentioned defects, the technical solution of this application will provide a unified hardware platform that can quickly realize the generation of physical layer single carrier for different satellite communication systems without modifying the program code of the existing FPGA-implemented baseband processor, thereby reducing maintenance costs.
[0039] like Figure 1 As shown, in one embodiment of the present application, a single carrier signal generation system is provided. The single carrier signal generation system can serve as a unified hardware platform for generating physical layer single carriers under different communication systems.
[0040] Specifically, in Figure 1 The single-carrier signal generation system in the embodiment includes: a baseband processor 101 , an off-chip processor 102 , and a shared memory 103 .
[0041] The baseband processor 101 can be any chip with digital signal storage, transmission, and computational processing capabilities, such as a DSP, CPU, etc. Of course, in scenarios where higher data transmission rates are required, the baseband processor 101 can preferably be a dedicated FPGA chip. In the subsequent embodiments of this application, the baseband processor 101 will be exemplified by an FPGA.
[0042] The off-chip processor 102 is an off-chip processor relative to the baseband processor 101. The off-chip processor 102 may be a chip such as a DSP, a CPU, or an MCU.
[0043] Shared memory 103 is a memory that can be accessed jointly by baseband processor 101 and off-chip memory 102 for data writing and reading. In some scenarios, shared memory 103 can be built into baseband processor 101 or off-chip processor 102. For example, if baseband processor 101 is an FPGA, shared memory 103 can be RAM built into the FPGA.
[0044] In the embodiment of the present application, the working principle of the single carrier signal generation system is as follows.
[0045] The off-chip processor 102 is configured to determine the data frame structure and time slot structure corresponding to the single carrier signal generated according to the needs.
[0046] The off-chip processor 102 is also used to generate configuration parameters corresponding to the single carrier signal based on the data frame structure and time slot structure, and write the configuration parameters into the shared memory 103 between the off-chip processor 102 and the baseband processor 101. The configuration parameters include the jump state and jump conditions of the data sending state machine of the baseband processor, and the communication module selection enable switch under each jump state.
[0047] The off-chip processor 102 is further configured to generate corresponding frame header data and communication module data according to the single carrier signal generated as needed, and write the frame header data and communication module data into the shared memory 103 .
[0048] The baseband processor 101 is used to obtain data to be sent and read configuration parameters and frame header data from the shared memory 103 to realize state jumps under the data transmission state machine. In each jump state, the baseband processor 101 reads the corresponding communication module data according to the communication module selection enable switch, processes the read communication module data, and generates a single carrier signal with a data frame structure and a time slot structure.
[0049] Corresponding to Figure 1 The system provided in the embodiment, on the other hand, the embodiment of the present application also provides an application Figure 1 The system's single-carrier signal generation method. For details, please refer to Figure 2 .
[0050] like Figure 2 As shown, in one embodiment of the present application, a single carrier generation method is provided.
[0051] The single carrier generation method includes:
[0052] S21, the off-chip processor determines the data frame structure and time slot structure corresponding to the single carrier signal according to the single carrier signal generated as needed;
[0053] Specifically, the off-chip processor may select a signal according to the communication system sent by the host computer and determine the physical layer single carrier signal that needs to be generated.
[0054] In some more detailed embodiments of the present application, the single carrier signal may include a single carrier in FDD or TDD format. The pilot mode may include continuous pilot or distributed pilot.
[0055] S22, the off-chip processor generates configuration parameters corresponding to the single carrier signal based on the data frame structure and the time slot structure, and writes the configuration parameters into a shared memory between the off-chip processor and the baseband processor. The configuration parameters include the jump state and jump conditions of the data transmission state machine of the baseband processor, and the communication module selection enable switch under each jump state;
[0056] Specifically, in some embodiments of the present application, the shared memory is a dual-port RAM shared by the baseband processor and the off-chip processor, each address of the dual-port RAM shared by the baseband processor and the off-chip processor corresponds to a jump state of the data sending state machine, and the data stored at each address is combined bit by bit to select an enable switch for the communication module in the jump state.
[0057] In the embodiments of the present application, the transition states of the data transmission state machine generally include an idle state and a data transmission state. In the data transmission state, the baseband processor transmits the generated single-carrier data to the outside. In the data transmission state, the baseband processor can transmit different data, such as frame header data, frame information data, or channel coded data, controlled by the communication module's selection enable switch.
[0058] In the embodiment of the present application, different data processing can be achieved through multiple communication modules, and the communication modules can include interleaving, scrambling or channel coding, etc.
[0059] S23, the off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated as needed, and writes the frame header data and communication module data into the shared memory;
[0060] S24, the baseband processor obtains the data to be sent, and reads the configuration parameters and frame header data from the shared memory to realize the state jump under the data transmission state machine. In each jump state, the corresponding communication module data is read according to the communication module selection enable switch, and the read communication module data is processed to generate a single carrier signal with a data frame structure and a time slot structure.
[0061] In an embodiment of the present application, in order to enable the baseband processor to correctly generate the required baseband signal, the method may further include:
[0062] S25, the baseband processor reports the data transmission status information of the single carrier signal to the off-chip processor through an interrupt signal, so that the off-chip processor can verify whether the baseband processor correctly generates the single carrier signal. And
[0063] S26, when the off-chip processor determines that the baseband processor does not correctly generate the single carrier signal, it readjusts the configuration parameters and communication module data and writes them into the shared memory for the baseband processor to read and process again.
[0064] That is, when the off-chip processor verifies that the baseband processor fails to correctly generate the single carrier signal, it returns to execute S22-S24 until the baseband processor generates all correct single carrier signals.
[0065] In the above-mentioned single-carrier signal generation system and method in the embodiment of the present application, the off-chip processor generates configuration parameters according to the single-carrier signal to be generated, and writes them into the shared memory. The baseband processor then reads the configuration parameters, and implements the state jump of the data transmission state machine and the processing of the module data in each state according to the configuration parameters to generate the required single-carrier signal. Compared with the existing technology, there is no need to change the hardware platform and code to achieve rapid generation of single-carrier signals for different communication systems, thereby improving efficiency and effectively reducing maintenance costs.
[0066] The above-mentioned single-carrier signal generation system and method are described below in some more detailed embodiments of the present application, and the advantages of the present application are described.
[0067] The single-carrier generation system provided in an embodiment of the present application includes a baseband processor, an off-chip processor, and a shared memory.
[0068] In one embodiment of the present application, Figure 3As shown, the baseband processor uses an FPGA as an example. The off-chip processor is an off-chip DSP or CPU outside the FPGA. The shared memory is a dual-port RAM built into the FPGA.
[0069] Figure 3 The signal flow of the single-carrier signal generation system in the embodiment is as follows:
[0070] In step (1), the off-chip DSP or CPU determines the physical layer single carrier signal to be generated according to the communication system selection signal sent by the host computer, and determines the data frame structure and time slot structure corresponding to the single carrier signal.
[0071] In step (2), the off-chip DSP or CPU generates configuration parameters corresponding to the single carrier signal according to the data frame structure and time slot structure, and writes the configuration parameters into the built-in dual-port RAM of the FPGA. The configuration parameters include the jump state and jump conditions of the FPGA's data transmission state machine, as well as the communication module selection enable switch under each jump state.
[0072] Specifically, in Figure 3 In the system of the embodiment, the data of each communication module may be frame header data, pilot data, channel coding, interleaving or scrambling, etc. In an optional scenario, more or fewer communication modules may be selected, which is not limited in the embodiment of the present application.
[0073] In step (3), the off-chip DSP or CPU generates corresponding frame header data and communication module data according to the single carrier signal generated as needed, and writes the frame header data and communication module data into the RAM.
[0074] Specifically, the frame header data is used for physical frame synchronization, and the communication module data can be scrambled code data used for scrambling, for example.
[0075] In step (4), the FPGA obtains the data to be sent and reads the configuration parameters from the built-in dual-port RAM to realize the state jump under the data transmission state machine. In each jump state, the corresponding communication module data is read according to the communication module selection enable switch, and the read communication module data is processed to generate a single carrier signal with a corresponding data frame structure and time slot structure.
[0076] Specifically, in the embodiment of the present application, each address in the dual-port RAM corresponds to a jump state of the data transmission state machine. The data stored at each address is combined bit by bit to select the communication module enable switch in the jump state (such as: interleaving, scrambling, channel coding, etc. module enable), as well as the configuration data corresponding to each module. The FPGA determines which modules to enable in each jump state based on the data frame to be generated and allocates the configuration data to the corresponding communication module. At the same time, for each strip state, the parameter RAM address corresponding to the next state is also given to ensure the normal state jump of the state machine.
[0077] The FPGA data transmission state machine jumps to the next state through the state machine start enable (FPGAStartEn) configured by the off-chip DSP or CPU. The state of the state machine can include the idle state and the data transmission state.
[0078] Among them, in the data transmission state of the FPGA state machine, frame header data, frame information data, or channel coded data can be sent. The specific type of data to be sent is determined by the transmission enable of different data types configured by the DSP or CPU. The amount of data sent for each data type can also be determined by the DSP or CPU configuration. The data transmission state machine can also be controlled to jump between the idle state and the data transmission state. In this way, the FPGA transmitter can complete the physical frame generation of continuous pilot and distributed pilot according to the jump method configured by the DSP or CPU, and can also complete the frame structure generation of FDD mode and TDD mode.
[0079] For data with different data types and modulation modes, the DSP or CPU can configure the FPGA according to the modulation mode corresponding to the data type, and the FPGA will complete the phase mapping of the modulated data.
[0080] In step (5), the FPGA reports the data transmission status information of the single carrier signal to the off-chip DSP or CPU via an interrupt signal, so that the off-chip DSP or CPU can verify whether the FPGA correctly generates the single carrier signal.
[0081] In step (6), the off-chip DSP or CPU chip responds to the interrupt sent by the FPGA chip, reads the status information reported by the FPGA chip, and determines whether the FPGA responds correctly based on the reported status information. If it is correct, no intervention will be made. If it is incorrect, the configuration parameters will be adjusted based on the reported information.
[0082] In step (7), the off-chip DSP or CPU chip determines whether the physical layer single carrier signal is generated based on the status parameters reported by the FPGA chip. If not, steps (2) to (6) are repeated until the physical layer single carrier signal is generated.
[0083] From the above steps (1) to (7), it can be seen that the processing flow of the single carrier signal generation method of the present application is a collaborative processing process in which the baseband processor (FPGA) interacts with the off-chip processor (off-chip DSP or CPU). Figure 4 As shown, the processing flow of the baseband processor is as follows Figure 5 Indicates.
[0084] Specifically, in Figure 4 In the example, the processing flow of the off-chip processor, taking an off-chip DSP or CPU as an example, includes:
[0085] 401, the off-chip DSP or CPU determines whether it receives a communication system selection signal from the host computer.
[0086] If not, it will be in waiting state. If so, execute 402.
[0087] 402. The off-chip DSP or CPU generates a corresponding frame structure and time slot structure.
[0088] 403 , the off-chip DSP or CPU generates configuration parameters of the FPGA's transmit state machine and stores them in the FPGA's shared RAM.
[0089] 404, set FPGAStartEn to 1 to start the FPGA modulation program.
[0090] 405, waiting for the data sending status reported by the FPGA through an interrupt.
[0091] 406 , the off-chip DSP or CPU determines whether the data frame has been sent.
[0092] If yes, process and exit. If no, return 405.
[0093] Accordingly, Figure 5 The FPGA processing flow includes:
[0094] The FPGA is in idle state (Idle) in advance.
[0095] 501, FPGA determines whether FPGAStartEn is set to 1.
[0096] If so, execute 502, otherwise it is in a waiting state.
[0097] 502, read the configuration parameters written into the RAM by the off-chip DSP or CPU.
[0098] 503. Generate and send a single carrier signal according to the configuration parameters.
[0099] 504, FPGA determines whether the data frame is sent completely.
[0100] If yes, execute 505, otherwise return 503.
[0101] 505, FPGA checks whether FPGAStartEn is set to 1.
[0102] If yes, return to 502, otherwise the FPGA sending state machine enters the idle state. More specifically, in the embodiment of the present application, the jump state and jump condition of the FPGA are as follows: Figure 6 Indicates.
[0103] Below, in one embodiment of the present application, the processing flow of the present application is explained by taking the following specific parameters of the baseband single-carrier signal to be generated as an example.
[0104] Specifically, the single carrier to be generated is in FDD form, the pilot is a distributed pilot mode, the pilot symbol length is 1024, and a pilot symbol is inserted every 15 data symbols. The pilot is modulated by BPSK, and the data symbol is modulated by QPSK. The pilot sequence generating polynomial is: f(x) = 1 + X + X 2 +X 8 +X 12 , the initial phase is: 12'b101010110011, the data part scrambled pseudo-random sequence generator polynomial is f(x)=1+X 3 +X 25 , the initial phase is: 1, the channel coding adopts LDPC coding with a code length of 2560 bits and a code rate of 1 / 3.
[0105] The system's processing flow includes:
[0106] In step (A), the off-chip DSP or CPU determines the physical layer single carrier signal to be generated according to the communication system selection signal sent by the host computer, and determines the data frame structure and time slot structure corresponding to the single carrier signal.
[0107] Specifically, the data frame structure in this example is as follows Figure 8 Indicates.
[0108] In step (B), the off-chip DSP or CPU generates configuration parameters corresponding to the single carrier signal based on the data frame structure and time slot structure, and writes the configuration parameters into the built-in dual-port RAM of the FPGA. The configuration parameters include the jump state and jump conditions of the FPGA's data transmission state machine, as well as the communication module selection enable switch under each jump state.
[0109] Specifically, configure the following parameters: set the pilot symbol length to 1, the data symbol length to 15, and reset the pilot symbols after every 1024 pilot symbols are sent. Also, enable parameters such as scrambling and LDPC coding when transmitting data symbols. These parameters are then written to the dual-port RAM shared by the FPGA and the DSP or CPU via the bus between the DSP or CPU and the FPGA, waiting for the FPGA's transmitter to read them.
[0110] In step (C), the off-chip DSP or CPU generates corresponding frame header data and communication module data according to the single carrier signal generated as needed, and writes the frame header data and communication module data into the RAM.
[0111] Specifically, the DSP or CPU chip uses the FDD waveform pilot parameters configured by the host computer to Figure 7 The algorithm flow shown generates the frame header data for synchronization of the physical layer frame and the scrambling code data for scrambling, and writes the frame header data and the scrambling code data into the dual-port data RAM in the FPGA chip through the bus between the DSP or CPU and the FPGA chip, waiting for the FPGA chip to read.
[0112] In step (D), the FPGA obtains the data to be sent and reads the configuration parameters from the built-in dual-port RAM to realize the state jump under the data transmission state machine. In each jump state, the corresponding communication module data is read according to the communication module selection enable switch, and the read communication module data is processed to generate a single carrier signal with a corresponding data frame structure and time slot structure.
[0113] Specifically, the DSP or CPU chip modulates the pilot symbol into BPSK according to the waveform requirements, mapping 0 to (X:0x81, Y:0x00) and 1 to (X:0x7F, Y:0x00). The data symbol is modulated into QPSK, mapping 00 to (X:0xA6, Y:0xA6), 01 to (X:0x5A, Y:0xA6), 10 to (X:0xA6, Y:0x5A), and 11 to (X:0x5A, Y:0x5A). The mapped values are then written to the dual-port mapping data RAM in the FPGA chip via the bus between the DSP or CPU and the FPGA chip.
[0114] The FPGA chip reads the configuration parameter RAM of the DSP or CPU chip, turns on scrambling and LDPC coding according to the length of the pilot symbol and data symbol sent each time, and each general state parameter, and cyclically jumps between the state addresses of sending pilot symbols and sending data symbols according to the jump address of the general state machine. At the same time, the mapping value in the mapping data RAM is read according to the mapping relationship between the pilot symbol and the data symbol to complete the generation and mapping of the FDD waveform data.
[0115] In step (E), the FPGA reports the data transmission status information of the single carrier signal to the off-chip DSP or CPU via an interrupt signal, so that the off-chip DSP or CPU can verify whether the FPGA correctly generates the single carrier signal.
[0116] Specifically, the FPGA chip reports the state value of the state machine in the sending program, the sending data symbol count value and other parameters to the DSP and CPU chips through an interrupt. The time of sending the interrupt is the moment when the sending symbol counter is 1.
[0117] In step (F), the off-chip DSP or CPU chip responds to the interrupt sent by the FPGA chip, reads the status information reported by the FPGA chip, and determines whether the FPGA responds correctly based on the reported status information. If it is correct, no intervention will be made. If it is incorrect, the configuration parameters will be adjusted based on the reported information.
[0118] In step (G), the off-chip DSP or CPU chip determines whether the physical layer single carrier signal is generated based on the status parameters reported by the FPGA chip. If not, steps (B) to (F) are repeated until the physical layer single carrier signal is generated.
[0119] In another embodiment of the present application, the processing flow of the present application is illustrated by taking the following specific parameters of the baseband single-carrier signal to be generated as an example.
[0120] The baseband waveform to be generated is in TDD form, the time protection interval is 1ms, the pilot is a continuous pilot mode, the pilot symbol length is 2048, the pilot adopts BPSK modulation, the length of a superframe data symbol is 16384, and QPSK modulation is adopted. The pilot sequence generating polynomial is: f(x) = 1 + X + X 2 +X 10 +X 13 The initial phase is: 13'b1110001110101. The channel coding uses Viterb coding with a code length of (2,1,9). The baseband waveform can be quickly generated by the following steps.
[0121] The system's processing flow includes:
[0122] In step (a), the off-chip DSP or CPU determines the physical layer single carrier signal to be generated according to the communication system selection signal sent by the host computer, and determines the data frame structure and time slot structure corresponding to the single carrier signal.
[0123] Specifically, the data frame structure in this example is as follows Figure 9 Indicates.
[0124] In step (b), the off-chip DSP or CPU generates configuration parameters corresponding to the single carrier signal based on the data frame structure and time slot structure, and writes the configuration parameters into the built-in dual-port RAM of the FPGA. The configuration parameters include the jump state and jump conditions of the FPGA's data transmission state machine, as well as the communication module selection enable switch under each jump state.
[0125] Specifically, configure the following parameters: set the pilot symbol length to 2048 and the data symbol length to 16384. After sending 2048 pilot symbols continuously, reset the pilot symbols. Enable parameters such as (2, 1, 9) Viterb encoding while transmitting data symbols. Then, write the configuration parameters to the shared parameter configuration dual-port RAM in the FPGA chip via the bus between the DSP or CPU and the FPGA chip, waiting for the FPGA chip's transmitter to read them.
[0126] In step (c), the off-chip DSP or CPU generates corresponding frame header data and communication module data according to the single carrier signal generated as needed, and writes the frame header data and communication module data into the RAM.
[0127] Specifically, the DSP or CPU chip uses the TDD waveform pilot parameters configured by the host computer to Figure 7 Generate physical layer frame header data for synchronization and scrambling data for scrambling, and write the header data and scrambling data into the dual-port data RAM in the FPGA chip through the bus between the DSP or CPU and the FPGA chip, waiting for the FPGA chip to read.
[0128] In step (d), the FPGA obtains the data to be sent and reads the configuration parameters from the built-in dual-port RAM to realize the state jump under the data transmission state machine. In each jump state, the corresponding communication module data is read according to the communication module selection enable switch, and the read communication module data is processed to generate a single carrier signal with a corresponding data frame structure and time slot structure.
[0129] Specifically, the DSP or CPU chip modulates the pilot symbol into BPSK according to the waveform requirements, mapping 0 to (X:0x81, Y:0x00) and 1 to (X:0x7F, Y:0x00). The data symbol is modulated into QPSK, mapping 00 to (X:0xA6, Y:0xA6), 01 to (X:0x5A, Y:0xA6), 10 to (X:0xA6, Y:0x5A), and 11 to (X:0x5A, Y:0x5A). The mapped values are then written to the dual-port mapping data RAM in the FPGA chip via the bus between the DSP or CPU and the FPGA chip.
[0130] The FPGA chip reads the parameter RAM configured by the DSP and CPU chips, turns on the (2, 1, 9) Viterb encoding enable according to the length of each pilot symbol sent, the length of the data symbol, and each common state parameter, and cyclically jumps between the sending pilot symbol, sending data symbol, and time guard interval state addresses according to the state jump address. At the same time, the mapping value in the mapping data RAM is read according to the mapping relationship between the pilot symbol and the data symbol to complete the generation and mapping of the TDD waveform data.
[0131] In step (e), the FPGA reports the data transmission status information of the single carrier signal to the off-chip DSP or CPU via an interrupt signal, so that the off-chip DSP or CPU can verify whether the FPGA correctly generates the single carrier signal.
[0132] Specifically, the FPGA chip reports the state value of the state machine in the sending program, the sending data symbol count value and other parameters to the DSP and CPU chips through an interrupt. The time of sending the interrupt is the moment when the sending symbol counter reaches 128.
[0133] In step (f), the off-chip DSP or CPU chip responds to the interrupt sent by the FPGA chip, reads the status information reported by the FPGA chip, and determines whether the FPGA responds correctly based on the reported status information. If it is correct, no intervention will be made. If it is incorrect, the configuration parameters will be adjusted based on the reported information.
[0134] In step (g), the off-chip DSP or CPU chip determines whether the physical layer single carrier signal is generated based on the status parameters reported by the FPGA chip. If not, steps (b) to (f) are repeated until the physical layer single carrier signal is generated.
[0135] To sum up, some embodiments of the present application illustrate how the provided unified hardware platform quickly generates the required single-carrier signal. The technical solution of the present application has the technical advantage of being able to quickly generate single-carrier waveforms of different systems under the configuration of an external DSP or CPU without changing the hardware platform and the FPGA-side program code, thereby saving a lot of waveform generation development time and effectively reducing the workload of system maintenance personnel.
[0136] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
Claims
1. A single carrier signal generation method, characterized in that: The method comprises: The off-chip processor determines the data frame structure and time slot structure corresponding to the single carrier signal according to the single carrier signal generated as needed; The off-chip processor generates configuration parameters corresponding to the single carrier signal according to the data frame structure and the time slot structure, and writes the configuration parameters into a shared memory between the off-chip processor and the baseband processor, wherein the configuration parameters include a jump state and a jump condition of a data transmission state machine of the baseband processor, and a communication module selection enable switch under each jump state; The off-chip processor generates corresponding frame header data and communication module data according to the single carrier signal generated as needed, and writes the frame header data and the communication module data into the shared memory; The baseband processor obtains the data to be sent and reads the configuration parameters and the frame header data from the shared memory to implement state jumps under the data transmission state machine. In each jump state, the baseband processor reads the corresponding communication module data according to the communication module selection enable switch, processes the read communication module data, and generates a single carrier signal with the data frame structure and time slot structure.
2. The single carrier signal generation method according to claim 1, wherein The method further includes: the baseband processor reporting data transmission status information of the single carrier signal to the off-chip processor via an interrupt signal, so that the off-chip processor can verify whether the baseband processor correctly generates the single carrier signal.
3. The single carrier signal generation method according to claim 2, wherein: The method further includes: when the off-chip processor determines that the baseband processor does not correctly generate a single carrier signal, readjusting the configuration parameters and the communication module data, and writing them into the shared memory for the baseband processor to read and process again.
4. The single carrier signal generation method according to claim 1, wherein: The off-chip processor determines the physical layer single carrier signal to be generated according to the communication system selection signal sent by the host computer.
5. The single carrier signal generation method according to claim 1, wherein: The shared memory is a dual-port RAM shared by the baseband processor and the off-chip processor. Each address of the dual-port RAM shared by the baseband processor and the off-chip processor corresponds to a jump state of the data sending state machine, and the data stored at each address is combined in bits to select an enable switch for the communication module in the jump state.
6. The single carrier signal generating method according to claim 5, wherein: The communication module includes interleaving, scrambling and channel coding.
7. The single carrier signal generation method according to claim 1, wherein: The single carrier mode includes FDD or TDD.
8. The single carrier signal generation method according to claim 1, wherein: The single-carrier pilot mode includes continuous pilot or distributed pilot.
9. A single carrier signal generation system, characterized in that: Includes baseband processor, off-chip processor and shared memory; The off-chip processor is configured to determine a data frame structure and a time slot structure corresponding to a single carrier signal generated as needed; The off-chip processor is further configured to generate configuration parameters corresponding to the single carrier signal according to the data frame structure and the time slot structure, and write the configuration parameters into a shared memory between the off-chip processor and the baseband processor, wherein the configuration parameters include a jump state and a jump condition of a data transmission state machine of the baseband processor, and a communication module selection enable switch under each jump state; The off-chip processor is further configured to generate corresponding frame header data and communication module data according to the single carrier signal generated as needed, and write the frame header data and the communication module data into the shared memory; The baseband processor is used to obtain the data to be sent, and read the configuration parameters and the frame header data from the shared memory, to realize the state jump under the data transmission state machine, and in each jump state, read the corresponding communication module data according to the communication module selection enable switch, process the read communication module data, and generate the single carrier signal of the data frame structure and time slot structure.
10. The single carrier generation system according to claim 9, characterized in that: The baseband processor is an FPGA; the off-chip processor is a DSP, a CPU or an MCU outside the FPGA.
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