A method and device for generating a non-periodic binary complementary sequence set signal with a set size of 4

Abstract

The present invention belongs to the technical field of communication systems, and particularly relates to a method and device for generating a non-periodic binary complementary sequence set signal with a set size of 4, wherein the device comprises a control circuit, four input shift registers, four intermediate shift registers, four output shift registers, three multipliers and two switches, and the control circuit controls the input or / and output of the input shift register, the intermediate shift register and the output shift register, and controls the connection of the switches; the present invention arbitrarily selects two pairs of binary Golay complementary sequence pairs with lengths of N and L as seed pairs of the present invention, performs sequence inversion operations, generates eight-way binary sequence signals, performs inversion processing on the selected sequences to finally form binary signals of ten branches, selects binary signals of fixed combinations for cascading, and thereby obtains a binary non-periodic complementary sequence set with a sequence length of 2N+L and a set size of 4; the present invention can be widely used in communication systems, radars and other devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of communication systems, and in particular relates to a method and a device for generating a non-periodic binary complementary sequence set signal with a set size of 4. Background Art

[0002] PMEPR (Peak-to-Mean Envelope Power Ratio) is an important performance parameter in OFDM communication systems, which reflects the ratio between the peak power and the mean power of the signal envelope. High PMEPR values ​​can lead to problems such as nonlinear distortion, increased bit error rate and reduced power efficiency in OFDM communication systems. Therefore, reducing the PMEPR value is crucial to the performance of OFDM communication systems. Complementary sequence sets have perfect complementary properties under certain conditions. Using complementary sequence sets as the modulation sequence of the OFDM system can minimize the difference between the peak power and the mean power of the signal, thereby effectively reducing the PMEPR value. At the same time, complementary sequence sets are also simple, efficient and easy to implement, so they have been widely used in OFDM systems.

[0003] The set of non-periodic binary complementary sequences with a set size of 4 consists of four sequences of equal length, where the sequence elements are composed of 1 and -1. Complementary sequences have been widely studied in sequence design because of their ideal self-correlation properties. In 1960, Golay first introduced and studied binary complementary pairs (Golay MJ E. Complementary Series [J]. IEEE Transactions on Information Theory, 1961, IT-7: 82-87.). The sequence length of a binary Golay complementary pair must satisfy 2 α 10 β 26 γ In the form of, α, β, γ are non-negative integers, and the sequence length of the Golay complementary pair is very limited. The sequence length of the four-complementary sequence pair is more flexible than that of the two-complementary sequence pair. The sequence length of the four-complementary sequence pair must satisfy 2 α+μ 3 β 5 γ 11 η 13 ζIn the form of, α, β, γ, η, ζ, μ ≥ 0; β + γ + η + ζ ≤ α + 2μ + 1; μ ≤ γ + ζ. At present, there are not many methods for constructing quaternary complementary sequence pairs in the prior art. Li Guojun et al. proposed a method and device for generating quaternary complementary sequence pairs of length 3N for quaternary complementary sequence pairs (Li Guojun, Zeng Fanxin, Zhou Xiaona, Ye Changrong. A method and device for generating a signal of a four-phase non-periodic complementary sequence pair of length 3N [P]. Chongqing: CN112688755A, 2021-04-20.), but this scheme can only generate complementary sequence pairs, not complementary sequence sets.

[0004] Subsequently, the binary Golay complementary pair was extended to the binary complementary sequence set, which means that the complementary sequence contains more than two subsequences (Tseng C, Liu C. Complementary Sets of Sequences [J]. IEEE Transactions on Information Theory, 1972, 18 (5): 644-665.). In terms of sequence length, the sequence length of the complementary sequence set is more flexible than that of the complementary sequence pair. The complementary sequence set sequence has more advantages in terms of sequence length than the complementary sequence pair sequence.In 2016, based on the truncated known Golay sequence, Chen proposed the first method to construct complementary sets of non-power-of-two length (CY Chen. Complementary sets and reed-muller codes for Peak-to-Average power ratio reduction in OFDM [J]. IEEE Trans. Inform., vol. 62, no. 12, pp. 7538-7545, Dec. 2016.). In 2017, a method to construct complementary sets of non-power-of-two length by concatenation [C]. in Proc. Eighth Int. Workshop Signal Design and Its Applications in Communications (IWSDA), 2017, pp. 24–28.) In 2019, Adhikary et al. proposed a new method for constructing complementary sequence sets by inserting elements on Golay complementary pairs (AR Adhikary, S. Majhi, New constructions of complementary sets of sequences of lengths non-power-of-two [J]. IEEE Communications Letters, vol. 23, no. 7, pp. 1119–1122, 2019.), in 2020, Wang et al. proposed a method to construct complementary sequence sets with non-power-of-two lengths by using Golay complementary pairs and the concatenation of sequences in complementary sequence sets (G. Wang, ARA Adhikary, Z. Zhou, and Y. Yang. Generalized constructions of complementary sets of sequences of lengths non-power-of-two [J]. IEEE Signal Processing Letters, vol. 27, pp. 136–140, 2020.).

[0005] In summary, there are few methods for constructing non-periodic binary complementary sequence sets in the prior art. Some methods lack flexibility and have the problem of code rate loss. Some constructed complementary sequence sets have limited sequence lengths. Some construction methods have limited parameters that are difficult to determine in advance and have disadvantages such as a difficult implementation process. Summary of the invention

[0006] In order to obtain a non-periodic binary complementary sequence set with a simple structure and easy implementation, the present invention proposes a method and device for generating a non-periodic binary complementary sequence set signal with a set size of 4, the method comprising:

[0007] S1. Arbitrarily select a binary Golay complementary sequence pair a=(a(0),…,a(k),…,a(N-1)) and b=(b(0),…,b(k),…,b(N-1)) of length N as a seed pair, and store them in a first input shift register and a second input shift register of length N, respectively; arbitrarily select a binary Golay complementary sequence pair x=(x(0),…,x(k),…,x(L-1)) and y=(y(0),…,y(k),…,y(L-1)) of length L as a seed pair, and store them in a third input shift register and a fourth input shift register of length L, respectively;

[0008] S2. Under the control of the control circuit, the output code element of the first input shift register is divided into two signals; the output code element of the second input shift register is divided into two signals; the output code element of the third input shift register is divided into two signals; the output code element of the fourth input shift register is divided into two signals;

[0009] S3, output the first signal of the first input shift register to the first node, and shift the second signal in reverse order into the first intermediate shift register; output the first signal of the second input shift register to the fourth node, and shift the second signal in reverse order into the second intermediate shift register; output the first signal of the third input shift register to the seventh node, and shift the second signal in reverse order into the third intermediate shift register; output the first signal of the fourth input shift register to the third multiplier and output it to the ninth node after inversion, and shift the second signal in reverse order into the fourth intermediate shift register;

[0010] S4. Under the control of the control circuit, the output code element of the first intermediate shift register is divided into two signals; the output code element of the second intermediate shift register is divided into two signals;

[0011] S5, output the first signal of the first intermediate shift register to the first multiplier and output it to the second node after inversion, and output the second signal to the third node; output the first signal of the second intermediate shift register to the second multiplier and output it to the fifth node after inversion, and output the second signal to the sixth node; output the output code element of the third intermediate shift register to the eighth node; output the output code element of the fourth intermediate shift register to the tenth node;

[0012] S6, control the second switch to connect to the first output shift register, control the first switch to connect to the fifth node, the seventh node and the first node in sequence to output the three signals; control the second switch to connect to the second output shift register, control the first switch to connect to the third node, the ninth node and the fourth node in sequence to output the three signals; control the second switch to connect to the third output shift register, control the first switch to connect to the sixth node, the tenth node and the first node in sequence to output the three signals; control the second switch to connect to the fourth output shift register, control the first switch to connect to the second node, the eighth node and the fourth node in sequence to output the three signals; finally obtain a binary non-periodic complementary sequence set with a sequence length of 2N+L and a set size of 4.

[0013] Furthermore, the output signal of the first intermediate shift register is a reverse sequence signal of the output signal of the first input shift register; the output signal of the second intermediate shift register is a reverse sequence signal of the output signal of the second input shift register; the output signal of the third intermediate shift register is a reverse sequence signal of the output signal of the third input shift register; and the output signal of the fourth intermediate shift register is a reverse sequence signal of the output signal of the fourth input shift register.

[0014] Furthermore, the multiplication coefficients of the first multiplier, the second multiplier, and the third multiplier are all -1.

[0015] Furthermore, the control circuit controls the connection between the first switch and the signal output node, and controls the connection between the second switch and the output shift register, and sequentially sends the combined three-way node signal to the output shift register, wherein the length of two-way node signal is N, and the length of one-way node signal is L. Finally, the signal of each output shift register is composed of a cascade of three-way node signal, that is, the sequence length of the non-periodic binary complementary sequence set finally obtained is 2N+L.

[0016] The present invention provides a non-periodic binary complementary sequence set signal generating device with a set size of 4, the device comprising a control circuit, four input shift registers, four intermediate shift registers, four output shift registers, three multipliers and two switches, the control circuit controls the input and / or output of the input shift register, the intermediate shift register and the output shift register and controls the connection of the switches;

[0017] The first input shift register is divided into two outputs, respectively connected to the first node and the first intermediate shift register; the second input shift register is divided into two outputs, respectively connected to the fourth node and the second intermediate shift register; the third input shift register is divided into two outputs, respectively connected to the seventh node and the third intermediate shift register; the second input shift register is divided into two outputs, respectively connected to the third multiplier and the fourth intermediate shift register;

[0018] The first intermediate shift register is divided into two outputs, respectively connected to the third node and the first multiplier; the second intermediate shift register is divided into two outputs, respectively connected to the sixth node and the second multiplier; the third intermediate shift register outputs to the eighth node; the fourth intermediate shift register outputs to the tenth node;

[0019] The first multiplier multiplies the coefficient and outputs to the second node; the second multiplier multiplies the coefficient and outputs to the fifth node; the third multiplier multiplies the coefficient and outputs to the ninth node;

[0020] The first switch controls the connection with the first node, the second node, the third node, the fourth node, the fifth node, the sixth node, the seventh node, the eighth node, the ninth node and the tenth node; the second switch controls the connection with the first output shift register, the second output shift register, the third output shift register and the fourth output shift register, and the first switch and the second switch are connected.

[0021] Furthermore, the length of the first input shift register, the second input shift register, the first intermediate shift register and the second intermediate shift register is N; the length of the third input shift register, the fourth input shift register, the third intermediate shift register and the fourth intermediate shift register is L; the length of the first output shift register, the second output shift register, the third output shift register and the fourth output shift register is 2N+L.

[0022] Beneficial effects of the present invention:

[0023] The present invention arbitrarily selects a binary Golay complementary sequence pair (a, b) with a length of N and a binary Golay complementary sequence pair (x, y) with a length of L as two seed pairs of the present invention, and obtains a reverse sequence signal by reversing the sequence signal. A total of eight binary signals are generated, and then the selected signal y, After inversion, we get the signal -y. Finally, ten output nodes are formed; in the present invention, sequence signals of ten output nodes are selected in a combined manner for cascade combination, and finally a binary non-periodic complementary sequence set (C1, C2, C3, C4) with a sequence length of 2N+L and a set size of 4 is obtained, and the sum of the non-periodic autocorrelation functions of the four sequences C1, C2, C3, C4 is an impulse function; the present invention can be applied to communication systems, signal processing, large-scale integrated circuit testing, etc., and can help solve the PMEPR problem and frequency domain synchronization problem in the OFDM system, and improve system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a principle block diagram of a non-periodic binary complementary sequence set signal generating device with a set size of 4 according to the present invention;

[0025] Figure 2 It is a flow chart of a method for generating a non-periodic binary complementary sequence set signal with a set size of 4 according to the present invention;

[0026] Figure 3 It is a simulation diagram of the sum of the non-periodic autocorrelation functions of the complementary sequence set subsets C1, C2, C3, and C4 that are finally constructed in the embodiment. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Figure 1 is a structural diagram of a non-periodic binary complementary sequence set signal generating device with a set size of 4 according to the present invention, such as Figure 1 Said device comprises a control circuit, four input shift registers, four intermediate shift registers, four output shift registers, three multipliers and two switches, wherein said control circuit controls the input and / or output of the input shift registers, the intermediate shift registers and the output shift registers and controls the connection of the switches;

[0029] The first input shift register is divided into two outputs, respectively connected to the first node and the first intermediate shift register; the second input shift register is divided into two outputs, respectively connected to the fourth node and the second intermediate shift register; the third input shift register is divided into two outputs, respectively connected to the seventh node and the third intermediate shift register; the second input shift register is divided into two outputs, respectively connected to the third multiplier and the fourth intermediate shift register;

[0030] The first intermediate shift register is divided into two outputs, respectively connected to the third node and the first multiplier; the second intermediate shift register is divided into two outputs, respectively connected to the sixth node and the second multiplier; the third intermediate shift register outputs to the eighth node; the fourth intermediate shift register outputs to the tenth node;

[0031] The first multiplier multiplies the coefficient and outputs to the second node; the second multiplier multiplies the coefficient and outputs to the fifth node; the third multiplier multiplies the coefficient and outputs to the ninth node;

[0032] The first switch controls the connection with the first node, the second node, the third node, the fourth node, the fifth node, the sixth node, the seventh node, the eighth node, the ninth node and the tenth node; the second switch controls the connection with the first output shift register, the second output shift register, the third output shift register and the fourth output shift register, and the first switch and the second switch are connected.

[0033] Understandably, Figure 1 In order to facilitate the description of each device, the description of each device is adjusted accordingly. For example, the input shift register includes a first input shift register, a second input shift register, a third input shift register and a fourth input shift register, which are respectively referred to as input shift register 1, input shift register 2, input shift register 3 and input shift register 4; similarly, the intermediate shift register includes a first intermediate shift register, a second intermediate shift register, a third intermediate shift register and a fourth intermediate shift register, which are respectively referred to as intermediate shift register 1, intermediate shift register 2, intermediate shift register 3 and intermediate shift register 4; similarly, the output shift register includes a first output shift register, a second output shift register, The third output shift register and the fourth output shift register refer to output shift register 1, output shift register 2, output shift register 3 and output shift register 4 respectively; in addition, nodes A, B, C, D, E, F, G, H, I and J represent the first node, the second node, the third node, the fourth node, the fifth node, the sixth node, the seventh node, the eighth node, the ninth node and the tenth node respectively, and nodes S and T are nodes with switches set to zero. When the signal of the output shift register is generated, the two switches are set to zero, that is, the first switch K1 is connected to the node S, and the second switch K2 is connected to the node T; multiplier 1 refers to the first multiplier, multiplier 2 refers to the second multiplier, and multiplier 3 refers to the third multiplier.

[0034] Figure 2 FIG. 4 is a flow chart of a method for generating a non-periodic binary complementary sequence set signal with a set size of 4 according to an embodiment of the present invention. Figure 2 As shown, the method includes:

[0035] S1. Arbitrarily select a binary Golay complementary sequence pair a=(a(0),…,a(k),…,a(N-1)) and b=(b(0),…,b(k),…,b(N-1)) of length N as a seed pair, and store them in a first input shift register and a second input shift register of length N, respectively; arbitrarily select a binary Golay complementary sequence pair x=(x(0),…,x(k),…,x(L-1)) and y=(y(0),…,y(k),…,y(L-1)) of length L as a seed pair, and store them in a third input shift register and a fourth input shift register of length L, respectively;

[0036] S2. Under the control of the control circuit, the output code element of the first input shift register is divided into two signals; the output code element of the second input shift register is divided into two signals; the output code element of the third input shift register is divided into two signals; the output code element of the fourth input shift register is divided into two signals;

[0037] S3, output the first signal a of the first input shift register to the first node, and shift the second signal in reverse order into the first intermediate shift register; output the first signal b of the second input shift register to the fourth node, and shift the second signal in reverse order into the second intermediate shift register; output the first signal x of the third input shift register to the seventh node, and shift the second signal in reverse order into the third intermediate shift register; output the first signal of the fourth input shift register to the third multiplier and output -y to the ninth node after inversion, and shift the second signal in reverse order into the fourth intermediate shift register;

[0038] S4. Under the control of the control circuit, the output code element of the first intermediate shift register is divided into two signals; the output code element of the second intermediate shift register is divided into two signals;

[0039] S5: Output the first signal of the first intermediate shift register to the first multiplier and invert it. Output to the second node, the second signal Output to the third node; output the first signal of the second intermediate shift register to the second multiplier and invert it Output to the fifth node, the second signal Output to the sixth node; Output code element of the third intermediate shift register Output to the eighth node; Output code element of the fourth intermediate shift register Output to the tenth node;

[0040] In the embodiment of the present invention, the signals a, b, x, and y are respectively arranged in reverse order, and the reverse order signals can be obtained respectively. Separately for the signal By inverting y, we can get -y; the output signals from the first node to the tenth node are a, b, x, -y,

[0041] S6, control the second switch to connect to the first output shift register, control the first switch to connect to the fifth node, the seventh node and the first node in sequence to output the three signals; control the second switch to connect to the second output shift register, control the first switch to connect to the third node, the ninth node and the fourth node in sequence to output the three signals; control the second switch to connect to the third output shift register, control the first switch to connect to the sixth node, the tenth node and the first node in sequence to output the three signals; control the second switch to connect to the fourth output shift register, control the first switch to connect to the second node, the eighth node and the fourth node in sequence to output the three signals; finally obtain a binary non-periodic complementary sequence set with a sequence length of 2N+L and a set size of 4.

[0042] Example:

[0043] For ease of understanding, this embodiment takes two pairs of binary Golay sequence pairs when N=4 and L=10 as seed pairs, which are expressed as:

[0044] Let (a, b) be a binary Golay complementary sequence pair of length 4.

[0045]

[0046] Let (x, y) be a binary Golay complementary sequence pair of length 10.

[0047]

[0048] According to the solution of the present invention, the binary non-periodic complementary sequence set (C1, C2, C3, C4) with a set size of 4 is:

[0049]

[0050] Finally, we obtain a set of binary non-periodic complementary sequences (C1, C2, C3, C4) with a sequence length of 18 and a set size of 4, such as Figure 3 As shown, the sum of the non-periodic autocorrelation functions of the four sequences C1, C2, C3, and C4 is an impulse function with ideal correlation performance.

[0051] In summary, the simulation results are consistent with the theoretical definition, and it is known that the present invention is feasible, that is, the binary non-periodic complementary sequence set signal with a set size of 4 generated by the present invention has practical physical value and can be widely used in signal processing and communication systems.

[0052] All or part of the steps of the present invention can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, which may include: ROM, RAM, magnetic disk or optical disk, etc.

[0053] Although the principles of the present invention have been shown and described, it will be appreciated by those skilled in the art that many changes, modifications, substitutions and variations may be made to the present invention without departing from the principles and spirit of the invention, and the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for generating a non-periodic binary complementary sequence set signal with a set size of 4, characterized in that: The method comprises the following steps: S1. Arbitrarily select a binary Golay complementary sequence pair a=(a(0),…,a(k),…,a(N-1)) and b=(b(0),…,b(k),…,b(N-1)) of length N as a seed pair, and store them in a first input shift register and a second input shift register of length N, respectively; arbitrarily select a binary Golay complementary sequence pair x=(x(0),…,x(k),…,x(L-1)) and y=(y(0),…,y(k),…,y(L-1)) of length L as a seed pair, and store them in a third input shift register and a fourth input shift register of length L, respectively; S2. Under the control of the control circuit, the output code element of the first input shift register is divided into two signals; the output code element of the second input shift register is divided into two signals; the output code element of the third input shift register is divided into two signals; the output code element of the fourth input shift register is divided into two signals; S3, output the first signal of the first input shift register to the first node, and shift the second signal in reverse order into the first intermediate shift register; output the first signal of the second input shift register to the fourth node, and shift the second signal in reverse order into the second intermediate shift register; output the first signal of the third input shift register to the seventh node, and shift the second signal in reverse order into the third intermediate shift register; output the first signal of the fourth input shift register to the third multiplier and output it to the ninth node after inversion, and shift the second signal in reverse order into the fourth intermediate shift register; S4. Under the control of the control circuit, the output code element of the first intermediate shift register is divided into two signals; the output code element of the second intermediate shift register is divided into two signals; S5, output the first signal of the first intermediate shift register to the first multiplier and output it to the second node after inversion, and output the second signal to the third node; output the first signal of the second intermediate shift register to the second multiplier and output it to the fifth node after inversion, and output the second signal to the sixth node; output the output code element of the third intermediate shift register to the eighth node; output the output code element of the fourth intermediate shift register to the tenth node; S6, control the second switch to connect to the first output shift register, control the first switch to connect to the fifth node, the seventh node and the first node in sequence to output the three signals; control the second switch to connect to the second output shift register, control the first switch to connect to the third node, the ninth node and the fourth node in sequence to output the three signals; control the second switch to connect to the third output shift register, control the first switch to connect to the sixth node, the tenth node and the first node in sequence to output the three signals; control the second switch to connect to the fourth output shift register, control the first switch to connect to the second node, the eighth node and the fourth node in sequence to output the three signals; finally obtain a binary non-periodic complementary sequence set with a sequence length of 2N+L and a set size of 4.

2. The method for generating a non-periodic binary complementary sequence set signal with a set size of 4 according to claim 1, characterized in that: The output signal of the first intermediate shift register is a reverse sequence signal of the output signal of the first input shift register; the output signal of the second intermediate shift register is a reverse sequence signal of the output signal of the second input shift register; the output signal of the third intermediate shift register is a reverse sequence signal of the output signal of the third input shift register; the output signal of the fourth intermediate shift register is a reverse sequence signal of the output signal of the fourth input shift register.

3. The method for generating a non-periodic binary complementary sequence set signal with a set size of 4 according to claim 1, characterized in that: The multiplication coefficients of the first multiplier, the second multiplier and the third multiplier are all -1.

4. The method for generating a non-periodic binary complementary sequence set signal with a set size of 4 according to claim 1, characterized in that: The control circuit controls the connection between the first switch and the signal output node, controls the connection between the second switch and the output shift register, and sequentially sends the combined three-way node signal to the output shift register, wherein the lengths of the two-way node signal are N, and the length of the one-way node signal is L. Finally, the signal of each output shift register is composed of the cascade of the three-way node signal, that is, the sequence length of the non-periodic binary complementary sequence set finally obtained is 2N+L.

5. A non-periodic binary complementary sequence set signal generating device with a set size of 4, characterized in that: The device comprises a control circuit, four input shift registers, four intermediate shift registers, four output shift registers, three multipliers and two switches, wherein the control circuit controls the input or / and output of the input shift register, the intermediate shift register and the output shift register and controls the connection of the switches; The first input shift register is divided into two outputs, respectively connected to the first node and the first intermediate shift register; the second input shift register is divided into two outputs, respectively connected to the fourth node and the second intermediate shift register; the third input shift register is divided into two outputs, respectively connected to the seventh node and the third intermediate shift register; the second input shift register is divided into two outputs, respectively connected to the third multiplier and the fourth intermediate shift register; The first intermediate shift register is divided into two outputs, respectively connected to the third node and the first multiplier; the second intermediate shift register is divided into two outputs, respectively connected to the sixth node and the second multiplier; the third intermediate shift register outputs to the eighth node; the fourth intermediate shift register outputs to the tenth node; The first multiplier multiplies the coefficient and outputs to the second node; the second multiplier multiplies the coefficient and outputs to the fifth node; the third multiplier multiplies the coefficient and outputs to the ninth node; The first switch controls the connection with the first node, the second node, the third node, the fourth node, the fifth node, the sixth node, the seventh node, the eighth node, the ninth node and the tenth node; the second switch controls the connection with the first output shift register, the second output shift register, the third output shift register and the fourth output shift register, and the first switch and the second switch are connected.

6. The device for generating a non-periodic binary complementary sequence set signal with a set size of 4 according to claim 5, characterized in that: The length of the first input shift register, the second input shift register, the first intermediate shift register and the second intermediate shift register is N; the length of the third input shift register, the fourth input shift register, the third intermediate shift register and the fourth intermediate shift register is L; the length of the first output shift register, the second output shift register, the third output shift register and the fourth output shift register is 2N+L.

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