Optimization method and system for spi interface communication between arm and fpga

Abstract

The application discloses an optimization method and system for ARM and FPGA SPI interface communication, and the method comprises the following steps: when ARM transmits data to a target FPGA through an SPI interface, the length of the data to be transmitted is determined; the length of the data to be transmitted is compared with the size of a preset bit width; the value of a transfer parameter is_poll is determined when the length of the data to be transmitted is less than or equal to the preset bit width; if the value of the transfer parameter is_poll is a first set value, the SPI chip selection pin of the target FPGA is pulled down, and the data to be transmitted is immediately transmitted to the target FPGA; if the value of the transfer parameter is_poll is a second set value, the data to be transmitted is transmitted to the target FPGA in a queue mode. By implementing the embodiment of the application, the time consumption of the SPI communication between ARM and FPGA can be reduced, the stability is improved, and the communication of the low-cost ARM+FPGA scheme can meet more industrial sites.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded systems, and in particular to a real-time optimization method and system for SPI interface communication between an ARM and a FPGA. Background Art

[0002] In recent years, single ARM processors have become increasingly unable to meet the functional requirements of industrial sites. In particular, industries such as energy and power, industrial control, and smart healthcare often require processor platforms with ARM+FPGA architecture to implement specific functions, such as multi-channel / high-speed AD acquisition, multiple network ports, multiple serial ports, multiple / high-speed parallel DI / DO, and high-speed data parallel processing.

[0003] For cost-insensitive discrete ARM+FPGA applications with high communication speed requirements, the PCIe communication interface is generally used. However, for cost-sensitive discrete ARM+FPGA applications, the PCIe communication interface increases the cost of the FPGA chip. Using the SPI interface can meet the functional needs of many industrial sites. However, current SPI and FPGA communication based on ARMLinux can affect the real-time performance and stability of SPI communication due to factors such as the Linux driver implementation and system scheduling.

[0004] The Chinese invention patent with publication number CN103389707A discloses an AISG controller and control method based on ARM and FPGA, which belongs to the field of antenna equipment technology. In this invention patent, the ARM and FPGA communicate through the SPI interface, with the ARM in master SPI mode and the FPGA in slave SPI mode. When data needs to be read and written, it is actively initiated by the ARM; the FPGA is connected to the external RS-485 chip through UART_TXD, UART_RXD and UART_CE; the ARM is used to process the AISG data link layer protocol; the FPGA is used to frame, deframe, encode, decode the data and implement RS-485 communication.

[0005] Although the above-mentioned comparative documents disclose the SPI communication between ARM and FPGA, when ARM and FPGA transmit data via SPI, ARM acts as the SPI master mode and FPGA acts as the SPI slave mode. Due to the working mechanism of SPI, ARM needs to select the slave device FPGA by pulling down the SPI chip select chip before sending the clock and data.

[0006] Because the SPI driver uses queues and interrupt signals to wait for transmission completion to determine whether to pull the chip select signal high or low, the control of the SPI chip select signal is affected by the Linux system task scheduling, resulting in two problems: (1) The SPI chip select signal is pulled low for too long, resulting in a low communication rate, that is, a low real-time performance. (2) Communication is unstable, sometimes taking a long time and sometimes a short time, with large jitter, resulting in unstable and untimely data transmission between ARM and FPGA, which cannot meet the high requirements of industrial field applications. Summary of the Invention

[0007] The purpose of the present invention is to provide a real-time optimization method and system for SPI interface communication between ARM and FPGA, which can reduce the time consumption (improve real-time performance) and improve the stability of SPI communication between ARM and FPGA, so that the communication of low-cost ARM+FPGA solution can meet the needs of more industrial sites.

[0008] To achieve the above objectives, the first aspect of the present invention discloses a real-time optimization method for SPI interface communication between an ARM and an FPGA, wherein the ARM is used as an SPI master mode and the FPGA is used as an SPI slave mode; the method comprises the following steps:

[0009] When the ARM transmits data to the target FPGA via the SPI interface, determining the length of the data to be transmitted;

[0010] Determine the size of the length of the data to be transmitted and the preset bit width, and when the length of the data to be transmitted is less than or equal to the preset bit width, determine the value of the transfer parameter is_poll;

[0011] If the transfer parameter is_poll value is a first set value, the SPI chip select pin of the target FPGA is pulled low, and the data to be transmitted is immediately transmitted to the target FPGA; if the transfer parameter is_poll value is a second set value, the data to be transmitted is transmitted to the target FPGA in a queue manner.

[0012] As an optional implementation manner, in the first aspect of the present invention, the data to be transmitted is immediately transmitted to the target FPGA, and then the method further includes:

[0013] Use the polling method to cyclically query the SPI transmission completion flag of the SPI status register. If the SPI transmission completion flag is found to be set, the SPI chip select pin of the target FPGA is pulled high to end the data transmission.

[0014] As an optional implementation manner, in the first aspect of the present invention, transmitting the data to be transmitted to the target FPGA in a queue manner includes:

[0015] The current thread is suspended by the SPI driver, and an interrupt wake-up is performed after the SPI driver is completed until the data to be transmitted is completed.

[0016] As an optional implementation, in the first aspect of the present invention, when the length of the data to be transmitted is greater than a preset bit width, a DMA controller is started to move the data to be transmitted.

[0017] As an optional implementation manner, in the first aspect of the present invention, starting the DMA controller to move the data to be transmitted includes:

[0018] The current thread is suspended by the DMA controller, and the interrupt wake-up is performed after the DMA controller completes the transfer, until the data to be transmitted is completed.

[0019] A second aspect of the present invention discloses a real-time optimization system for SPI interface communication between an ARM and an FPGA, wherein the ARM operates in SPI master mode and the FPGA operates in SPI slave mode. When the ARM transmits data to a target FPGA via the SPI interface, the ARM is configured to determine the length of the data to be transmitted and to judge the difference between the length of the data to be transmitted and a preset bit width. If the length of the data to be transmitted is less than or equal to the preset bit width, the ARM further determines the value of a transmission parameter, is_poll.

[0020] If the transfer parameter is_poll value is a first set value, ARM pulls down the SPI chip select pin of the target FPGA through the SPI driver and immediately transmits the data to be transmitted to the target FPGA; if the transfer parameter is_poll value is a second set value, ARM transmits the data to be transmitted to the target FPGA in a queue manner.

[0021] As an optional embodiment, in the second aspect of the present invention, ARM pulls down the SPI chip select pin of the target FPGA through SPI driving, and immediately transmits the data to be transmitted to the target FPGA. Then, ARM uses a polling method to cyclically query the SPI transmission completion flag of the SPI status register. If the SPI transmission completion flag is set, the SPI chip select pin of the target FPGA is pulled high to end the data transmission.

[0022] As an optional implementation, in the second aspect of the present invention, when the length of the data to be transmitted is greater than a preset bit width, the ARM starts DMA to move the data to be transmitted.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] This embodiment of the present invention builds on the existing SPILinux driver (the SPI driver in Linux, often referred to as the SPI driver) by adding a function to determine the value of a transmission parameter. This value can be used to determine the data transmission mode selected by the user. When the user selects polling mode, the SPI driver immediately transmits data after pulling the SPI chip select pin of the target FPGA low. This eliminates the need for queues, avoids CPU scheduling, and reduces time consumption, thereby improving real-time performance and stability. This allows the communication of low-cost ARM+FPGA solutions to meet the needs of more industrial sites. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of a method for optimizing real-time performance of SPI interface communication between an ARM and an FPGA according to an embodiment of the present invention;

[0026] Figure 2 This is the structural diagram of the existing ARMSPI driver framework;

[0027] Figure 3 It is a structural diagram of the ARMSPI driver framework according to an embodiment of the present invention;

[0028] Figure 4 The figure is a schematic diagram of the process of transmitting data from the ARM side to the FPGA side according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Below, the present invention is further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, under the premise of no conflict, the various embodiments described below or the various technical features can be arbitrarily combined to form a new embodiment. Unless otherwise specified, the materials and equipment used in this embodiment can be purchased from the market. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and cannot be understood as limiting this application.

[0030] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatus.

[0031] Example 1

[0032] The application discloses an ARM and FPGA SPI interface communication real-time optimization method, which is mainly applied to the scene that ARM Linux and FPGA transmit data through an SPI interface, wherein the ARM is in an SPI master mode (master device) and the FPGA is in an SPI slave mode (slave device).

[0033] Please refer to Figure 1 The ARM and FPGA SPI interface communication real-time optimization method comprises the following steps:

[0034] S110, when the ARM (ARM is a short name of an ARM processor) transmits data to a target FPGA (FPGA is a short name of an FPGA processor) through an SPI interface, the length of the data to be transmitted is determined.

[0035] The target FPGA refers to an FPGA to which the ARM sends the data to be transmitted, the ARM processor generally has a plurality of SPI controllers and a plurality of chip selects, can connect a plurality of different devices (for example, can be a plurality of FPGA processors, or other types of devices, for example, data acquisition devices, etc.), and the data transmission between the ARM and the target FPGA does not affect the normal use of other devices.

[0036] S120, it is judged whether the length of the data to be transmitted is less than or equal to the size of a preset bit width, when the length of the data to be transmitted is less than or equal to the preset bit width, the operation of step S130 is performed, and when the length of the data to be transmitted is greater than the preset bit width, the operation of step S160 is performed.

[0037] The preset bit width is the amount of data transmitted at a time in a current thread, and a user can configure the preset bit width when configuring an SPI bus, for example, the preset bit width can be set to 64 bytes, and the user can also configure a clock rate and the like when configuring the SPI bus.

[0038] The application mainly improves the data transmission mode when the length of the data to be transmitted is less than or equal to the preset bit width. Please refer to Figure 3 The application improves the data transmission mode when the length of the data to be transmitted is less than or equal to the preset bit width. Please refer to Figure 2 The application improves the data transmission mode when the length of the data to be transmitted is less than or equal to the preset bit width. Please refer to

[0039] In the case where the length of the data to be transmitted is greater than the preset bit width, the embodiment of the present invention still adopts the existing method of starting DMA transfer to realize data transmission, and specifically refers to the operation of step S160.

[0040] S130, determining the value of the transfer parameter is_poll. If the transfer parameter is_poll value is the first set value, executing the operation of step S140; if the transfer parameter is_poll value is the second set value, executing the operation of step S150.

[0041] The value of the parameter is_poll is input by the user into the ARM through the application, and then passed to the SPI driver by the ARM. The user input through the application can be realized by selecting from the drop-down box or by checking the box, which is not limited here.

[0042] The specific values ​​of the first set value and the second set value can be set as needed. Obviously, the first set value and the second set value need to be consistent with the corresponding parameter values ​​in the SPI driver code. For example, the first set value can be set to 1 and the second set value can be set to 0.

[0043] When the user sets the transfer parameter is_poll value to the first set value, it means that the user hopes to improve the real-time and stability of the data transmission to be transmitted, and the parameter entered in the application is the polling mode. Please refer to the operation of step S140 for details. When the user sets the transfer parameter is_poll value to the second set value, it means that the user hopes to use the existing method to transmit the data to be transmitted. The parameter entered in the application is the interrupt mode. Please refer to the operation of step S150 for details.

[0044] S140 , pull down the SPI chip select pin of the target FPGA, and immediately transmit the data to be transmitted to the target FPGA.

[0045] When the parameter is_poll is set to the first set value, the data to be transmitted is transmitted in a polling manner. In this case, ARM directly drives the SPI to pull down the SPI chip select pin corresponding to the target FPGA and directly transmits the data to be transmitted without using a queue to wait for CPU scheduling, thereby greatly reducing time consumption. Moreover, since data transmission is not affected by the Linux system task scheduling, it also avoids large jitter and unstable communication.

[0046] Next, the SPI driver uses a polling method to cyclically query the SPI transmission completion flag of the SPI status register. If the SPI transmission completion flag is found to be set, the SPI chip select pin of the target FPGA is pulled high to end this data transmission.

[0047] S150: Transmit the data to be transmitted to the target FPGA in a queue manner.

[0048] When the value of the transfer parameter is_poll is set to the second set value, the data to be transmitted is transmitted using the existing interrupt mode.

[0049] The SPI driver uses queues and interrupt signals waiting for transmission completion to determine whether the chip select signal is pulled high or low. That is, the current thread is suspended by the SPI driver, waiting for the SPI driver to complete, and the interrupt handling function wakes up until the data to be transmitted is completed.

[0050] S160: Start the DMA controller to move the data to be transmitted.

[0051] When the length of the data to be transmitted is greater than the preset bit width, data transmission is achieved by starting DMA transfer, that is, suspending the current thread through the DMA controller, waiting for the DMA controller transfer to end, and waking up the interrupt processing function until the data to be transmitted is completed.

[0052] Figure 4 The test process of polling mode and interrupt mode is shown. Please refer to Figure 4 As shown, the testing process is as follows:

[0053] First, the parameters entered by the user are received and parsed. One parameter determines whether the user uses polling mode. Second, the SPI bus is configured (configuration of clock rate, preset bit width, etc.). Third, the parameter content of the user input corresponding to the transmission parameter is determined. If the polling mode is used, the parameter is_poll=1 is passed to the SPI driver, and the SPI driver will use polling mode to transmit data. If the user input parameters are not used (i.e., interrupt mode is used), the parameter is_poll=0 is passed to the SPI driver, and the SPI driver will use non-polling mode (interrupt mode) to transmit data. Finally, the data to be transmitted is prepared and the SPI driver is started for transmission.

[0054] You can test it by choosing polling or non-polling mode. From the test results, the real-time performance and stability of the polling mode are significantly improved compared with the non-polling mode.

[0055] Example 2

[0056] A real-time optimization system for SPI interface communication between an ARM and an FPGA, wherein the ARM operates in SPI master mode and the FPGA operates in SPI slave mode. When the ARM transmits data to a target FPGA via the SPI interface, the ARM is configured to determine the length of the data to be transmitted and to judge the difference between the length of the data to be transmitted and a preset bit width. If the length of the data to be transmitted is less than or equal to the preset bit width, the ARM further determines the value of a transmission parameter, is_poll.

[0057] If the transfer parameter is_poll value is a first set value, ARM pulls down the SPI chip select pin of the target FPGA through the SPI driver and immediately transmits the data to be transmitted to the target FPGA; if the transfer parameter is_poll value is a second set value, ARM transmits the data to be transmitted to the target FPGA in a queue manner.

[0058] Preferably, ARM pulls down the SPI chip select pin of the target FPGA through the SPI driver, and immediately transmits the data to be transmitted to the target FPGA. Then, ARM uses a polling method to cyclically query the SPI transmission completion flag of the SPI status register. If the SPI transmission completion flag is set, the SPI chip select pin of the target FPGA is pulled high to end the data transmission.

[0059] Preferably, when the length of the data to be transmitted is greater than a preset bit width, the ARM starts DMA to move the data to be transmitted.

[0060] This embodiment of the present invention builds on the existing SPILinux driver by adding a function to determine the value of a transmission parameter. This value can be used to determine the user-selected data transmission mode. When the user selects polling mode, the SPI driver immediately transmits data after pulling the SPI chip select pin of the target FPGA low. This eliminates the need for queues, avoids CPU scheduling, and reduces time consumption, thereby improving real-time performance and stability. This allows the low-cost ARM+FPGA solution to meet the communication needs of more industrial sites.

[0061] Finally, it should be noted that the above-mentioned implementation mode is only a preferred embodiment of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and replacements made by technicians in this field on the basis of the present invention fall within the scope of protection required by the present invention.

Claims

1. A method for optimizing SPI interface communication between an ARM and an FPGA, wherein the ARM is used as an SPI master mode and the FPGA is used as an SPI slave mode; characterized in that: It includes the following steps: When the ARM transmits data to the target FPGA through the SPI interface, it determines the length of the data to be transmitted; Determine the size of the length of the data to be transmitted and the preset bit width. When the length of the data to be transmitted is less than or equal to the preset bit width, determine the value of the transfer parameter is_poll; the value of the transfer parameter is_poll is input into the ARM by the user through the application, and then transmitted to the SPI driver by the ARM; If the transfer parameter is_poll value is a first set value, the SPI chip select pin of the target FPGA is pulled low, and the data to be transmitted is immediately transmitted to the target FPGA; if the transfer parameter is_poll value is a second set value, the data to be transmitted is transmitted to the target FPGA in a queue manner.

2. The optimization method for the SPI interface communication of ARM and FPGA according to claim 1, wherein Immediately transmit the data to be transmitted to the target FPGA, and then further include: Use the polling method to cyclically query the SPI transmission completion flag of the SPI status register. If the SPI transmission completion flag is found to be set, the SPI chip select pin of the target FPGA is pulled high to end the data transmission.

3. The optimization method for the SPI interface communication of ARM and FPGA according to claim 1, wherein Transmitting the data to be transmitted to the target FPGA in a queue manner includes: The current thread is suspended by the SPI driver, and an interrupt wake-up is performed after the SPI driver is completed until the data to be transmitted is completed.

4. The method for optimizing the SPI interface communication between the ARM and FPGA according to any one of claims 1 to 3, wherein: When the length of the data to be transmitted is greater than the preset bit width, the DMA controller is started to move the data to be transmitted.

5. The optimization method for SPI interface communication between ARM and FPGA according to claim 4, wherein Starting the DMA controller to move the data to be transmitted includes: The current thread is suspended by the DMA controller, and an interrupt wake-up is performed after the DMA controller completes the transfer, until the data to be transmitted is completed.

6. An optimized system for SPI interface communication between ARM and FPGA, wherein the ARM is used as SPI master mode and the FPGA is used as SPI slave mode; characterized in that: When the ARM transmits data to the target FPGA through the SPI interface, the ARM is used to determine the length of the data to be transmitted and judge the difference between the length of the data to be transmitted and the preset bit width. If the length of the data to be transmitted is less than or equal to the preset bit width, the ARM also determines the value of the transfer parameter is_poll; the value of the transfer parameter is_poll is input into the ARM by the user through the application program and then transmitted by the ARM to the SPI driver. If the transfer parameter is_poll value is a first set value, ARM pulls down the SPI chip select pin of the target FPGA through the SPI driver and immediately transmits the data to be transmitted to the target FPGA; if the transfer parameter is_poll value is a second set value, ARM transmits the data to be transmitted to the target FPGA in a queue manner.

7. The optimization system for SPI interface communication between ARM and FPGA according to claim 6, characterized in that, ARM drives the SPI chip select pin of the target FPGA low through SPI, and immediately transmits the data to be transmitted to the target FPGA. Then, ARM uses a polling method to cyclically query the SPI transmission completion flag of the SPI status register. If the SPI transmission completion flag is set, the SPI chip select pin of the target FPGA is pulled high to end the data transmission.

8. The optimization system for SPI interface communication between ARM and FPGA according to claim 6, characterized in that, When the length of the data to be transmitted is greater than the preset bit width, the ARM starts DMA to move the data to be transmitted.

Images