Failure analysis method and device of semiconductor structure and electronic equipment

Abstract

This invention provides a failure analysis method for semiconductor structures, applicable to the field of semiconductor technology. Specifically, it addresses a certain thin-film failure problem in semiconductor samples with thin-film structures made of low-k dielectric materials. By modifying conventional imaging conditions in existing technologies to TEM imaging conditions with a large aperture and a CL1 condenser lens stop, while extending the irradiation time, the high-voltage irradiation energy emitted by the TEM can be used to raise the temperature of the FIB sample. This temperature increase causes surface contraction and tension in the low-k dielectric thin-film structure, amplifying the problem of poor film adhesion. This solves the problem that conventional imaging conditions in existing technologies cannot detect the relatively weak thin-film interface failures in FIB samples, ultimately improving the efficiency of semiconductor structure failure analysis.

Description

A method, apparatus and electronic device for failure analysis of semiconductor structures Technical Field

[0001] This invention relates to the field of semiconductor chip failure analysis technology, and in particular to a method, apparatus and electronic device for failure analysis of semiconductor structures. Background Technology

[0002] As semiconductor integration increases and chip applications and operating environments become more diverse, the reliability requirements for chips are also becoming increasingly stringent. During research and development and production, rigorous reliability assessments are necessary. For failed samples, electrical and physical property failure analysis is required to identify the root cause of the failure and subsequently improve the process. Furthermore, as semiconductor process nodes continue to shrink, subtle process issues that have no significant impact at mature process nodes can have fatal consequences at advanced process nodes. Moreover, these influencing factors are often too minute, and due to limitations in instrument resolution or the analytical methods themselves, conventional physical property analysis methods cannot effectively pinpoint the cause of failure.

[0003] To address these issues, one approach is to develop more sophisticated analytical instruments to detect problems by increasing resolution or employing new analytical methods. However, this approach involves a long development cycle and very high instrument costs, and is sometimes limited by technological constraints that prevent its purchase and use. Another approach is to amplify existing relatively weak failure points through certain means, thereby identifying problems that are not easily detected.

[0004] Specifically, the failure analysis process commonly used in existing technologies is as follows: confirm the electrical properties of the failed chip, and then use instruments such as OM, SEM, FIB, and TEM to observe the physical property failure behavior of the sample, thereby analyzing the root cause of the failure. Figure 1 shows a bright-field cross-sectional image of a sample failure observed using conventional TEM in existing technologies; as shown in Figure 1, no obvious physical property anomalies were found in the bright-field cross-sectional image of the TEM. Therefore, we need to find other ways to analyze failure problems using existing instruments. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, and electronic device for failure analysis of semiconductor structures, in order to solve the problem that conventional imaging conditions used in the prior art cannot detect relatively weak thin film interface failures on the thin film interface in FIB samples, thereby improving the analysis efficiency of failure analysis of semiconductor structures.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a failure analysis method for semiconductor structures, which may include at least the following steps:

[0007] A FIB sample containing a target region is provided, wherein a thin film structure is disposed in the target region of the FIB sample, and the thin film structure has a thin film interface failure problem;

[0008] The FIB sample was imaged using a transmission electron microscope with adjusted imaging conditions to obtain TEM images.

[0009] Identify the thin film interface anomalies in the TEM image, and determine the failure cause corresponding to the thin film interface anomalies in the FIB sample based on the thin film interface anomalies and the preset sample failure background information.

[0010] Furthermore, the material of the thin film structure may specifically include a low-K dielectric with a dielectric constant of less than 5.

[0011] Furthermore, the imaging conditions of the transmission electron microscope after the imaging conditions are adjusted may specifically include: the aperture parameter range can be 70μm~200μm, the aperture mode of the first condenser lens is the condenser aperture mode, and the irradiation time range can be 2min~5min.

[0012] Furthermore, the preset sample failure background information may include: semiconductor process parameters of the thin film structure contained in the FIB sample or its WAT test parameters.

[0013] Furthermore, the step of determining the failure cause corresponding to the thin film interface anomaly point in the FIB sample based on the anomaly point at the thin film interface and the preset sample failure background information may specifically include:

[0014] The abnormal points at the thin film interface are compared with preset sample failure background information. Based on the correspondence between the parameter information contained in the preset sample failure background information and the failure cause, the failure cause corresponding to the semiconductor process parameters or its WAT test parameters in the thin film structure process included in the manufacturing of the FIB sample is determined.

[0015] Secondly, based on the same inventive concept as the aforementioned method for failure analysis of semiconductor structures, this invention also provides a device for failure analysis of semiconductor structures, which specifically may include: a sample preparation module, an image acquisition module, and a failure cause determination module; wherein...

[0016] The sample preparation module is used to provide a FIB sample containing a target region. A thin film structure is provided in the target region of the FIB sample, and the thin film structure has a thin film interface failure problem.

[0017] The image acquisition module is used to acquire images of the FIB sample using a transmission electron microscope with image acquisition conditions adjusted, so as to obtain TEM images;

[0018] The failure cause determination module is used to find thin film interface anomalies in the TEM image and determine the failure cause corresponding to the thin film interface anomalies in the FIB sample based on the thin film interface anomalies and preset sample failure background information.

[0019] Furthermore, the material of the thin film structure may specifically include a low-K dielectric with a dielectric constant of less than 5.

[0020] Furthermore, the imaging conditions of the transmission electron microscope after the imaging conditions are adjusted may specifically include: an aperture parameter range of 70μm to 200μm, a condenser aperture mode of the first condenser lens, and an irradiation time range of 2min to 5min. The aperture parameter is set to operate in a large aperture mode, and the irradiation time is preferably 3min.

[0021] Furthermore, the failure cause determination module in the failure analysis device provided by the present invention may specifically include a comparison unit; wherein,

[0022] The comparison unit can be specifically used to compare the abnormal points at the thin film interface with preset sample failure background information, so as to determine the failure cause corresponding to the semiconductor process parameters or its WAT test parameters in the thin film structure process included in the manufacturing of the FIB sample based on the correspondence between the parameter information contained in the preset sample failure background information and the failure cause.

[0023] Thirdly, based on the same inventive concept as the failure analysis method of the semiconductor structure, the present invention also provides an electronic device, which may specifically include a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0024] Memory, used to store computer programs;

[0025] When a processor executes a program stored in memory, it implements the steps of the failure analysis method for the semiconductor structure described in any of the first aspects.

[0026] Fourthly, based on the same inventive concept as the failure analysis method for the semiconductor structure, the present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method steps of the failure analysis method for the semiconductor structure described in any of the first aspects.

[0027] Fifthly, based on the same inventive concept as the failure analysis method for the semiconductor structure described above, the present invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the failure analysis method for the semiconductor structure described in any of the first aspects above.

[0028] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0029] In the failure analysis method for semiconductor structures provided by this invention, a certain thin film failure problem is addressed in semiconductor samples with thin film structures made of low-k dielectric material. This is achieved by modifying conventional imaging conditions in the prior art to TEM imaging conditions with a large aperture and a CL1 condenser lens stop, while simultaneously extending the irradiation time. This allows the high-voltage irradiation energy emitted by the TEM to raise the temperature of the FIB sample. The increased temperature causes the surface of the low-k dielectric thin film structure to shrink, generating tension and amplifying the problem of poor film adhesion. This solves the problem that conventional imaging conditions in the prior art cannot detect the relatively weak thin film interfaces at the film interfaces in the FIB sample, ultimately improving the efficiency of semiconductor structure failure analysis. Attached Figure Description

[0030] Figure 1 shows a bright-field cross-section of a TEM used in the prior art to observe sample failure using conventional TEM.

[0031] Figure 2 is a flowchart illustrating a failure analysis method for semiconductor structures provided in an embodiment of the present invention;

[0032] Figure 3 shows a TEM cross-sectional image of the M3 film obtained by taking pictures under conventional imaging conditions, a TEM cross-sectional image of all metal films including the metal interconnect structure, and a TEM cross-sectional image of the M3 film obtained by taking pictures under the imaging conditions adjusted by the present invention, provided in an embodiment of the present invention.

[0033] Figure 4 shows a TEM cross-sectional view of the NDC dielectric layer on the M3 film layer with thin film interface failure problem obtained by taking a picture under the adjusted imaging conditions of the present invention, and a TEM cross-sectional view of the NDC dielectric layer on the M2 film layer without abnormality problem obtained by taking a picture under the same adjusted imaging conditions of the present invention.

[0034] Figure 5 is a schematic diagram of a failure analysis device for a semiconductor structure provided in one embodiment of the present invention. Detailed Implementation

[0035] The failure analysis method, apparatus, and electronic device for semiconductor structures proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0036] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] As described in the background section, to address the problem that conventional physical property analysis methods cannot effectively identify the cause of failure due to limitations in instrument resolution or the analytical methods themselves, existing technologies often improve this issue in two ways: First, by developing more precise analytical instruments to improve resolution or new analytical methods to discover problems. However, this approach has a long development cycle and very high instrument costs, and is sometimes limited by technology, making it impossible to purchase and use. Second, by using certain methods to amplify existing relatively weak failure points, problems that are not easily detected can be found.

[0038] Specifically, regarding the two aspects raised in the existing technology and the aforementioned problems, the failure analysis process typically used in the existing technology is as follows: confirm the electrical characteristics of the failed chip, and then use instruments such as OM, SEM, FIB, and TEM to observe the physical property failure performance of the sample, thereby analyzing the root cause of the failure. As shown in Figure 1, no obvious physical property anomalies were found in the TEM bright-field cross-sectional image. Therefore, we need to find other methods to analyze failure problems using existing instruments.

[0039] However, when using the methods provided in the prior art, such as observing the failure manifestations of sample properties with a TEM instrument, the TEM images obtained cannot reflect the abnormal properties due to the conventional imaging method of the selected TEM.

[0040] To address this problem, the present invention aims to provide a method, apparatus, and electronic device for failure analysis of semiconductor structures, thereby solving the problem that conventional imaging conditions used in the prior art cannot detect relatively weak thin film interface failures on the thin film interfaces in FIB samples, thus improving the analysis efficiency of failure analysis of semiconductor structures.

[0041] Referring to Figure 2, which is a flowchart illustrating a failure analysis method for semiconductor structures provided by the present invention, the failure analysis method provided by the present invention may include at least the following steps:

[0042] Step S201: Provide a FIB sample containing a target region. The target region contained in the FIB sample has a thin film structure, and the thin film structure has a thin film interface failure problem.

[0043] Typically, when performing failure analysis on a semiconductor structure, a planar sample corresponding to the semiconductor device is first fabricated. Then, TEM images of this sample are taken to observe the failure points in a specific region of the semiconductor structure. Further processing, such as planar-to-cross sectioning, can be used to obtain cross-sectional samples of each failure point in the target region of the semiconductor device, allowing for further failure analysis. The semiconductor structure to be analyzed can be a patterned semiconductor device layer formed on a semiconductor substrate, such as a silicon substrate.

[0044] The failure analysis method provided by this invention is primarily used to analyze certain thin-film failure problems in semiconductor samples with thin-film structures made of low-k dielectric materials. The main inventive point or key aspect of this invention that solves this type of problem lies in: modifying the imaging conditions of TEM (Transmission of Biological Instruments) images. This allows the high-voltage irradiation energy emitted by the TEM to raise the temperature of the FIB (Film Injection Block) sample. This temperature increase causes surface contraction and tension in the low-k thin-film structure, thus amplifying thin-film adhesion problems. In other words, unlike conventional TEM imaging conditions, the failure analysis method in this invention uses a large aperture and a CL1 condenser lens stop, while extending the irradiation time, thereby amplifying potential problems in the sample and identifying relatively weak thin-film interface failures that cannot be detected under conventional imaging conditions.

[0045] In this embodiment, a low-k dielectric thin film structure can be fabricated on a semiconductor substrate made of silicon wafer using conventional semiconductor manufacturing processes. The region containing the low-k dielectric thin film structure is referred to as the target region. Then, FIB sample preparation is performed on the target region to obtain the FIB sample.

[0046] Step S202: Using a transmission electron microscope with adjusted imaging conditions, images of the FIB sample are acquired to obtain TEM images.

[0047] In this embodiment, after obtaining the FIB sample containing the target region using the above steps, and before taking a TEM image of the FIB sample, the imaging conditions of the TEM device are adjusted. Then, the TEM image of the FIB sample is acquired. Specifically, the imaging conditions of the transmission electron microscope after the imaging conditions are adjusted in this invention include: aperture parameter range of 70μm to 200μm, aperture mode of the first condenser lens is condenser aperture mode, and irradiation time range of 2min to 4min.

[0048] As a preferred example, the aperture parameters of the TEM can be adjusted to the range of parameters in the large aperture working mode, and the aperture mode of the first condenser lens CL1 can be adjusted to the condenser aperture mode. Then, in the working state of this mode, the FIB sample is irradiated for about 3 minutes to obtain the TEM image corresponding to the FIB sample containing the target area.

[0049] Subsequently, TEM images under different imaging conditions can be compared under conventional TEM imaging conditions (small aperture, partial light blocking, CL2 aperture, short-term irradiation of the sample). For details, please refer to Figures 3 and 4. In Figure 3, from left to right, the images are TEM cross-sectional images of the M3 film obtained under conventional imaging conditions, TEM cross-sectional images of all metal films including the metal interconnect structure, and TEM cross-sectional images of the M3 film obtained under the imaging conditions adjusted by this invention. In Figure 4, from left to right, the images are TEM cross-sectional images of the M3 film with thin film interface failure problems in the NDC dielectric layer, obtained under the imaging conditions adjusted by this invention, and TEM cross-sectional images of the M2 film without abnormal problems in the NDC dielectric layer, obtained under the same imaging conditions adjusted by this invention.

[0050] As shown in Figures 4 and 5, no obvious anomalies were found in the TEM images taken under the conventional imaging conditions. However, anomalies were found in the M3NDCfilm under the adjusted imaging conditions proposed in this invention. Further comparison of the M3 and M2NDCfilms under the adjusted imaging conditions (at the same time) revealed that only the M3NDCfilm exhibited anomalies. This indicates that the failure analysis method proposed in this invention has no significant impact on normal films.

[0051] Step S203: Identify the thin film interface anomalies in the TEM image, and determine the failure cause corresponding to the thin film interface anomalies in the FIB sample based on the thin film interface anomalies and the preset sample failure background information.

[0052] The semiconductor manufacturing process parameters or WAT test parameters of the thin film structure contained in the FIB sample are specified.

[0053] Furthermore, the step of determining the failure cause corresponding to the thin film interface anomaly point in the FIB sample based on the anomaly point at the thin film interface and preset sample failure background information includes:

[0054] Step S203.1: Compare the abnormal points at the thin film interface with the preset sample failure background information, so as to determine the failure cause corresponding to the semiconductor process parameters or its WAT test parameters in the thin film structure process included in the manufacturing of the FIB sample based on the correspondence between the parameter information contained in the preset sample failure background information and the failure cause.

[0055] In this embodiment, for example, the failure background information, such as the semiconductor manufacturing process and WAT test process of the thin film structure contained in the FIB sample, can be traced first. Then, it is found that before and after the WAT test of M3, the M3 NDC dielectric layer was demolded twice with a 36-hour wait in between. It is suspected that this caused the NDC dielectric film to be relatively thin, and problems are likely to occur at this position during the test. That is, the physical property analysis results obtained by the failure analysis method after adjusting the imaging conditions provided by the present invention are consistent with the online information.

[0056] Furthermore, based on the same inventive concept as the aforementioned semiconductor structure failure analysis method, as shown in Figure 5, this invention also provides a semiconductor structure failure analysis apparatus, which specifically may include: a sample preparation module 501, an image acquisition module 502, and a failure cause determination module 503; wherein,

[0057] The sample preparation module 501 is used to provide a FIB sample containing a target region. A thin film structure is provided in the target region of the FIB sample, and the thin film structure has a thin film interface failure problem.

[0058] The image acquisition module 502 is used to acquire images of the FIB sample using a transmission electron microscope with image acquisition conditions adjusted, so as to obtain TEM images;

[0059] The failure cause determination module 503 is used to find thin film interface anomalies in the TEM image and determine the failure cause corresponding to the thin film interface anomalies in the FIB sample based on the thin film interface anomalies and preset sample failure background information.

[0060] Furthermore, the material of the thin film structure may specifically include a low-K dielectric with a dielectric constant of less than 5.

[0061] Furthermore, the imaging conditions of the transmission electron microscope after the imaging conditions are adjusted may specifically include: an aperture parameter range of 70μm to 200μm, a condenser aperture mode of the first condenser lens, and an irradiation time range of 2min to 5min. The aperture parameter is set to operate in a large aperture mode, and the irradiation time is preferably 3min.

[0062] Furthermore, the failure cause determination module 403 in the failure analysis device provided by the present invention may specifically include a comparison unit; wherein,

[0063] The comparison unit can be specifically used to compare the abnormal points at the thin film interface with preset sample failure background information, so as to determine the failure cause corresponding to the semiconductor process parameters or its WAT test parameters in the thin film structure process included in the manufacturing of the FIB sample based on the correspondence between the parameter information contained in the preset sample failure background information and the failure cause.

[0064] In summary, the failure analysis method for semiconductor structures provided by this invention addresses a specific thin-film failure problem in semiconductor samples with low-k dielectric materials. It modifies conventional imaging conditions in existing technologies to TEM imaging conditions with a large aperture and a CL1 condenser lens stop, while simultaneously extending the irradiation time. This allows the high-voltage irradiation energy emitted by the TEM to raise the temperature of the FIB sample. The increased temperature causes surface contraction and tension in the low-k dielectric thin-film structure, amplifying the problem of poor film adhesion. This solves the problem that conventional imaging conditions in existing technologies cannot detect the relatively weak thin-film interface failures in FIB samples, ultimately improving the efficiency of semiconductor structure failure analysis.

[0065] This invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0066] Memory, used to store computer programs;

[0067] When the processor executes a program stored in the memory, it implements the steps described in the embodiments of the failure analysis method for the above-described semiconductor structure.

[0068] For details on the specific implementation of each step of this method and related explanations, please refer to the method embodiments shown in Figures 2 to 4 above, which will not be elaborated here.

[0069] In addition, other implementations of the application setup method implemented by the processor executing the program stored in the memory are the same as those mentioned in the aforementioned method embodiment section, and will not be repeated here.

[0070] The communication bus of the aforementioned user terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not indicate that there is only one bus or one type of bus.

[0071] The communication interface is used for communication between the aforementioned user terminal and other devices.

[0072] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0073] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0074] In another embodiment of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, it implements the steps of the above-described failure analysis method for semiconductor structures.

[0075] In another embodiment of the present invention, the present invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the above-described semiconductor structure failure analysis method.

[0076] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0077] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0078] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for apparatus, user terminals, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A failure analysis method for semiconductor structures, characterized in that, The method includes at least the following steps: providing a FIB sample containing a target region, wherein a thin film structure is disposed in the target region of the FIB sample, and the thin film structure has a thin film interface failure problem; acquiring images of the FIB sample using a transmission electron microscope with adjusted imaging conditions to obtain TEM images; identifying thin film interface anomalies in the TEM images, and determining the failure cause corresponding to the thin film interface anomalies in the FIB sample based on the thin film interface anomalies and preset sample failure background information; the material of the thin film structure includes a low-K dielectric with a dielectric constant lower than 5; the imaging conditions of the transmission electron microscope with adjusted imaging conditions include: aperture parameter range of 70µm~200µm, first condenser aperture mode of condenser aperture mode, and irradiation time range of 2min~5min.

2. The failure analysis method for semiconductor structures as described in claim 1, characterized in that, The preset sample failure background information includes: semiconductor process parameters of the thin film structure contained in the FIB sample or its WAT test parameters.

3. The failure analysis method for semiconductor structures as described in claim 2, characterized in that, The step of determining the failure cause corresponding to the thin film interface anomaly point in the FIB sample based on the thin film interface anomaly point and the preset sample failure background information includes: comparing the thin film interface anomaly point with the preset sample failure background information, so as to determine the failure cause corresponding to the semiconductor process parameters or its WAT test parameters in the process of manufacturing the thin film structure contained in the FIB sample according to the correspondence between the parameter information contained in the preset sample failure background information and the failure cause.

4. A failure analysis device for semiconductor structures, characterized in that, include: The sample preparation module is used to provide a FIB sample containing a target region, wherein a thin film structure is disposed in the target region of the FIB sample, and the thin film structure has a thin film interface failure problem; The image acquisition module is used to acquire images of the FIB sample using a transmission electron microscope with adjusted imaging conditions to obtain TEM images; The failure cause determination module is used to identify thin film interface anomalies in the TEM image and determine the failure cause corresponding to the thin film interface anomalies in the FIB sample based on the thin film interface anomalies and preset sample failure background information; the material of the thin film structure includes a low-K dielectric with a dielectric constant of less than 5; the imaging conditions of the transmission electron microscope after the imaging conditions are adjusted include: aperture parameter range of 70µm~200µm, first condenser aperture mode is condenser aperture mode, and irradiation time range of 2min~5min.

5. The failure analysis apparatus for semiconductor structures as described in claim 4, characterized in that, The failure cause determination module includes a comparison unit, used to compare the abnormal points at the thin film interface with preset sample failure background information, so as to determine the failure cause corresponding to the semiconductor process parameters or its WAT test parameters in the thin film structure process included in the manufacturing of the FIB sample according to the correspondence between the parameter information contained in the preset sample failure background information and the failure cause.

6. An electronic device, characterized in that, The system includes a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other via the communication bus. The memory is used to store computer programs. When the processor executes the program stored in the memory, it implements the steps of the failure analysis method for the semiconductor structure according to any one of claims 1 to 3.

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