Method for capacity promotion of ssd, nand backend hardware circuit, device, equipment and medium

Abstract

The application discloses a capacity promotion method of an SSD, a NAND backend hardware circuit, a device, equipment and a medium, and relates to the technical field of computer storage. The method is applied to the NAND backend hardware circuit, wherein the NAND backend hardware circuit comprises a computer flash memory equipment controller, a bus switch and a computer flash memory equipment particle. The method comprises the following steps: obtaining a chip select signal of target channel selection of the computer flash memory equipment controller and an output signal of a general input / output interface; transmitting the chip select signal and the output signal to a low-speed control area and a high-speed control area of the bus switch, respectively; determining a target chip select signal by using a low-speed control output signal obtained by expanding the chip select signal through a decoder function, and determining a target high-speed signal transmission channel by using a selection signal determined by the output signal in the high-speed control area, so as to perform data operation on the computer flash memory equipment particle. Through the technical scheme of the application, the capacity of the solid state disk can be doubled under the condition of hardware resource limitation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer storage, in particular to a capacity promotion method of an SSD, a NAND backend hardware circuit, a device, an apparatus and a medium. BACKGROUND

[0002] It is well known that, compared with a mechanical hard disk (HDD), a solid state disk (SSD) has great advantages in speed, power consumption, capacity, noise, reliability and other performances. At the present stage, although the mechanical hard disk has certain advantages in price, with the emergence of large-capacity FLASH flash memory particles, the capacity of the SSD will become larger and larger, so that it is more widely used in servers, storage and other devices.

[0003] With the increasing demand for SSDs, the overall capacity demand of single-disk SSDs is also increasing, from the mainstream 2T capacity, to 4T capacity, and then to 8T capacity. Due to the limitation of the number of channels of the computer flash memory device controller (hereinafter referred to as NAND controller) or the number of chip selection signals (Chip Enable, hereinafter referred to as CE) of each channel of the NAND controller, the maximum capacity of a specific single NAND controller can only reach 4T or 8T. Although the capacity of a single computer flash memory device particle (hereinafter referred to as NAND package) can be increased to solve the implementation of some specific large-capacity points, due to the limitation of the number of channels of the NAND controller, the number of CEs of each channel, the adaptation of the specific NAND controller model and other hardware resource conditions, the maximum capacity of the single-disk SSD cannot be improved, so that the competitiveness of the SSD disk at the large-capacity point is missing.

[0004] In summary, how to realize the SSD disk at a large-capacity point under the condition of the limitation of the number of channels of the NAND controller, the number of CEs of each channel, the adaptation of the specific NAND controller model and other hardware resources, and improve the product competitiveness of the SSD disk is a problem to be solved at present. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a capacity promotion method of an SSD, a NAND backend hardware circuit, a device, an apparatus and a medium, which can realize the SSD disk at a large-capacity point under the condition of the limitation of the number of channels of the NAND controller, the number of CEs of each channel, the adaptation of the specific NAND model and other hardware resources, and improve the product competitiveness of the SSD disk. The specific scheme is as follows:

[0006] The first aspect discloses a capacity upgrading method of a solid state disk, applied to a computer flash device backend hardware circuit, the computer flash device backend hardware circuit comprising a computer flash device controller, a bus switch and a computer flash device particle, wherein the method comprises:

[0007] obtaining a chip select signal of target channel selection of the computer flash device controller, and obtaining an output signal of a general input / output interface of the computer flash device controller;

[0008] transmitting the chip select signal to a low-speed control area of the bus switch, and transmitting the output signal to a high-speed control area of the bus switch;

[0009] expanding the chip select signal in the low-speed control area by a decoder function of the bus switch to obtain a low-speed control output signal, and determining a selection signal for selecting a high-speed signal transmission channel of the computer flash device particle in the high-speed control area by the output signal;

[0010] determining a target chip select signal of the computer flash device particle by the low-speed control output signal, and determining a target high-speed signal transmission channel by the selection signal, so as to perform data operation on the computer flash device particle through the target high-speed signal transmission channel.

[0011] Optionally, the expanding the chip select signal in the low-speed control area by the decoder function of the bus switch to obtain the low-speed control output signal, and determining the selection signal for selecting the high-speed signal transmission channel of the computer flash device particle in the high-speed control area by the output signal comprises:

[0012] setting an ENB pin in the bus switch to a low level, then expanding the chip select signal in the low-speed control area to obtain the low-speed control output signal, and determining the selection signal for selecting the high-speed signal transmission channel of the computer flash device particle in the high-speed control area by the output signal.

[0013] Optionally, the expanding the chip select signal in the low-speed control area by the decoder function of the bus switch to obtain the low-speed control output signal, and determining the selection signal for selecting the high-speed signal transmission channel of the computer flash device particle in the high-speed control area by the output signal comprises:

[0014] setting the first CFG pin in the bus switch to low level, connecting the low-speed control area to obtain control logic between the chip select signal and the low-speed control output signal, and then expanding the chip select signal based on the control logic between the chip select signal and the low-speed control output signal to obtain a low-speed control output signal;

[0015] setting the second CFG pin in the bus switch to high level, connecting the high-speed control area to obtain control logic between the selection signal and the high-speed signal transmission channel, and then determining the selection signal of the high-speed signal transmission channel for selecting the computer flash memory device grain based on the control logic between the selection signal and the high-speed signal transmission channel.

[0016] Optionally, the decoder function of the bus switch expands the chip select signal in the low-speed control area to obtain a low-speed control output signal, including:

[0017] The decoder function of the bus switch expands the chip select signal in the low-speed control area and sets the ENCB pin in the bus switch to low level to obtain a low-speed control output signal.

[0018] Optionally, the chip select signal of the target channel selection of the computer flash memory device controller includes:

[0019] The chip select signal corresponding to the channel selected by the lowest bit to the channel corresponding to the first preset number of high bits in the computer flash memory device controller is obtained.

[0020] Optionally, the target chip select signal of the computer flash memory device grain is determined by the low-speed control output signal, and the target high-speed signal transmission channel is determined by the selection signal, so as to perform data operation on the computer flash memory device grain through the target high-speed signal transmission channel, including:

[0021] The target chip select signal of the computer flash memory device grain is determined by the low-speed control output signal, and the target high-speed signal transmission channel is determined by the selection signal, so as to determine the operation target in the computer flash memory device grain based on the target chip select signal and the target high-speed signal transmission channel, and then perform data operation on the operation target through the target high-speed signal transmission channel by using the computer flash memory device controller.

[0022] In a second aspect, the present application discloses a computer flash memory device backend hardware circuit, including a computer flash memory device controller, a bus switch and a computer flash memory device grain; wherein,

[0023] The computer flash device controller is configured to acquire a chip select signal selected by a target channel, and transmit the chip select signal to a low-speed control area of the bus switch; and acquire an output signal of a general input / output interface, and transmit the output signal to a high-speed control area of the bus switch.

[0024] The bus switch is connected with the computer flash device controller and the computer flash device particle respectively, and is configured to expand the chip select signal in the low-speed control area by a decoder function to obtain a low-speed control output signal, and determine a selection signal for selecting a high-speed signal transmission channel of the computer flash device particle in the high-speed control area by the output signal.

[0025] The computer flash device particle is configured to determine a target chip select signal by the low-speed control output signal of the bus switch, and determine a target high-speed signal transmission channel of the computer flash device particle by the selection signal of the bus switch, so as to perform data operation on the computer flash device particle through the target high-speed signal transmission channel.

[0026] In a third aspect, the application discloses a capacity improving device of a solid state disk, which is applied to a computer flash device back-end hardware circuit, and the computer flash device back-end hardware circuit comprises a computer flash device controller, a bus switch and a computer flash device particle.

[0027] The signal acquisition module is configured to acquire a chip select signal selected by a target channel of the computer flash device controller, and acquire an output signal of a general input / output interface of the computer flash device controller.

[0028] The signal transmission module is configured to transmit the chip select signal to a low-speed control area of the bus switch, and transmit the output signal to a high-speed control area of the bus switch.

[0029] The decoding expansion module is configured to expand the chip select signal in the low-speed control area by a decoder function of the bus switch to obtain a low-speed control output signal, and determine a selection signal for selecting a high-speed signal transmission channel of the computer flash device particle in the high-speed control area by the output signal.

[0030] The data communication module is configured to determine a target chip select signal of the computer flash device particle by the low-speed control output signal, and determine a target high-speed signal transmission channel by the selection signal, so as to perform data operation on the computer flash device particle through the target high-speed signal transmission channel.

[0031] In a fourth aspect, the present application discloses an electronic device, comprising a processor and a memory; wherein the memory is used to store a computer program, the computer program is loaded and executed by the processor to realize the capacity improvement method of the solid state disk as described above.

[0032] In a fifth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to realize the capacity improvement method of the solid state disk as described above.

[0033] The present application provides a capacity improvement method of a solid state disk, applied to a computer flash memory device backend, the computer flash memory device backend hardware circuit comprising a computer flash memory device controller, a bus switch and a computer flash memory device particle; wherein the method comprises: obtaining a chip select signal selected by a target channel of the computer flash memory device controller, and obtaining an output signal of a general input / output interface of the computer flash memory device controller; transmitting the chip select signal to a low-speed control area of the bus switch, and transmitting the output signal to a high-speed control area of the bus switch; expanding the chip select signal in the low-speed control area through a decoder function of the bus switch to obtain a low-speed control output signal, and determining a selection signal for selecting a high-speed signal transmission channel of the computer flash memory device particle in the high-speed control area by using the output signal; determining a target chip select signal of the computer flash memory device particle by the low-speed control output signal, and determining a target high-speed signal transmission channel by the selection signal, so as to perform data operation on the computer flash memory device particle through the target high-speed signal transmission channel.

[0034] It can be seen that, by the chip selection signal selected by the target channel of the NAND controller, the decoder function of the bus switch is used to decode and expand in the low-speed control area, and then the target chip selection signal of the NAND package is determined by the low-speed control output signal. Since the decoder function of the bus switch expands the chip selection signal, the expanded output can select more chip selection signals of the NAND package, realize the decoding expansion of the chip selection signal, and further expand the number of connected NAND packages, improve the capacity of the SSD, and thus eliminate the capacity limitation of the SSD caused by the fact that the chip selection signal of the NAND package can only be selected by the fixed number of channels of the NAND controller in the prior art, realize the doubling of the capacity of the SSD under the limitation of the number of channels of the NAND controller, the number of CEs of each channel, and the adaptation to the specific NAND controller model, and fill in the large-capacity point of the SSD, and improve the product competitiveness of the SSD. In addition, the selection signal is determined in the high-speed control area of the bus switch by the output signal of the general input / output interface, and then the target high-speed signal transmission channel of the NAND package is determined, so as to perform data operation on the NAND package through the target high-speed signal transmission channel. In this way, the hardware design circuit combines with the software logic control, realizes the point-to-point communication of the high-speed signal through the switch control of the high-speed control area, and overall improves the capacity of the SSD and the high-speed signal interface rate of the NAND package.

[0035] In addition, the NAND backend hardware circuit, device, equipment and medium provided by the present application correspond to the capacity improvement method of the SSD, and have the same effect as above. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0037] Figure 1 Flow chart of the capacity improvement method of the solid state disk disclosed by the present application;

[0038] Figure 2 Schematic diagram of the NAND backend hardware circuit for realizing 8TB capacity point of each channel decoding to 16CE disclosed by the present application;

[0039] Figure 3 Schematic diagram of the NAND backend hardware circuit for realizing 4TB capacity point of each channel decoding to 8CE disclosed by the present application;

[0040] Figure 4 A structural schematic diagram of a computer flash memory device backend hardware circuit disclosed by the application is shown in the figure;

[0041] Figure 5 A structural schematic diagram of a capacity improvement device of a solid state disk disclosed by the application is shown in the figure;

[0042] Figure 6 A structural diagram of an electronic device disclosed by the application is shown in the figure. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the application.

[0044] At present, although the capacity of a single NAND package can be increased to solve the implementation of some specific large-capacity points, because of the hardware resource limitation conditions such as the number of channels of a NAND controller, the number of CEs of each channel, and the adaptation to a specific NAND controller model, the maximum capacity of a single-disk SSD cannot be improved, so that the competitiveness of the SSD disk at the large-capacity point is lost.

[0045] Therefore, the application provides a capacity improvement scheme of a solid state disk, which can realize a large-capacity-point SSD disk under the hardware resource limitation conditions such as the number of channels of a NAND controller, the number of CEs of each channel, and the adaptation to a specific NAND model, and improve the product competitiveness of the SSD disk.

[0046] The embodiment of the application discloses a capacity improvement method of a solid state disk, which is shown in the figure. Figure 1 As shown in the figure, the application is applied to a computer flash memory device backend hardware circuit, and the computer flash memory device backend hardware circuit comprises a computer flash memory device controller, a bus switch and a computer flash memory device particle. For the convenience of description, the U.2 NVMe SSD widely used in the market is taken as an example in the embodiment of the application, and the Microchip PCIe3.0 controller PM8632 and the 1:4 high-speed bus switch MX0141KA1 chip of the Renesas manufacturer are used. The controller is an 8-channel (independent data bus) NAND controller (computer flash memory device controller), each channel supports 8 CEs, and the subsequent description is omitted. The method comprises the following steps:

[0047] Step S11: obtaining a chip selection signal of a target channel selection of the computer flash memory device controller, and obtaining an output signal of a general input / output interface of the computer flash memory device controller.

[0048] In the embodiment of the present application, the chip select signal corresponding to the selected channel in the computer flash memory device controller from the channel corresponding to the lowest bit to the channel corresponding to the first preset number of high bits is obtained. That is, the first preset number of channels from low to high in the NAND controller are selected as the target channel, and the CE signal of the target channel is obtained, so as to determine the low-speed control input signal of the bus switch subsequently. In addition, the output signal output by the general purpose input / output interface (General Purpose Input Output, hereinafter referred to as GPIO) in the NAND controller is obtained, so as to determine the selection signal for selecting the high-speed signal transmission channel for data transmission in the bus switch subsequently.

[0049] For example, the CE signals CE0_n-CE3_n of the NAND controller are selected, and the CE0_n-CE3_n in the CE signal of each channel are connected to CIN[0]-CIN[3] of the bus switch as the low-speed control input signal of the bus switch. It should be noted that if the signals of CE4_n-CE7_n are used, 1 group of high-speed signals DQ0-DQ7 / DQS / RE / ALE / CLE / WE will be added, a total of 2 groups of high-speed signals are connected in parallel, which will increase the signal stub, resulting in longer reflection time and poorer integrity, therefore, only 4 CE signals are used for CE expansion in the embodiment of the present application.

[0050] Step S12: transmitting the chip select signal to the low-speed control area of the bus switch, and transmitting the output signal to the high-speed control area of the bus switch.

[0051] In the embodiment of the present application, the chip select signal corresponding to the selected target channel in the NAND controller is transmitted to the low-speed control area of the bus switch, and is decoded and expanded as the low-speed control input signal of the bus switch. As shown in Figure 2 CH0 in the NAND controller is taken as an example, the CE signals CE0_n-CE3_n in CH0 are connected to the low-speed control input signals CIN[0]-CIN[3] respectively, that is, CH0_CE0_n is connected to the CIN[0] signal of the MX0141KA1 chip; CH0_CE1_n is connected to the CIN[1] signal of the MX0141KA1 chip; CH0_CE2_n is connected to the CIN[2] signal of the MX0141KA1 chip; and so on, which will not be described one by one here.

[0052] In the embodiments of the present application, the GPIO0 / GPIO1 of the NAND controller end is connected with SEL[0] / SEL[1] in the high-speed control area of the bus switch, that is, GPIO[1:0] is connected with SEL[1:0] in correspondence, and the input of SEL[1:0] signal is controlled by using GPIO[1:0].

[0053] Step S13: the chip enable signal is expanded in the low-speed control area by the decoder function of the bus switch to obtain a low-speed control output signal, and the output signal is used to determine a selection signal of a high-speed signal transmission channel for selecting the computer flash device grain in the high-speed control area.

[0054] It can be understood that the data transmission can be initiated concurrently among the channels of the NAND controller, the data bus is shared under the same channel, and the corresponding target is selected by different CE, and a NAND independent concurrent unit target is connected under the CE to perform NAND internal operation.

[0055] As Figure 3As shown in the schematic diagram of the NAND controller controlling the NAND package in the traditional SSD, all 8 CEs of each channel of the controller are utilized, and since each NAND package has 4 CEs, 2 NAND packages can be expanded under hardware connection, resulting in that the capacity of the SSD is limited by the number of CEs supported by the NAND controller, the number of NAND packages mounted by the NAND controller is limited, and the maximum capacity supported by the NAND controller is limited. For example, for Kioxia Bics496 layer NAND this generation of particles, the general material is 256 Gb / die ODP (Octal Die Package) NAND particles, each NAND package has 4 targets, each target includes 2 dies, and each die has a capacity of 256 Gb. Since 1 Byte = 8 bits, the capacity of a single NAND is 256 Gb*2*4 = 256 GB, each channel corresponds to 512 GB, and 8 channels are combined into a maximum of 4 TB overall capacity space. In the embodiment of the present application, the decoder function of the bus switch is used to decode 4 CEs into 16 CEs in the low-speed control area, and the low-speed control output signals CIO[0]~CIO

[15] of the bus switch are connected to the CE signals of the 4 NAND packages, respectively. Each low-speed control output signal corresponds to a NAND target in the NAND package. Through 16 groups of low-speed control output signals CIO[0]~CIO

[15] , that is, through CIO[0:15], each CE of each particle NAND package is accessed. For example: the CIO[0] signal of the MX0141KA1 chip is connected to the CE0 signal of the NAND package1; the CIO[1] signal is connected to the CE2 signal of the NAND package1; the CIO[2] signal is connected to the CE1 signal of the NAND package1; the CIO[3] signal is connected to the CE3 signal of the NAND package1, and the hardware connection of the remaining NAND packages 2, 3 and 4 is similar and will not be repeated here. In this way, the CE of the connectable NAND package corresponding to each channel is expanded by one, that is, from originally connecting 2 NAND packages per channel to connecting 4 NAND packages per channel, corresponding to 1 TB capacity, 8 channels are combined into a maximum of 8 TB overall capacity space, realizing the doubling of the SSD capacity under the limitation of the number of channels of the NAND controller, the number of CEs of each channel, and the adaptation of the specific NAND controller model, etc. hardware resources, filling the SSD of large capacity points, and improving the product competitiveness of the SSD.

[0056] Specifically, when performing decoding expansion, the first CFG pin in the bus switch is set to low level, and the low-speed control area is connected to obtain the control logic between the chip select signal and the low-speed control output signal, and then the chip select signal is expanded based on the control logic between the chip select signal and the low-speed control output signal to obtain the low-speed control output signal. Wherein, the control logic between the chip select signal and the low-speed control output signal is shown in Table 1.

[0057] Table 1

[0058]

[0059] In the embodiment of the application, since the selection signals SEL[0] / SEL[1] for selecting the high-speed signal transmission channel of the NAND package are respectively connected with the GPIO0 / GPIO1 of the NAND controller, the channel selection between the high-speed signals IN[15:0] and the high-speed signals port A[15:0] / port B[15:0] / port C[15:0] / port D[15:0] can be controlled by the selection signals. It should be noted that the four groups of port buses port A / port B / port C / port D of the bus switch are respectively connected with the four groups of NAND buses of the NAND package1 / NAND package2 / NAND package3 / NAND package4; the DQ0-DQ7 / DQS / RE / ALE / CLE / WE high-speed signals of the NAND controller are respectively connected with the IN[15:0] signals of the bus switch, so that the 15 groups of signals are used to determine which high-speed signal transmission channel of the NAND package is selected, and further determine the target corresponding to the operation.

[0060] Specifically, when performing the decoder function, the second CFG pin in the bus switch is set to high level, and the high-speed control area is connected to obtain the control logic between the selection signal and the high-speed signal transmission channel, and then the selection signal for selecting the high-speed signal transmission channel of the computer flash device particle is determined based on the control logic between the selection signal and the high-speed signal transmission channel. Wherein, the control logic between the selection signal and the high-speed signal transmission channel is shown in Table 2, when SEL[1:0] = 00, IN[15:0] selects port A; when SEL[1:0] = 01, IN[15:0] selects port B; when SEL[1:0] = 10, IN[15:0] selects port C; when SEL[1:0] = 11, IN[15:0] selects port D.

[0061] Table II

[0062]

[0063] In addition, the ENCB pin in the bus switch is set to low, which is used to select whether CIO[0:15] is enabled as an output signal, that is, when the ENCB pin is set to low, the selected CE signal and the corresponding target are determined according to the control logic in Table I. The ENB pin in the bus switch is set to low, which is used to enable the device and the A / B / C / D channel, at this time, the CIN[3:0] input is defaulted and the CIO[15:0] decoding output function is enabled. That is, when the ENB pin is set to low, the high-speed transmission channel is selected according to the control logic in Table II, and then the NAND package and the target are determined according to the high-speed transmission channel. It should be noted that in the target selection, low level is effective, and which CE output low level represents which CE is selected.

[0064] Step S14: determining the target chip select signal of the computer flash memory device particle through the low-speed control output signal, and determining the target high-speed signal transmission channel through the selection signal, so as to perform data operation on the computer flash memory device particle through the target high-speed signal transmission channel.

[0065] In the embodiment of the present application, the target chip select signal of the NAND package can be determined according to the control logic provided in Table I, and the selected transmission target high-speed signal transmission channel can be determined according to the control logic provided in Table II. The target in the NAND package is determined based on the target chip select signal and the target high-speed signal transmission channel, and then the data operation on the target is performed through the target high-speed signal transmission channel by using the NAND controller.

[0066] For example, Figure 2As shown, when the NAND controller end CE0_n~CE3_n output 1111, corresponding CIN[3:0]=1111, according to table one can know decoding output CIO[15:0]=1111_1111_1111_1110, then the NAND package1 CE0 signal selected; NAND controller end GPIO[1:0] output 00, corresponding SEL[1:0] is 00, according to table two can know high speed bus channel IN[0:15] gating port A; NAND controller end CH0 of 15 groups of high speed signal through the bus switch chip to reach A port, and then to the NAND package1 NAND bus, realize the controller channel CH0 and NAND package1 target0 read, write, erase and other related operations. When the NAND controller end CE0_n~CE3_n output 1110, corresponding CIN[3:0]=1110, according to table one can know decoding output CIO[15:0]=1111_1111_1111_1101, then the NAND package1 CE2 signal selected; NAND controller end GPIO[1:0] output 00, corresponding SEL[1:0] is 00, according to table two can know high speed bus channel IN[0:15] gating port A; NAND controller end CH0 of 15 groups of high speed signal through the bus switch chip to reach A port, and then to the NAND package1 NAND bus, realize the controller channel CH0 and NAND package1 target2 read, write, erase and other related operations. When the NAND controller end CE0_n~CE3_n output 1101, corresponding CIN[3:0]=1101, according to table one can know decoding output CIO[15:0]=1111_1111_1111_1011, then the NAND package1 CE1 signal selected; NAND controller end GPIO[1:0] output 00, corresponding SEL[1:0] is 00, according to table two can know high speed bus channel IN[0:15] gating port A; NAND controller end CH0 of 15 groups of high speed signal through the bus switch chip to reach A port, and then to the NAND package1 NAND bus, realize the controller channel CH0 and NAND package1 target1 read, write, erase and other related operations.When the CE0_n~CE3_n of the NAND controller end outputs 1101, the corresponding CIN[3:0]=1100, according to Table 1, the decoding output CIO[15:0]=1111_1111_1111_0111, then the CE3 signal of the NAND package1 is selected; at the same time, the GPIO[1:0] of the NAND controller end outputs 00, the corresponding SEL[1:0] is 00, according to Table 2, the high-speed bus channel IN[0:15] selects the port A; at this time, the NAND 15 groups of high-speed signals of the CH0 of the NAND controller end pass through the high-speed switch chip to reach the A port, and then reach the NAND bus of the NAND package1, realizing the reading, writing, erasing and other related operations of the controller channel CH0 and the target3 in the NAND package1. The NAND controller realizes the control of the SEL[1:0] level through the GPIO[1:0], and realizes the channel selection between the high-speed channels IN / Port A / B / C / D and the CE decoding control between CIN[3:0] / CIO[15:0] by combining the control logic of the CH0_CE0_n~CH0_CE3_n signals. The software and hardware logic methods of CH0 and NAND package2 / NAND package3 / NAND package4 are similar to the above, which will not be described here.

[0067] In addition, for the hardware resource limitation conditions such as the number of channels of the NAND controller, the number of CEs of each channel, and the adaptation to specific NAND controller models, the single-disk capacity of other SATA / SAS SSDs can also be improved.

[0068] The application provides a capacity improvement method of a solid state disk, applied to a computer flash memory device backend, the computer flash memory device backend hardware circuit comprising a computer flash memory device controller, a bus switch and a computer flash memory device particle; wherein the method comprises: acquiring a chip select signal of a target channel selection of the computer flash memory device controller, and acquiring an output signal of a general input / output interface of the computer flash memory device controller; transmitting the chip select signal to a low-speed control area of the bus switch, and transmitting the output signal to a high-speed control area of the bus switch; expanding the chip select signal in the low-speed control area by a decoder function of the bus switch to obtain a low-speed control output signal, and determining a selection signal for selecting a high-speed signal transmission channel of the computer flash memory device particle in the high-speed control area by using the output signal; determining a target chip select signal of the computer flash memory device particle by the low-speed control output signal, and determining a target high-speed signal transmission channel by the selection signal, so as to perform data operation on the computer flash memory device particle through the target high-speed signal transmission channel.

[0069] It can be seen that, by the chip select signal selected by the target channel of the NAND controller, the decoder function of the bus switch is used to decode and expand in the low-speed control area, and then the target chip select signal of the NAND package is determined by the low-speed control output signal. Since the decoder function of the bus switch expands the chip select signal, the expanded output can select more chip select signals of the NAND package, realizes the decoding expansion of the chip select signal, and further expands the number of connected NAND packages, improves the capacity of the SSD, and thus eliminates the capacity limitation of the SSD caused by the fact that the chip select signal of the NAND package can only be selected by the fixed number of channels of the NAND controller in the prior art, realizes the doubling of the capacity of the SSD under the limitation of the number of channels of the NAND controller, the number of CEs of each channel, and the adaptation to the specific NAND controller model, and fills in the large-capacity point of the SSD, and improves the product competitiveness of the SSD. In addition, the selection signal is determined in the high-speed control area of the bus switch by the output signal of the general input / output interface, and then the target high-speed signal transmission channel of the NAND package is determined, so as to perform data operation on the NAND package through the target high-speed signal transmission channel. In this way, the hardware design circuit combines with the software logic control, realizes the point-to-point communication of the high-speed signal through the switch control of the high-speed control area, and overall improves the capacity of the SSD and the high-speed signal interface rate of the NAND package.

[0070] The embodiment of the present application discloses a computer flash device backend hardware circuit, referring to Figure 4 As shown in the figure, it comprises a computer flash device controller, a bus switch and a computer flash device particle; wherein,

[0071] The computer flash device controller is used for acquiring a chip select signal selected by a target channel, and transmitting the chip select signal to a low-speed control area of the bus switch, and acquiring an output signal of a general input / output interface, and transmitting the output signal to a high-speed control area of the bus switch;

[0072] The bus switch is connected with the computer flash device controller and the computer flash device particle respectively, and is used for expanding the chip select signal in the low-speed control area by a decoder function to obtain a low-speed control output signal, and determining a selection signal of a high-speed signal transmission channel of the computer flash device particle by the output signal in the high-speed control area by the decoder function;

[0073] The computer flash memory device particle determines a target chip select signal through the low-speed control output signal of the bus switch, and determines a target high-speed signal transmission channel of the computer flash memory device particle through the selection signal of the bus switch, so as to perform data operation on the computer flash memory device particle through the target high-speed signal transmission channel.

[0074] More specific descriptions about the computer flash memory device controller, the bus switch and the computer flash memory device particle can refer to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

[0075] It can be seen that the chip select signal selected by the target channel of the NAND controller is decoded and expanded in the low-speed control area by the decoder function of the bus switch, and then the target chip select signal of the NAND package is determined through the low-speed control output signal. Since the decoder function of the bus switch expands the chip select signal, the expanded output can select more chip select signals of the NAND package, realizes the decoding expansion of the chip select signal, and further expands the number of connected NAND packages, improves the capacity of the SSD, and therefore eliminates the capacity limitation of the SSD caused by the fact that the chip select signal of the NAND package can only be selected by the fixed number of channels of the NAND controller in the prior art, realizes the doubling of the capacity of the SSD under the limitation of the number of channels of the NAND controller, the number of CEs of each channel, and the adaptation to the specific NAND controller model, and fills in the large-capacity point of the SSD, and improves the product competitiveness of the SSD. In addition, the selection signal is determined in the high-speed control area of the bus switch through the output signal of the general input / output interface, and then the target high-speed signal transmission channel of the NAND package is determined, so as to perform data operation on the NAND package through the target high-speed signal transmission channel. In this way, the hardware design circuit combines with the software logic control, realizes the point-to-point communication of the high-speed signal through the switch control of the high-speed control area, and overall improves the capacity of the SSD and the high-speed signal interface rate of the NAND package.

[0076] Correspondingly, the embodiment of the application also discloses a capacity improving device of an SSD, as shown in Figure 5 The computer flash memory device controller, the bus switch and the computer flash memory device particle, and the device comprises:

[0077] The signal acquisition module 11 is configured to acquire the chip select signal selected by the target channel of the computer flash memory device controller, and acquire the output signal of the general input / output interface of the computer flash memory device controller.

[0078] The signal transmission module 12 is configured to transmit the chip select signal to a low-speed control area of the bus switch and transmit the output signal to a high-speed control area of the bus switch.

[0079] The decoding expansion module 13 is configured to expand the chip select signal in the low-speed control area by a decoder function of the bus switch to obtain a low-speed control output signal and determine a selection signal for selecting a high-speed signal transmission channel of the computer flash device grain in the high-speed control area by using the output signal.

[0080] The data communication module 14 is configured to determine a target chip select signal of the computer flash device grain by the low-speed control output signal and determine a target high-speed signal transmission channel by the selection signal to perform data operation on the computer flash device grain through the target high-speed signal transmission channel.

[0081] The above-mentioned more specific working processes of the various modules can refer to the corresponding contents disclosed in the foregoing embodiments, and will not be described here.

[0082] Therefore, by the above-mentioned scheme of the embodiment, the computer flash device backend is applied, the computer flash device backend hardware circuit includes a computer flash device controller, a bus switch and a computer flash device grain; wherein the method includes: obtaining a target channel selection chip select signal of the computer flash device controller and an output signal of a general input / output interface of the computer flash device controller; transmitting the chip select signal to a low-speed control area of the bus switch and transmitting the output signal to a high-speed control area of the bus switch; expanding the chip select signal in the low-speed control area by a decoder function of the bus switch to obtain a low-speed control output signal and determining a selection signal for selecting a high-speed signal transmission channel of the computer flash device grain in the high-speed control area by using the output signal; determining a target chip select signal of the computer flash device grain by the low-speed control output signal and determining a target high-speed signal transmission channel by the selection signal to perform data operation on the computer flash device grain through the target high-speed signal transmission channel.

[0083] It can be seen that, by the chip select signal selected by the target channel of the NAND controller, the decoder function of the bus switch is used to decode and expand in the low-speed control area, and then the target chip select signal of the NAND package is determined by the low-speed control output signal. Since the decoder function of the bus switch expands the chip select signal, the expanded output can select more chip select signals of the NAND package, realize the decoding expansion of the chip select signal, and further expand the number of connected NAND packages, improve the capacity of the SSD, and thus eliminate the capacity limitation of the SSD caused by the fact that the chip select signal of the NAND package can only be selected by the fixed number of channels of the NAND controller in the prior art, realize the doubling of the capacity of the SSD under the limitation of the number of channels of the NAND controller, the number of CEs of each channel, and the adaptation of specific NAND controller models, and fill in the large-capacity point of the SSD, and improve the product competitiveness of the SSD. In addition, the selection signal is determined in the high-speed control area of the bus switch by the output signal of the general input / output interface, and then the target high-speed signal transmission channel of the NAND package is determined, so as to perform data operation on the NAND package through the target high-speed signal transmission channel. In this way, the hardware design circuit combines with the software logic control, realizes the point-to-point communication of the high-speed signal through the switch control of the high-speed control area, and overall improves the capacity of the SSD and the high-speed signal interface rate of the NAND package.

[0084] Further, the embodiment of the present application further discloses an electronic device, Figure 6 is an electronic device 20 structure diagram according to an exemplary embodiment, the contents in the figure cannot be considered as any limitation on the use range of the present application.

[0085] Figure 6 A structure diagram of an electronic device 20 provided by the embodiment of the present application. The electronic device 20 can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. Among them, the memory 22 is used to store a computer program, the computer program is loaded and executed by the processor 21, to realize the related steps in the capacity improvement method of the SSD disclosed in any of the preceding embodiments. In addition, the electronic device 20 in the embodiment can be a computer.

[0086] In this embodiment, the power supply 23 is configured to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 is configured to create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which will not be limited here; the input and output interface 25 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which will not be limited here.

[0087] In addition, the memory 22 as a carrier of resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222 and data 223, etc., and the data 223 can include various data. The storage mode can be temporary storage or permanent storage.

[0088] The operating system 221 is configured to manage and control each hardware device on the electronic device 20 and the computer program 222, and can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program capable of completing the capacity improvement method of the SSD executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 can further include a computer program capable of completing other specific work.

[0089] Further, the present application also discloses a computer readable storage medium, which includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk or an optical disk, or any other form of storage medium known in the technical field. The computer program is executed by the processor to implement the foregoing capacity improvement method of the SSD. For the specific steps of the method, please refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0090] In the present specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. For the same or similar parts between each embodiment, please refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part is described in the method part.

[0091] The steps of the capacity improving method or algorithm of the SSD described in connection with the embodiments disclosed herein can be implemented directly with hardware, a software module executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0092] Finally, it should be noted that, in this document, the terms such as first and second are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0093] The above describes in detail the capacity improving method of an SSD, a NAND backend hardware circuit, an apparatus, a device and a medium provided by the present application. The principles and implementation manners of the present application are described by using specific examples in this document. The above description of the embodiments is only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range can be changed. In summary, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A method for increasing the capacity of a solid-state drive, characterized in that, An application to the back-end hardware circuitry of a computer flash memory device, the back-end hardware circuitry of the computer flash memory device including a computer flash memory device controller, a bus switch, and computer flash memory chips, wherein the method includes: Obtain the chip select signal for the target channel selection of the computer flash memory device controller, and obtain the output signal of the general-purpose input / output interface of the computer flash memory device controller; The chip select signal is transmitted to the low-speed control area of ​​the bus switch, and the output signal is transmitted to the high-speed control area of ​​the bus switch. The decoder function of the bus switch expands the chip select signal in the low-speed control area to obtain a low-speed control output signal, and uses the output signal in the high-speed control area to determine a selection signal for selecting the high-speed signal transmission channel of the computer flash memory device chip; the low-speed control output signal is obtained by expanding the chip select signal based on the control logic between the chip select signal and the low-speed control output signal, and the selection signal is determined based on the control logic between the chip select signal and the high-speed signal transmission channel; The target chip select signal of the computer flash memory device is determined by the low-speed control output signal, and the target high-speed signal transmission channel is determined by the selection signal, so as to perform data operations on the computer flash memory device chip through the target high-speed signal transmission channel; The decoder function via the bus switch extends the chip select signal in the low-speed control area to obtain a low-speed control output signal, and uses the output signal in the high-speed control area to determine a selection signal for selecting the high-speed signal transmission channel of the computer flash memory device chip, including: The ENB pin of the bus switch is set to a low level, and then the chip select signal is extended in the low-speed control area to obtain a low-speed control output signal. In the high-speed control area, the output signal is used to determine the selection signal for selecting the high-speed signal transmission channel of the computer flash memory chip. Set the first CFG pin in the bus switch to a low level and connect it to the low-speed control area to obtain the control logic between the chip select signal and the low-speed control output signal. Then, based on the control logic between the chip select signal and the low-speed control output signal, extend the chip select signal to obtain the low-speed control output signal. Set the second CFG pin in the bus switch to a high level and connect it to the high-speed control area to obtain the control logic between the selection signal and the high-speed signal transmission channel. Then, based on the control logic between the selection signal and the high-speed signal transmission channel, determine the selection signal for selecting the high-speed signal transmission channel of the computer flash memory device chip. The decoder function of the bus switch extends the chip select signal in the low-speed control area and sets the ENCB pin of the bus switch to a low level to obtain a low-speed control output signal.

2. The method for increasing the capacity of a solid-state drive according to claim 1, characterized in that, The step of obtaining the chip select signal for the target channel selection of the computer flash memory device controller includes: Obtain the chip select signal from the least significant bit of the channel selected by the computer flash memory device controller until the preset number of high-signal bits of the channel are selected.

3. The method for increasing the capacity of a solid-state drive according to claim 1 or 2, characterized in that, The step of determining the target chip select signal of the computer flash memory device chip through the low-speed control output signal, and determining the target high-speed signal transmission channel through the selection signal, so as to perform data operations on the computer flash memory device chip through the target high-speed signal transmission channel, includes: The target chip select signal of the computer flash memory device is determined by the low-speed control output signal, and the target high-speed signal transmission channel is determined by the selection signal. Based on the target chip select signal and the target high-speed signal transmission channel, the operation target in the computer flash memory device is determined, and then the computer flash memory device controller performs data operations on the operation target through the target high-speed signal transmission channel.

4. A back-end hardware circuit for a computer flash memory device, characterized in that, This includes computer flash memory device controllers, bus switches, and computer flash memory chips; among which, The computer flash memory device controller is used to acquire the chip select signal for the target channel selection and transmit the chip select signal to the low-speed control area of ​​the bus switch, and to acquire the output signal of the general-purpose input / output interface and transmit the output signal to the high-speed control area of ​​the bus switch; The bus switch is connected to the computer flash memory device controller and the computer flash memory chip, respectively. It is used to expand the chip select signal in the low-speed control area via a decoder function to obtain a low-speed control output signal, and to determine a selection signal for selecting the high-speed signal transmission channel of the computer flash memory chip in the high-speed control area using the output signal via the decoder function. The low-speed control output signal is obtained by expanding the chip select signal based on the control logic between the chip select signal and the low-speed control output signal. The selection signal is determined based on the control logic between the chip select signal and the high-speed signal transmission channel. The computer flash memory chip is used to determine a target chip select signal through the low-speed control output signal of the bus switch, and to determine a target high-speed signal transmission channel of the computer flash memory chip through the selection signal of the bus switch, so as to perform data operations on the computer flash memory chip through the target high-speed signal transmission channel; The bus switch is specifically used for: The ENB pin is set to a low level, and then the chip select signal is extended in the low-speed control area to obtain a low-speed control output signal. In the high-speed control area, the output signal is used to determine the selection signal for selecting the high-speed signal transmission channel of the computer flash memory device chip. Set the first CFG pin to a low level and connect it to the low-speed control area to obtain the control logic between the chip select signal and the low-speed control output signal. Then, based on the control logic between the chip select signal and the low-speed control output signal, extend the chip select signal to obtain the low-speed control output signal. Set the second CFG pin to a high level and connect it to the high-speed control area to obtain the control logic between the selection signal and the high-speed signal transmission channel. Then, based on the control logic between the selection signal and the high-speed signal transmission channel, determine the selection signal for selecting the high-speed signal transmission channel of the computer flash memory device chip. The chip select signal is extended in the low-speed control area by the decoder function, and the ENCB pin is set to a low level to obtain the low-speed control output signal.

5. A device for increasing the capacity of a solid-state drive, characterized in that, An apparatus for use in the back-end hardware circuitry of a computer flash memory device, the back-end hardware circuitry of the computer flash memory device including a computer flash memory device controller, a bus switch, and computer flash memory chips, wherein the apparatus includes: The signal acquisition module is used to acquire the chip select signal of the target channel selection of the computer flash memory device controller, and to acquire the output signal of the general input / output interface of the computer flash memory device controller; A signal transmission module is used to transmit the chip select signal to the low-speed control area of ​​the bus switch and to transmit the output signal to the high-speed control area of ​​the bus switch. The decoding extension module is used to extend the chip select signal in the low-speed control area through the decoder function of the bus switch to obtain a low-speed control output signal, and to determine a selection signal for selecting the high-speed signal transmission channel of the computer flash memory device in the high-speed control area using the output signal; the low-speed control output signal is obtained by extending the chip select signal based on the control logic between the chip select signal and the low-speed control output signal, and the selection signal is determined based on the control logic between the chip select signal and the high-speed signal transmission channel; The data communication module is used to determine the target chip select signal of the computer flash memory device chip through the low-speed control output signal, and to determine the target high-speed signal transmission channel through the selection signal, so as to perform data operations on the computer flash memory device chip through the target high-speed signal transmission channel; The decoding extension module is specifically used for: The ENB pin of the bus switch is set to a low level, and then the chip select signal is extended in the low-speed control area to obtain a low-speed control output signal. In the high-speed control area, the output signal is used to determine the selection signal for selecting the high-speed signal transmission channel of the computer flash memory chip. Set the first CFG pin in the bus switch to a low level and connect it to the low-speed control area to obtain the control logic between the chip select signal and the low-speed control output signal. Then, based on the control logic between the chip select signal and the low-speed control output signal, extend the chip select signal to obtain the low-speed control output signal. Set the second CFG pin in the bus switch to a high level and connect it to the high-speed control area to obtain the control logic between the selection signal and the high-speed signal transmission channel. Then, based on the control logic between the selection signal and the high-speed signal transmission channel, determine the selection signal for selecting the high-speed signal transmission channel of the computer flash memory device chip. The decoder function of the bus switch extends the chip select signal in the low-speed control area and sets the ENCB pin of the bus switch to a low level to obtain a low-speed control output signal.

6. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the solid-state drive capacity enhancement method as described in any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that, Used for storing computer programs; wherein the computer programs, when executed by a processor, implement the solid-state drive capacity enhancement method as described in any one of claims 1 to 3.

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