Memory controller, memory data writing and reading method, and storage system

Abstract

The present invention provides a memory controller and a data writing and reading method of a memory and a storage system. The data writing method for the memory controller comprises: encoding the data to be written into m storage particle groups respectively to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group comprises n1…n m storage particles, n1…n m ≥1; m write coded data are sent to m storage particle groups respectively, wherein each of the m write coded data includes a write data symbol and a write check symbol, so that the m storage particle groups respectively decode the write data symbol and the write check symbol to obtain m groups of write error-corrected symbols. The data writing method for a memory controller can check and correct errors that occur when data is transmitted between a memory particle group (e.g., a single memory particle) and a memory controller in application scenarios such as in-memory computing.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory, and more particularly, to a memory controller, a data writing method and a data reading method of the memory, and a storage system. Background Art

[0002] For a long time, modern computer systems have used memory (for example, dynamic random access memory (DRAM)) as main memory. DRAM memory now basically uses double data rate (DDR) technology, generally referred to as DDR memory. DDR memory has evolved to the fifth generation, generally referred to as DDR5 memory. With the increase in the number of DDR memory used in computer systems every year, memory data reliability has become one of the most important factors in the stability of data center systems. In today's high-reliability computer systems in data centers, they are equipped with a wealth of reliability, availability, and serviceability (RAS) features to ensure the correctness of memory data. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a data writing method for a memory controller, comprising: encoding data to be written into m storage particle groups respectively to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; sending the m write coded data to the m storage particle groups respectively, wherein each of the m write coded data includes a write data codeword and a write verification codeword, so that the m storage particle groups respectively decode the write data codeword and the write verification codeword to obtain m groups of write error-corrected codewords.

[0004] At least one embodiment of the present disclosure provides a data reading method for a memory controller, comprising: sending a read data command to m storage particle groups, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m≥1; reading m read coded data from the m storage particle groups, wherein the m read coded data are generated by the m storage particle groups respectively encoding the data stored in the m storage particle groups, and each of the m read coded data includes a read data code element and a read check code element; and decoding the read data code element and the read check code element to obtain m groups of read error-corrected code elements.

[0005] At least one embodiment of the present disclosure provides a data writing method for a memory, comprising: receiving m write coded data respectively by m storage particle groups, wherein the m write coded data are generated by encoding data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; the m storage particle groups respectively decode the write data codewords and the write check codewords to obtain m groups of write error-corrected codewords.

[0006] At least one embodiment of the present disclosure provides a data reading method for a memory, comprising: receiving a read data command from a memory controller by m memory particle groups, wherein the m memory particle groups belong to the same memory column of the memory, m≥2, and each memory particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; the m storage particle groups respectively encode the data stored in the m storage particle groups to obtain m read coded data; and the m read coded data are sent to the memory controller, wherein each of the m read coded data includes a read data code element and a read check code element, so that the memory controller decodes the read data code element and the read check code element to obtain m groups of read error-corrected code elements.

[0007] At least one embodiment of the present disclosure provides a memory controller, comprising: an encoding unit, configured to encode data to be written into m storage particle groups, to obtain m write-in encoding data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m≥1; and a transceiver unit, configured to send the m write coded data to the m storage particle groups respectively, wherein each of the m write coded data includes a write data codeword and a write check codeword, so that the m storage particle groups respectively decode the write data codeword and the write check codeword to obtain m groups of write error-corrected codewords.

[0008] At least one embodiment of the present disclosure provides a memory controller, comprising: a transceiver unit, configured to: send a read data command to m storage particle groups, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; reading m read coded data from the m storage particle groups, wherein the m read coded data are generated by the m storage particle groups respectively encoding the data stored in the m storage particle groups, and each of the m read coded data includes a read data code element and a read check code element; and a decoding unit, configured to decode the data code element and the check code element to obtain m groups of read error-corrected code elements.

[0009] At least one embodiment of the present disclosure provides a memory, comprising: m storage particle groups, configured to: respectively receive m write-in coded data, wherein the m write-in coded data are generated by encoding data to be written into the m storage particle groups, wherein each of the m write-in coded data comprises a write-in data code element and a write-in check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group comprises n 1 …n m Storage particles, n 1 …n m ≥1; and respectively decode the write data codewords and the write check codewords to obtain m groups of write error-corrected codewords.

[0010] At least one embodiment of the present disclosure provides a memory, comprising: m storage particle groups, configured to: receive a read data command from a memory controller, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m≥1; respectively encode the data stored in the m storage particle groups to obtain m read coded data; and send the m read coded data to the memory controller, wherein each of the m read coded data includes a read data code element and a read check code element, so that the memory controller decodes the read data code element and the read check code element to obtain m groups of read error-corrected code elements.

[0011] At least one embodiment of the present disclosure provides a memory controller, comprising: a coding unit, configured to encode data to be written into m storage particle groups, to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; a transceiver unit configured to send the m write coded data to the m storage particle groups respectively, wherein each of the m write coded data includes a write data codeword and a write check codeword, so that the m storage particle groups respectively decode the write data codeword and the write check codeword to obtain m groups of write error-corrected codewords, and the transceiver unit is also configured to: send a read data command to the m storage particle groups; and read m read coded data from the m storage particle groups, wherein the m read coded data are generated by the m storage particle groups respectively encoding the data stored in the m storage particle groups, and each of the m read coded data includes a read data codeword and a read check codeword; and the encoding and decoding unit is also configured to: decode the read data codeword and the read check codeword to obtain m groups of read error-corrected codewords.

[0012] At least one embodiment of the present disclosure provides a memory, comprising: m storage particle groups, configured to: respectively receive m write-in coded data, wherein the m write-in coded data are generated by encoding data to be written into the m storage particle groups, wherein each of the m write-in coded data comprises a write-in data code element and a write-in check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group comprises n 1 …n m Storage particles, n 1 …n m≥1; respectively decode the write data codeword and the write check codeword to obtain m groups of write error-corrected codewords; receive a read data command from a memory controller; and respectively encode the data stored in the m storage particle groups to obtain m read coded data; and send the m read coded data to the memory controller, wherein each of the m read coded data includes a read data codeword and a read check codeword, so that the memory controller decodes the read data codeword and the read check codeword to obtain m groups of read error-corrected codewords.

[0013] At least one embodiment of the present disclosure provides a storage system, including the memory controller as described above; and the memory as described above.

[0014] According to at least one embodiment of the present disclosure, a data writing method and a reading method for a memory controller, a data writing method and a reading method for a memory, a memory controller, a memory, and a storage system can solve errors that occur when in-memory computing data is transmitted on a link between a storage particle and a main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments of the present disclosure are briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and are not intended to limit the present disclosure.

[0016] Figure 1 An exemplary DDR5 ECC data arrangement diagram is shown;

[0017] Figure 2 A flow chart showing a method for writing data to a memory controller according to at least one embodiment of the present disclosure;

[0018] Figure 3 A flow chart showing a data reading method for a memory controller according to at least one embodiment of the present disclosure;

[0019] Figure 4 A flow chart showing a method for writing data into a memory according to at least one embodiment of the present disclosure;

[0020] Figure 5 A flow chart showing a method for reading data from a memory according to at least one embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of a memory controller according to at least one embodiment of the present disclosure is shown;

[0022] Figure 7A schematic diagram of a memory according to at least one embodiment of the present disclosure is shown;

[0023] Figure 8 A schematic diagram of a storage system according to at least one embodiment of the present disclosure is shown;

[0024] Fig. 9 A schematic diagram showing a memory subsystem according to at least one embodiment of the present disclosure is shown;

[0025] Fig.10 A schematic diagram of a DRAM chip supporting ECC according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the present disclosure to the described embodiments. On the contrary, it is intended to cover changes, modifications and equivalents included within the spirit and scope of the present disclosure as defined by the appended claims. It should be noted that the method operations described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of the two.

[0027] In order to enable those skilled in the art to better understand the present disclosure, the present disclosure is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0028] Note that the examples to be introduced below are only specific examples, and are not intended to limit the embodiments of the present disclosure to the specific shapes, hardware, connection relationships, operations, values, conditions, data, sequences, etc. shown and described. Those skilled in the art can apply the concepts of the present disclosure to construct more embodiments not mentioned in the present description by reading the present description.

[0029] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0030] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously as required. At the same time, other operations may also be added to these processes, or one or more operations may be removed from these processes.

[0031] First, the abbreviations and related terms involved in this application are defined and explained.

[0032] DRAM (Dynamic Random Access Memory): Dynamic random access memory.

[0033] DDR (Double Data Rate): Double data rate.

[0034] DDR SDRAM (Double Data Rate SDRAM): Double data rate synchronous dynamic random access memory.

[0035] DDR5 (Double Data Rate 5): Double data rate 5, generally refers to the 5th generation DDR memory.

[0036] Device: For example, a dual in-line memory unit (DIMM) or a memory chip directly soldered on a circuit board. Exemplary memory devices include DRAM devices.

[0037] ECC (Error Correction Code): Error correction code or error correction coding is a coding technology that can implement error checking and correction, which can improve the reliability of the system.

[0038] CE (Correctable Error): Correctable error.

[0039] UE (Uncorrectable Error): Uncorrectable error.

[0040] RAS (Reliability, Availability, Serviceability): reliability, availability, and maintainability.

[0041] PIM (Processing In Memory): In-memory computing or in-memory processing, realizing computing functions in the memory chip.

[0042] NDC (Near Data Computing): Near Data Computing.

[0043] Near Memory Computing: Implementing computing functions near memory chips.

[0044] RS coding (Reed-Solomon coding): is a forward error correction channel coding.

[0045] Hamming code: An error detection and correction code.

[0046] Channel: usually refers to a combination of multiple particles that share the same address bus, which may contain multiple chip select signals.

[0047] Memory Rank: Each dual in-line memory module can have one or more memory ranks. A memory rank is a group of memory particles that provide the data required by the memory controller at the same time. The number of memory particles required for a memory rank is determined by the width of the memory particles. For example, for DDR to DDR4, 16 x4 DRAM particles (64 / 4=16) are required to form a memory rank, and if ECC is supported, 18 particles (16+8 / 4=18); if it is x8 memory particles, 9 memory particles ((64+8) / 8=9) are required to support ECC. The signals of the same memory rank are controlled by the same CS signal. If it is DDR5, a memory rank requires 8 x4 DRAM particles (32 / 4=8), and a memory rank that supports ECC requires 10 x4 memory particles (40 / 4=10), or 4 x8 memory particles, and a memory rank that supports ECC requires 5 x8 memory particles.

[0048] Symbol is also called code element: the smallest unit of ECC error correction, usually with x4 and x8 particles, corresponding to 4 bits and 8 bits of data.

[0049] DIMM (dual In-line memory module): dual in-line memory module.

[0050] DDR PHY (DDR Physical Layer): responsible for sending / receiving DDR electrical signals.

[0051] Link: refers to the physical path between DDR particles and the main control chip, usually including circuit board routing, DDRPHY and other parts.

[0052] Burst Size: refers to the size of the burst data that the memory controller sends to the DRAM particles at one time. It is usually the product of the particle's data width and the burst length, such as 64 bits or 128 bits.

[0053] It is understandable that the terms defined above are only exemplary definitions in specific application scenarios to facilitate a better understanding of the present application. For example, the exemplary definitions for specific memory described above can be extended to other types of memory or other storage.

[0054] In order to ensure the correctness of memory data, common means include memory error correction coding (ECC). ECC error correction coding can provide different error correction capabilities depending on the algorithm. Common coding methods include RS coding and Hamming coding. However, these common coding methods are usually based on all the data in the DDR channel.

[0055] In recent years, in order to solve the problems of memory access bandwidth and memory access power consumption in mainstream computing architectures, processing in memory has received widespread attention and has become one of the main technical routes for intelligent computing. One of the main technical routes for processing in memory is to integrate computing units into storage units, also known as near data processing. An important implementation of near data computing is to embed computing units based on DRAM. The new architecture of processing in memory has put forward new requirements for the protection of data reliability.

[0056] Exemplary ECC schemes include 1) a DDR channel-based ECC scheme and 2) an on-chip ECC scheme of a DRAM particle.

[0057] Regarding 1) the ECC solution based on the DDR channel, it is mainly implemented through an ECC algorithm based on the DDR channel. Figure 1 An exemplary DDR5 ECC data arrangement diagram is shown. Figure 1 As shown, the ECC-encoded data (also called data symbols) and check symbols (also called check symbols) of DDR5 (embodied as DDR5 memory column 200) are dispersedly stored on 5 x8 memory particles 202 to 210. These data symbols and check symbols can be collectively referred to as encoded data in this article. The 8-bit check word is stored in the x8 memory particle 202, and the 8-bit data is stored in the x8 memory particles 204 to 210. When the memory controller writes data to the DRAM particle, it will write the check word to the corresponding DRAM particle at the same time. See Figure 1 , the 15 pieces of coded data (the 1st piece of coded data is equal to the 15th piece of coded data) include check words and data. Each read operation will read back all the memory particle data, combine them into the data and check words required for ECC decoding, and then start data error detection and correction.

[0058] In the above case, in application scenarios such as in-memory computing and near-memory computing, since the data calculation is completed inside or near the DRAM particles, and since the new data is generated in the PIM unit, the check word originally written from the memory controller has become invalid. Therefore, the traditional error detection and correction method based on the DDR channel memory controller side is no longer applicable.

[0059] Regarding 2) the on-chip ECC solution of DRAM particles, it performs ECC encoding and verification work while accessing data inside the DRAM particles. On-chip ECC can solve the problem of data error detection and correction inside the memory particles.

[0060] However, the data protection of the above-mentioned on-chip ECC scheme is limited to the DRAM particles. It cannot detect and correct errors that occur in the link between the memory particles and the main control chip. As the frequency of the memory bus continues to increase, the signal integrity problem on the link becomes increasingly worse, and the possibility of errors in data transmission on the link becomes greater and greater.

[0061] With the development of new computing architectures, new applications such as in-memory computing have put forward new requirements for data error correction functions. The above-mentioned 1) ECC solutions based on DDR channels and 2) on-chip ECC solutions of DRAM particles can no longer meet the requirements. At least some embodiments of the present disclosure propose a data writing method and a reading method for a memory controller, a data writing method and a reading method for a memory, a memory controller, a memory, and a storage system to solve errors generated when in-memory computing data is transmitted on a link between a storage particle and a main control chip.

[0062] With reference to the accompanying drawings, the following describes in detail a data writing method and a reading method for a memory controller, a data writing method and a reading method for a memory, a memory controller, a memory, and a storage system according to an embodiment of the present disclosure.

[0063] First, a data writing method for a memory controller according to an embodiment of the present disclosure is introduced below. The data writing method for a memory controller can be applied to a memory controller, a storage system, other electronic devices, and other suitable software or hardware, or a combination of hardware and software as further described below.

[0064] Figure 2 A flow chart of a method 200 for writing data to a memory controller according to at least one embodiment of the present disclosure is shown. The method 200 for writing data to a memory controller may include steps S210 to S220.

[0065] In step S210, the data to be written into m storage particle groups are encoded to obtain m write-in encoded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m storage particles (ie, the first storage particle group includes n 1 storage particles, the second storage particle group includes n 2 storage particles, and so on, the mth storage particle group includes nm storage particles), n 1 …n m ≥1.

[0066] It is understandable that, in this article, a storage column is a group of multiple storage particles, which provide data required by the memory controller at the same time, so the memory controller can access (write / read) the storage particle groups in the storage column at the same time. In this embodiment, the memory controller can write to m storage particle groups at the same time.

[0067] In some embodiments, m groups of memory granules constitute the same memory column of the memory.

[0068] In step S220, the m write-in coded data are sent to the m storage particle groups respectively.

[0069] In this embodiment, each of the m write coded data includes a write data codeword and a write verification codeword, so that the m storage particle groups respectively decode the write data codeword and the write verification codeword to obtain m groups of write error-corrected codewords.

[0070] Additionally, m groups of written error-corrected symbols can be stored in m storage granule groups respectively, so that each storage granule group can store a corresponding group of written error-corrected symbols.

[0071] In this way, the data writing method for a memory controller according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0072] For example, according to at least one embodiment of the present disclosure, the data writing method for the memory controller can generate check words for the data to be written into the corresponding memory particle group in the memory column (rather than all the memory particles in the memory column) as a unit, so that the corresponding memory particle group can be prompted to decode the written data based on its own check words to achieve error correction. For example, compared with the above-mentioned 1) ECC scheme based on the DDR channel, the check words required for decoding the corresponding memory particle group in the data writing method for the memory controller according to at least one embodiment of the present disclosure are not affected by the data to be written into other memory particle groups, ensuring that the data check and the generation of the check words are completed on the local memory particles, meeting the need for data to be modified in the memory particles in application scenarios such as near-memory computing. For another example, compared with the above-mentioned 2) on-chip ECC scheme of DRAM particles, according to at least one embodiment of the present disclosure, the data writing method for the memory controller can promote the decoding of the check words generated by the memory particle group based on the data to be written into the memory particle group, and achieve error correction on the link between the memory particle group and the memory controller, thereby increasing the error range covered by the error correction, thereby increasing the error correction capability.

[0073] Other aspects of the data writing method for a memory controller according to at least one embodiment of the present disclosure are described in detail below.

[0074] In some embodiments, according to at least one embodiment of the present disclosure, a data writing method for a memory controller is used. 1 …n m =1. Thus, the data writing method for a memory controller according to at least one embodiment of the present disclosure can generate a check word for each storage particle in a storage column of the memory, thereby causing the corresponding single storage particles to be decoded based on their respective check words to achieve error correction. For example, in some examples, a storage column may include 2 (m=2) storage particle groups, each storage particle group may include 1 (n 1 =n 2 =1) Storage particles.

[0075] In some embodiments, according to at least one embodiment of the present disclosure, a data writing method for a memory controller is used. 1 …n m >1. Thus, the data writing method for a memory controller according to at least one embodiment of the present disclosure can generate a check word for each of the multiple storage particles in the storage column of the memory, thereby enabling the corresponding multiple storage particles to be individually decoded based on their respective check words to achieve error correction. For example, in some examples, the storage column may include 2 (m=2) storage particle groups, each storage particle group may include 2 (n1 =n 2 =2) Storage particles.

[0076] In some embodiments, according to at least one embodiment of the present disclosure, a data writing method for a memory controller is used. 1 …n m ≥1 and n 1 …n m Each is not equal or not completely equal. In this way, the data writing method for a memory controller according to at least one embodiment of the present disclosure can flexibly set the number of storage particles included in the storage particle group, which is particularly advantageous in application scenarios such as in-memory computing, where some storage particle groups require higher RAS requirements (and thus can each include only a single storage particle) while other storage particle groups require lower RAS requirements (and thus can each include multiple storage particles). For example, in some examples, a storage column may include 2 (m=2) storage particle groups, and a storage particle group may include 1 (n 1 =1) storage particle, and another storage particle group may include 2 (n 2 =2) Storage particles.

[0077] In some embodiments, according to at least one embodiment of the present disclosure, the data writing method for the memory controller may further include: mapping m write coded data to m storage particle groups respectively; and performing digital-to-analog conversion on the m write coded data. For example, the memory controller may include a remapping unit, which may map the m write coded data to the m storage particle groups, thereby facilitating sending the write coded data to the corresponding storage particle groups. For example, the memory controller may also include a memory physical layer (e.g., DDR PHY) unit, and the memory physical layer unit may perform digital-to-analog conversion on the write coded data to send the write coded data. Therefore, the remapping unit and the memory physical layer unit may send the write coded data to the corresponding storage particles. However, the embodiment is not limited thereto, and the write coded data may also be sent to the corresponding storage particles in other ways.

[0078] In some embodiments, according to at least one embodiment of the present disclosure, the data writing method for a memory controller, m groups of write error-corrected code elements may include m write error-corrected data code elements and m write error-corrected check code elements, wherein the m write error-corrected data code elements may be stored in m storage particle groups respectively, and the m write error-corrected check code elements may be discarded. In this way, according to at least one embodiment of the present disclosure, the data writing method for a memory controller may store the write error-corrected data code elements in the corresponding storage particle groups without storing the error-corrected check code elements, thereby improving the utilization rate of the memory.

[0079] In some embodiments, according to the data writing method for a memory controller according to at least one embodiment of the present disclosure, m written error-corrected data symbols may be stored in storage array units of m storage particle groups, respectively.

[0080] In some embodiments, according to the data writing method for a memory controller according to at least one embodiment of the present disclosure, the encoding and decoding may use the same algorithm, so that the structure of the encoding and decoding unit of the memory controller and the memory may be simplified.

[0081] In some embodiments, according to the data writing method for a memory controller according to at least one embodiment of the present disclosure, the algorithm may include a RS encoding algorithm or a Hamming code encoding algorithm.

[0082] The following introduces a data reading method for a memory controller according to an embodiment of the present disclosure. The data reading method can be applied to a memory controller, a storage system, other electronic devices, and other suitable software or hardware, or a combination of hardware and software as further described below.

[0083] Figure 3 A flow chart of a data reading method 300 for a memory controller according to at least one embodiment of the present disclosure is shown. The data writing method 300 for a memory controller may include steps S310 to S330.

[0084] In step S310, a read data command is sent to m storage particle groups, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1.

[0085] In this embodiment, the memory controller may read the m storage granule groups together at the same time.

[0086] In step S320, m read coded data are read from m storage particle groups, wherein the m read coded data are generated by respectively encoding the data stored in the m storage particle groups by the m storage particle groups, and each of the m read coded data includes a read data code element and a read check code element.

[0087] In step S330, the read data symbols and the read check symbols are decoded to obtain m groups of read error-corrected symbols.

[0088] Additionally, the m groups of read error-corrected symbols may be further processed by, for example, a memory controller.

[0089] In this way, the data reading method for a memory controller according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0090] For example, according to at least one embodiment of the present disclosure, the data reading method for the memory controller can obtain the check words generated for the data of the storage particle group to be read in units of the storage particle group in the storage column of the memory (rather than all the storage particles in the storage column), so that the memory controller can decode the read data in units of the storage particle group to achieve error correction. For example, compared with the above-mentioned 1) ECC scheme based on the DDR channel, the data reading method for the memory controller according to at least one embodiment of the present disclosure can support the original data to be rewritten on the storage particle side, and the check word is generated in real time based on the modified original data. And this feature is exactly the necessary feature for in-memory calculation. The ECC check word in the ECC scheme based on the DDR channel is generated on the memory controller side and written into a special DRAM particle for storage. Once the original data is rewritten on the particle side, the corresponding ECC check word will fail and lose the protection function for the original data. At least one implementation of the present disclosure can support the real-time generation of ECC check words for the rewritten original data on the particle side, and send it to the memory controller to complete the data error protection function. For another example, compared with the on-chip ECC scheme of the above-mentioned 2) DRAM particles, the data writing method for a memory controller according to at least one embodiment of the present disclosure can support the memory controller to decode the check words generated based on the data of the storage particle group to be read, thereby realizing error correction of errors on the link between the storage particles and the storage controller, thereby increasing the error range covered by the error correction and thus improving the error correction capability.

[0091] Other aspects of the data reading method for a memory controller according to at least one embodiment of the present disclosure are described in detail below.

[0092] In some embodiments, according to at least one embodiment of the present disclosure, the data reading method for a memory controller may further include: mapping m read coded data to the memory controller respectively; and performing digital-to-analog conversion on the m read coded data. For example, the memory controller may include a remapping unit, which may map the m read coded data to the memory controller respectively, thereby facilitating reading the read coded data from the corresponding storage particle group. For example, the storage controller may also include a memory physical layer (e.g., DDR PHY) unit, and the memory physical layer unit may perform digital-to-analog conversion on the read coded data to receive the read coded data. Therefore, the remapping unit and the memory physical layer unit may read the read coded data from the corresponding storage particle group. However, the embodiment is not limited thereto, and the read coded data may also be read from the corresponding storage particle group in other ways.

[0093] In some embodiments, according to the data reading method for a memory controller according to at least one embodiment of the present disclosure, encoding and decoding may use the same algorithm.

[0094] In some embodiments, according to the data reading method for a memory controller according to at least one embodiment of the present disclosure, the algorithm may include a RS encoding algorithm or a Hamming code encoding algorithm.

[0095] The above is only combined with Figure 3 Part of a data reading method 300 for a memory controller according to at least one embodiment of the present disclosure is described, and the remaining part of the data reading method 300 for a memory controller may be combined with the present disclosure. Figure 2 The various aspects of the data writing method 200 for a memory controller described herein are referred to and combined according to the present disclosure. Figure 2 The effects of various aspects of the data writing method 200 described for a memory controller can also be mapped to the combination of the present disclosure. Figure 3 The data reading method 300 for the memory controller is described and will not be described in detail here.

[0096] Combination of the above Figure 2 The data writing method 200 described for the memory controller is combined with the above Figure 3 The described data reading method 300 for a memory controller can be combined into, for example, a data access method for a memory controller, thereby including both the data writing method 200 for a memory controller and the data reading method 300 for a memory controller and having corresponding technical effects, which will not be repeated here.

[0097] It should be noted that the terms prefixed with "write" and "read" in this article are only for distinguishing descriptions of objects in the writing process and the reading process to avoid confusion. For example, "write coded data" corresponds to the coded data in the data writing process, and "read coded data" corresponds to the coded data in the data reading process. For another example, "write data codewords" and "write check codewords" correspond to the data codewords and check codewords in the data writing process, respectively, and "read data codewords" and "read check codewords" correspond to the data codewords and check codewords in the data reading process, respectively. For another example, "write error-corrected codewords" corresponds to the error-corrected codewords in the data writing process, and "read error-corrected codewords" corresponds to the error-corrected codewords in the data reading process.

[0098] The following introduces a method for writing data to a memory according to an embodiment of the present disclosure. The method for writing data to a memory can be applied to a memory, a storage system, other electronic devices, and other suitable software or hardware, or a combination of hardware and software as further described below.

[0099] Figure 4 A flow chart of a method 400 for writing data into a memory according to at least one embodiment of the present disclosure is shown. The method 400 for writing data into a memory may include steps S410 to S420.

[0100] In step S410, m storage particle groups receive m write coded data respectively, wherein the m write coded data are generated by encoding the data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1.

[0101] In step S420, m storage particle groups decode the write data symbols and the write check symbols respectively to obtain m groups of write error-corrected symbols.

[0102] In this way, the data writing method for a memory according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0103] Other aspects of the method for writing data to a memory according to at least one embodiment of the present disclosure are described in detail below.

[0104] In some embodiments, according to at least one embodiment of the present disclosure, a data writing method for a memory, m groups of write error-corrected code elements may include m write error-corrected data code elements and m write error-corrected verification code elements, wherein the m write error-corrected data code elements may be stored in m storage particle groups respectively, and the m write error-corrected verification code elements may be discarded.

[0105] Combination Figure 4 The described method for writing data to a memory may be combined with Figure 2 The data writing method for the memory controller described above corresponds to that described above. Figure 4 Additional methods for the data writing method described in conjunction with Figure 2 The data writing method for the memory controller and its additional method are described and have corresponding technical effects, which will not be described in detail here.

[0106] Figure 5 A flow chart of a method 500 for reading data from a memory according to at least one embodiment of the present disclosure is shown. The method 500 for reading data from a memory may include steps S510 to S530.

[0107] In step S510, m storage particle groups receive a read data command from a memory controller, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1.

[0108] In step S520, the m storage particle groups respectively encode the data stored in the m storage particle groups to obtain m read coded data.

[0109] In step S530, m read coded data are sent to the memory controller.

[0110] In the above embodiment, each of the m read coded data includes a read data symbol and a read check symbol, so that the memory controller decodes the read data symbol and the read check symbol to obtain m groups of read error-corrected symbols.

[0111] In this way, the data reading method for a memory according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0112] Combination Figure 5 The data reading method for a memory described can be combined with Figure 3 The data reading method for the memory controller described above corresponds to that described above. Figure 5 Additional methods for the data reading method described for the memory can be found in conjunction with Figure 3 The data reading method for the memory controller and its additional method are described and have corresponding technical effects, which will not be repeated here.

[0113] Combination of the above Figure 4 The data writing method 400 described above for a memory is combined with Figure 5 The described data reading method 500 for a memory can be combined into, for example, a data access method for a memory, thereby including both the data writing method 400 for a memory and the data reading method 500 for a memory and having corresponding technical effects, which will not be repeated here.

[0114] Corresponding to the data writing method for a memory controller or the data reading method for a memory controller according to at least one embodiment of the present disclosure, the present disclosure also provides a memory controller.

[0115] Figure 6 FIG. 4 is a schematic diagram of a memory controller 600 according to at least one embodiment of the present disclosure. Figure 6 As shown, the memory controller 600 may include a coding unit 610 and a transceiver unit 620 .

[0116] For example, corresponding to the data writing method for a memory controller according to at least one embodiment of the present disclosure, the encoding and decoding unit 610 and the transceiver unit 620 included in the memory controller 600 may be configured as follows.

[0117] The encoding and decoding unit 610 may be configured to encode the data to be written into the m storage particle groups to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1.

[0118] The transceiver unit 620 may be configured to send the m write-in coded data to the m storage particle groups respectively.

[0119] In this embodiment, each of the m write coded data includes a write data codeword and a write verification codeword, so that the m storage particle groups respectively decode the write data codeword and the write verification codeword to obtain m groups of write error-corrected codewords.

[0120] In this way, the memory controller according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0121] For example, corresponding to the data reading method for a memory controller according to at least one embodiment of the present disclosure, the encoding and decoding unit 610 and the transceiver unit 620 included in the memory controller 600 may be configured as follows.

[0122] The transceiver unit 620 may be configured to send a read data command to m storage particle groups, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; and reading m read coded data from m storage particle groups, wherein the m read coded data are generated by respectively encoding the data stored in the m storage particle groups by the m storage particle groups, and each of the m read coded data includes a read data code element and a read check code element.

[0123] The decoding unit 610 may be configured to decode the data symbols and the check symbols to obtain m groups of read error-corrected symbols.

[0124] In this way, the memory controller according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0125] Corresponding to the data writing method for a memory controller and the data reading method for a memory controller according to at least one embodiment of the present disclosure, the encoding and decoding unit 610 and the transceiver unit 620 included in the memory controller 600 may be configured as follows.

[0126] The encoding and decoding unit 610 may be configured to encode the data to be written into m storage particle groups respectively, to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1.

[0127] The transceiver unit 620 can be configured to send the m write coded data to the m storage particle groups respectively, wherein each of the m write coded data includes a write data codeword and a write verification codeword, so that the m storage particle groups respectively decode the write data codeword and the write verification codeword to obtain m groups of write error-corrected codewords.

[0128] The transceiver unit 620 can also be configured to: send a read data command to the m storage particle groups; and read m read coded data from the m storage particle groups, wherein the m read coded data are generated by the m storage particle groups respectively encoding the data stored in the m storage particle groups, and each of the m read coded data includes a read data code element and a read check code element.

[0129] The encoding and decoding unit 610 may also be configured to decode the read data symbols and the read check symbols to obtain m groups of read error-corrected symbols.

[0130] In this way, the memory controller according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0131] Corresponding to the data writing method for a memory or the data reading method for a memory according to at least one embodiment of the present disclosure, the present disclosure also provides a memory.

[0132] Figure 7 FIG. 1 shows a schematic diagram of a memory 700 according to at least one embodiment of the present disclosure. Figure 7 As shown, the memory 700 includes m memory particle groups 710 .

[0133] Corresponding to the data writing method for a memory according to at least one embodiment of the present disclosure, the m memory particle groups 710 included in the memory 700 may be configured as follows.

[0134] The m storage particle groups can be configured to: respectively receive m write coded data, wherein the m write coded data are generated by encoding the data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m≥1; and respectively decode the write data codewords and the write check codewords to obtain m groups of write error-corrected codewords.

[0135] In this way, the memory according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0136] Corresponding to the data reading method for a memory according to at least one embodiment of the present disclosure, the m memory cell groups 710 included in the memory 700 may be configured as follows.

[0137] The m storage particle groups may be configured to: receive a read data command from a memory controller, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m ≥1; respectively encode the data stored in the m storage particle groups to obtain m read coded data; and send the m read coded data to the memory controller, wherein each of the m read coded data includes a read data code element and a read check code element, so that the memory controller decodes the read data code element and the read check code element to obtain m groups of read error-corrected code elements.

[0138] In this way, the memory according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0139] Corresponding to the data writing method for a memory and the data reading method for a memory according to at least one embodiment of the present disclosure, the m memory particle groups 710 included in the memory 700 may be configured as follows.

[0140] The m storage particle groups can be configured to: respectively receive m write coded data, wherein the m write coded data are generated by encoding the data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n 1 …n m Storage particles, n 1 …n m≥1; respectively decode the write data codewords and the write check codewords to obtain m groups of write error-corrected codewords; receive a read data command from a memory controller; and respectively encode the data stored in the m storage particle groups to obtain m read coded data; and send the m read coded data to the memory controller, wherein each of the m read coded data includes a read data codeword and a read check codeword, so that the memory controller decodes the read data codeword and the read check codeword to obtain m groups of read error-corrected codewords.

[0141] In this way, the memory according to at least one embodiment of the present disclosure can check and correct errors that occur when data is transmitted between a memory particle group (such as a single memory particle) and a memory controller in application scenarios such as in-memory computing.

[0142] Figure 8 FIG. 8 is a schematic diagram of a storage system 800 according to at least one embodiment of the present disclosure. Figure 8 As shown, the storage system 800 may include the Figure 6 The memory controller 600 described herein and the memory controller 600 of FIG. Figure 7 Memory 700 described herein. Thus, see Figure 6 The memory controller 600 described herein and the memory controller 600 of FIG. Figure 7 The memory 700 described may be mapped to Figure 8 The storage system 800 described above will not be described in detail here.

[0143] Below through Figures 9 and 10 To describe the method that can be used according to the present disclosure Figures 2 to 8 Example application scenarios of one or more aspects of the embodiments of the present invention. It is understood that Figures 9 and 10 The application scenarios shown are only exemplary and do not exhaustively list the application scenarios of the present disclosure. Figures 2 to 8 Various aspects of the embodiments, and in combination Figures 9 and 10 Aspects and combinations of descriptions Figures 2 to 8 Various aspects of the described embodiments may be referenced to each other without departing from the scope of the present disclosure.

[0144] In this example application scenario, the memory controller is shown as a memory controller, the memory is shown as a DRAM memory, and the storage rank is shown as a DDR memory rank (DDR Rank), so this example application scenario can be embodied as a memory subsystem. However, the embodiment is not limited thereto.

[0145] Fig. 9 FIG. 9 is a schematic diagram of a memory subsystem 900 according to at least one embodiment of the present disclosure. The memory subsystem 900 here may be an exemplary example of the above storage system.

[0146] See also Fig. 9 , the memory subsystem 900 may include a memory controller 910 and a DDR memory rank 920. The memory controller 910 may be an exemplary instance of the memory controller described above, and the DDR memory rank 920 may be an exemplary instance of the memory rank described above. The memory controller 910 is also commonly referred to as a master chip. An exemplary memory may include one or more DDR memory ranks 920.

[0147] The memory controller 910 may include an ECC encoding and decoding unit 902, a data remapping unit 904, and a DDR PHY unit 906. The DDR memory rank 920 may include a plurality of DRAM particles, such as a DRAM particle 922, a DRAM particle 924, and a DRAM particle 926. The DDR memory rank 920 may be a dual in-line memory unit (DIMM), a plurality of DRAM particles directly soldered on a circuit board (also referred to as a DRAM particle chip), or other forms.

[0148] The structure of an exemplary DRAM chip is as follows Fig.10 shown. Fig.10 FIG. 1 is a schematic diagram of a DRAM chip 1000 supporting ECC according to at least one embodiment of the present disclosure. Fig.10 The DRAM particle 1000 may include a storage array unit 1002, an ECC encoding and decoding unit 1004, and optionally a processing in memory unit (PIM) 1406.

[0149] Continue to see Fig. 9 , the memory controller 910 can access the DDR memory ranks 920 via the DDR channels. Fig. 9 One DDR channel is taken as an example, but the embodiment is not limited thereto, and the memory subsystem 900 may also include multiple DDR channels.

[0150] The following describes the data writing workflow and data reading workflow between the memory controller 910 and the DDR memory rank 920 in the memory subsystem 900 .

[0151] An exemplary workflow for writing data is as follows.

[0152] 1. When the memory controller 910 can send write data to the DRAM particles (e.g., DRAM particles 922) in the DDR memory column 920, the ECC encoding and decoding unit 902 in the memory controller 910 can complete encoding according to the burst data size of the current DRAM particles (e.g., DRAM particles 922) and generate encoded data (e.g., corresponding to the write encoded data above). For example, for x8 DRAM particles, the burst length is 16, the burst data size is 128 bits, and the ECC encoding unit 902 can generate a 16-bit check word accordingly.

[0153] 2. The corresponding encoded data (including ECC-encoded data and check words) can be sent to a single corresponding DRAM particle (eg, DRAM particle 922) through the data remapping unit 904 and the DDR PHY unit 906.

[0154] 3. After receiving the encoded data, the DRAM particles (such as DRAM particles 922) can be decoded by the local ECC codec unit 1004 to complete data error detection and correction. In addition, the DRAM particles (such as DRAM particles 922) can store the corrected data, for example, in the storage array unit 1002 of the DRAM particles. In addition, the corrected check word can be discarded instead of being stored. Once an ECC check error occurs, the DRAM particles (such as DRAM particles 922) can transmit the error information back to the memory controller 910 through a specific signal line such as Alert_N, requesting retransmission reporting and other error handling processes.

[0155] An exemplary workflow for reading data is as follows.

[0156] 1. The memory controller 910 may send a read data command to a DRAM chip (eg, DRAM chip 922 ).

[0157] 2. DRAM particles (e.g., DRAM particles 922) can take the data generated by the in-memory processing unit (PIM) 1406 from the storage array unit 1002, call the local ECC codec unit 1004 to complete the ECC encoding, and generate encoded data (e.g., corresponding to the reading of encoded data above). The encoded data may include the original data and the ECC check word. Then, the ECC check word may be attached to the original data and sent together to the memory controller 910.

[0158] 3. After passing through the DDR PHY unit 906 and the remapping unit 904, the encoded data is sent to the ECC encoding and decoding unit 902 of the memory controller 910 for decoding to achieve data error detection and correction.

[0159] In this example application scenario, the data of each DRAM particle can be independently error-checked and error-corrected, without relying on the data stored on other DRAM particles in the DDR storage column.

[0160] In additional aspects of this example application scenario, the ECC codec unit 902 in the memory controller 910 and the ECC codec unit 1004 in the DRAM particles can use the same algorithm to implement an encoding-decoding pair, that is, encoding on one side and decoding on the other side.

[0161] In this example application scenario, errors that occur when data is transmitted between a single memory particle and a memory controller can be checked and corrected in application scenarios such as in-memory computing. For example, error detection and error correction can be completed in a single memory particle. For another example, the generation of the check word does not require reading data from other memory particles. For another example, the use of ECC check particles is saved, for example, a single memory particle can complete the writing and reading of all data required for ECC error correction.

[0162] The above example application scenarios are only used to implement the Figures 2 to 8 One or more aspects of the embodiments of the present disclosure may be referred to in detail for other aspects of the above example application scenarios. Figures 2 to 8 Other aspects of the embodiments and additional aspects thereof.

[0163] The above example application scenarios are only exemplary, and other variations may exist. For example, the above example application scenarios are not limited to the error correction protection of DRAM particles, and other memories (such as off-chip SRAM modules, Flash modules, and other storage media) can be applied. For another example, the above example application scenarios are not limited to memories that support the PIM function, and any application that supports changing data in the memory can use this method to correct protection data errors during transmission.

[0164] In the above detailed description, for the purpose of explanation rather than limitation, specific details are set forth in order to provide a thorough understanding of the various aspects and embodiments described in the present disclosure. In some cases, a detailed description of well-known devices, components, circuits and methods is omitted to avoid blurring the description of the embodiments disclosed herein with unnecessary details. All statements of the principles, aspects and embodiments disclosed herein, as well as specific examples thereof, are listed herein, and are intended to cover both their structural equivalents and functional equivalents. In addition, such equivalents are intended to include currently known equivalents and equivalents developed in the future, that is, any element developed to perform the same function, regardless of the structure. Therefore, for example, it is understood that the block diagram herein may represent a conceptual diagram of an illustrative circuit system or other functional unit embodying the principles of the described embodiments. Such functions and the functional blocks shown will be understood to be hardware-implemented and / or computer-implemented.

[0165] The various embodiments of the present disclosure are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0166] It should be noted that, in this article, relational terms such as first, second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "include", "comprises", or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements includes not only those elements, but also further includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. In the absence of further restrictions, the elements defined by the statement "includes..." do not exclude the presence of other identical elements in the process, method, article, or device including the elements.

[0167] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure; the scope of the present disclosure is determined by the claims.

Claims

1. A data writing method for a memory controller, comprising: Encode the data to be written into m storage particle groups respectively to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; The m write-in coded data are sent to the m storage particle groups respectively, Among them, each of the m write-coded data includes a write data codeword and a write verification codeword, so that each storage particle group in the m storage particle groups decodes the corresponding write data codeword and the corresponding write verification codeword internally to obtain m groups of write error-corrected codewords.

2. The data writing method according to claim 1, further comprising: Mapping the m write-in coded data to the m storage particle groups respectively; as well as The m written coded data are digital-to-analog converted.

3. The data writing method according to claim 1, wherein: The m groups of write error-corrected code elements include m write error-corrected data code elements and m write error-corrected verification code elements, wherein the m write error-corrected data code elements are stored in the m storage particle groups respectively, and the m write error-corrected verification code elements are discarded.

4. The data writing method according to claim 1, wherein: The encoding and the decoding adopt the same algorithm.

5. The data writing method according to claim 4, wherein: The algorithm includes a RS encoding algorithm or a Hamming code encoding algorithm.

6. A data reading method for a memory controller, comprising: Send a read data command to m storage particle groups, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; Reading m read coded data from the m storage particle groups, wherein the m read coded data are generated by encoding data stored in the corresponding storage particle group in each of the m storage particle groups, and each of the m read coded data includes a read data code element and a read check code element; and The read data codewords and the read check codewords are decoded to obtain m groups of read error-corrected codewords.

7. The data reading method according to claim 6, further comprising: Performing digital-to-analog conversion on the m read coded data; as well as The m read coded data are mapped to the memory controller respectively.

8. The data reading method according to claim 6, wherein: The encoding and the decoding adopt the same algorithm.

9. The data reading method according to claim 8, wherein: The algorithm includes a RS encoding algorithm or a Hamming code encoding algorithm.

10. A method for writing data into a memory, comprising: m storage particle groups receive m write coded data respectively, wherein the m write coded data are generated by encoding the data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; Each storage particle group in the m storage particle groups decodes the corresponding write data code element and the corresponding write verification code element therein to obtain m groups of write error-corrected code elements.

11. The data writing method according to claim 10, wherein: The m groups of write error-corrected code elements include m write error-corrected data code elements and m write error-corrected verification code elements, wherein the m write error-corrected data code elements are stored in the m storage particle groups respectively, and the m write error-corrected verification code elements are discarded.

12. A method for reading data from a memory, comprising: m storage particle groups receive a read data command from a memory controller, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; Each storage particle group in the m storage particle groups encodes the data stored in the corresponding storage particle group therein to obtain m read coded data; and sending the m read coded data to the memory controller, Each of the m read coded data includes a read data symbol and a read check symbol, so that the memory controller decodes the read data symbol and the read check symbol to obtain m groups of read error-corrected symbols.

13. A memory controller comprising: The encoding unit is configured to encode the data to be written into the m storage particle groups respectively to obtain m write-in encoding data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; and a transceiver unit, configured to send the m write-in coded data to the m storage particle groups respectively, Among them, each of the m write-coded data includes a write data codeword and a write verification codeword, so that each storage particle group in the m storage particle groups decodes the corresponding write data codeword and the corresponding write verification codeword internally to obtain m groups of write error-corrected codewords.

14. A memory controller comprising: The transceiver unit is configured as follows: Send a read data command to m storage particle groups, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; m read coded data are read from the m storage particle groups, wherein the m read coded data are generated by each storage particle group in the m storage particle groups encoding the data stored in the corresponding storage particle group internally, and each of the m read coded data includes a read data code element and a read check code element; and a decoding unit is configured to decode the data code element and the check code element to obtain m groups of read error-corrected code elements.

15. A memory comprising: m storage granule groups are configured as follows: m write coded data are received respectively, wherein the m write coded data are generated by encoding the data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; and Each storage particle group in the m storage particle groups decodes the corresponding write data code element and the corresponding write verification code element therein to obtain m groups of write error-corrected code elements.

16. A memory comprising: m storage granule groups are configured as follows: A read data command is received from a memory controller, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; Each storage particle group in the m storage particle groups encodes the data stored in the corresponding storage particle group therein to obtain m read coded data; and sending the m read coded data to the memory controller, Each of the m read coded data includes a read data symbol and a read check symbol, so that the memory controller decodes the read data symbol and the read check symbol to obtain m groups of read error-corrected symbols.

17. A memory controller comprising: The encoding and decoding unit is configured to encode the data to be written into the m storage particle groups respectively to obtain m write-in coded data, wherein the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; a transceiver unit, configured to send the m write-in coded data to the m storage particle groups respectively, Each of the m write coded data includes a write data symbol and a write check symbol, so that each of the m storage particle groups decodes the corresponding write data symbol and the corresponding write check symbol inside the m storage particle groups to obtain m groups of write error-corrected symbols. The transceiver unit is further configured as: Sending a read data command to the m storage particle groups; and m read coded data are read from the m storage particle groups, wherein the m read coded data are generated by each storage particle group in the m storage particle groups encoding the data stored in the corresponding storage particle group internally, and each of the m read coded data includes a read data code element and a read check code element; and the encoding and decoding unit is further configured to: decode the read data code element and the read check code element to obtain m groups of read error-corrected code elements.

18. A memory comprising: m storage granule groups are configured as follows: m write coded data are received respectively, wherein the m write coded data are generated by encoding the data to be written into the m storage particle groups respectively, wherein each of the m write coded data includes a write data code element and a write check code element, the m storage particle groups belong to the same storage column of the memory, m≥2, and each storage particle group includes n1…n m storage particles, n1…n m ≥1; Each storage particle group in the m storage particle groups decodes the corresponding write data code element and the corresponding write check code element therein to obtain m groups of write error-corrected code elements; receiving a read data command from a memory controller; and Each storage particle group in the m storage particle groups encodes the data stored in the corresponding storage particle group therein to obtain m read coded data; and sending the m read coded data to the memory controller, Each of the m read coded data includes a read data symbol and a read check symbol, so that the memory controller decodes the read data symbol and the read check symbol to obtain m groups of read error-corrected symbols.

19. A storage system comprising: The memory controller according to claim 17; as well as A memory according to claim 18.

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