Wiring method, device, equipment, medium and product of storage device

Abstract

Embodiments of the present application disclose a wiring method and device of a storage device, equipment, medium and product. By comprehensively considering the time delay of a reference signal line at a processor, a receiving end, each wiring layer and a via, the total time delay of the reference signal line in transmitting a reference signal between the processor and the receiving end can be more accurately determined. According to the total time delay, a target time delay range of a target signal line is determined, and wiring design of the target signal line is performed according to the target time delay range. The wiring path of the target signal line can be reasonably controlled in time delay, so that the timing requirement of a high-speed signal can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of printed circuit board design, and in particular to a wiring method, device, equipment, medium and product of a storage device. BACKGROUND

[0002] In the printed circuit board (PCB) design of a storage device based on a source synchronous clock bus architecture, in order to meet the timing requirements of signals, the related signals of the storage device need to be designed by "winding equal length".

[0003] However, as the signal rate is getting higher and higher, the timing requirements of signals are getting more and more stringent, and the existing wiring design method based on the equal length of physical wiring length is difficult to meet the timing requirements of high-speed signals. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a wiring method, device, equipment, medium and product of a storage device, which can meet the timing requirements of high-speed signals.

[0005] To solve the above technical problems, in a first aspect, the embodiments of the present application provide a wiring method of a storage device, the method comprising:

[0006] obtaining a first wiring path of a reference signal line between a processor and a receiving end in the storage device;

[0007] determining a total delay corresponding to the reference signal line according to processor delay information and receiving end delay information corresponding to the first wiring path, and delay information of each wiring layer and delay information of each via corresponding to the first wiring path;

[0008] determining a target delay range corresponding to a target signal line according to the total delay corresponding to the reference signal line;

[0009] determining a wiring path of the target signal line according to the target delay range.

[0010] Optionally, determining the wiring path of the target signal line according to the target delay range comprises:

[0011] determining a combination of alternative wiring layers of the target signal line and length information of each via corresponding to the combination of alternative wiring layers according to the wiring space of each wiring layer between the processor and the receiving end;

[0012] determining delay information of the via corresponding to the combination of alternative wiring layers according to the length information of each via corresponding to the combination of alternative wiring layers;

[0013] determine a length of each routing layer in the candidate routing layer combination according to the target delay range, a propagation delay of each routing layer in the candidate routing layer combination, and processor delay information, receiving end delay information and via delay information corresponding to the candidate routing layer combination;

[0014] determine the routing path of the target signal line according to the length information of each via corresponding to the candidate routing layer combination and the length of each routing layer corresponding to the candidate routing layer combination.

[0015] Optionally, in the case that there are multiple candidate routing layer combinations for the target signal line, the determining of the routing path of the target signal line according to the length information of each via corresponding to the candidate routing layer combination and the length of each routing layer corresponding to the candidate routing layer combination comprises:

[0016] determine multiple candidate routing paths according to the length information of each via corresponding to each of the multiple candidate routing layer combinations and the length of each routing layer corresponding to the candidate routing layer combination;

[0017] determine a total delay corresponding to each of the multiple candidate routing paths;

[0018] determine the routing path of the target signal line from the multiple candidate routing paths according to the total delay corresponding to the reference signal line and the total delay corresponding to each of the multiple candidate routing paths.

[0019] Optionally, for each routing layer corresponding to the first routing path, the delay information of the routing layer is determined by the following steps:

[0020] obtain a propagation delay of the routing layer;

[0021] determine the delay information of the routing layer according to the length of the routing layer of the first routing path on the routing layer and the propagation delay of the routing layer.

[0022] Optionally, for each via corresponding to the first routing path, the delay information of the via is determined by the following steps:

[0023] determine a parasitic parameter of the via according to length information of the via;

[0024] determine the delay information of the via according to the parasitic parameter.

[0025] Optionally, the reference signal line is used for transmitting any one of a data signal, a data strobe signal and a clock signal;

[0026] in the case that the reference signal line is used for transmitting a data signal, the target signal line is used for transmitting a same type signal in a group of the data signal;

[0027] In the case that the reference signal line is used to transmit a data strobe signal, the target signal line is used to transmit a data signal.

[0028] In the case that the reference signal line is used to transmit a clock signal, the target signal line is used to transmit a command signal or a control signal.

[0029] In a second aspect, the embodiments of the present application further provide a wiring device of a storage device, and the device comprises:

[0030] a first obtaining module, configured to obtain a first wiring path of a reference signal line between a processor and a receiving end in the storage device;

[0031] a first processing module, configured to determine a total time delay corresponding to the reference signal line according to processor time delay information and receiving end time delay information corresponding to the first wiring path, and time delay information of each wiring layer and time delay information of each via corresponding to the first wiring path;

[0032] a second processing module, configured to determine a target time delay range corresponding to a target signal line according to the total time delay corresponding to the reference signal line;

[0033] a third processing module, configured to determine a wiring path of the target signal line according to the target time delay range.

[0034] In a third aspect, the embodiments of the present application further provide an electronic device, comprising a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the wiring method of the storage device as described in the first aspect.

[0035] In a fourth aspect, the embodiments of the present application further provide a computer readable storage medium, which stores a computer program / instruction, and the computer program / instruction is executed by a processor to implement the wiring method of the storage device as described in the first aspect.

[0036] In a fifth aspect, the embodiments of the present application further provide a computer program product, comprising a computer program / instruction, and the computer program / instruction is executed by a processor to implement the wiring method of the storage device as described in the first aspect.

[0037] As can be seen from the above technical solutions, by comprehensively considering the time delays generated at the processor, the receiving end, each wiring layer and the via of the reference signal line, the total time delay of the reference signal line in transmitting the reference signal between the processor and the receiving end can be more accurately determined, the target time delay range of the target signal line is determined according to the total time delay, and the wiring path of the target signal line is designed according to the target time delay range, so that the wiring path of the target signal line can be reasonably controlled, thereby meeting the timing requirements of high-speed signals. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0039] Figure 1 A schematic diagram of a DDR signal wiring topology provided for the embodiments of the present application;

[0040] Figure 2 A schematic diagram of another DDR signal wiring topology provided for the embodiments of the present application;

[0041] Figure 3 An implementation flowchart of a wiring method of a storage device provided for the embodiments of the present application;

[0042] Figure 4 An implementation flowchart of a wiring path of a target signal line provided for the embodiments of the present application;

[0043] Figure 5 A structural schematic diagram of a wiring device of a storage device provided for the embodiments of the present application;

[0044] Figure 6 A schematic diagram of an electronic device provided for the embodiments of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the protection scope of the present application.

[0046] The terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can include steps or units not listed.

[0047] The main function of the storage device is to store programs and various data, and can complete the access of programs or data automatically and at high speed during the operation of the computer. Currently, the most commonly used in the field of notebook computers, servers, storage and other fields is double data rate synchronous dynamic random access memory (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory). DDR SDRAM adopts a source synchronous clock bus architecture, which can greatly improve the speed of the bus. In theory, the transmission of signals can not be affected by transmission delay.

[0048] DDR SDRAM transmits signals once at the rising and falling edges of the clock cycle, which makes its data transmission speed twice that of single data rate synchronous dynamic random access memory (SDR SDRAM, Single Data Rate Synchronous Dynamic Random Access Memory), and does not increase power consumption. As for the address and control signals of DDR SDRAM, they are the same as those of SDR SDRAM, and are only transmitted at the rising edge, which is a compromise for compatibility and performance of the memory controller at that time. The data transmission rate of the DDR bus has experienced from 400Mbps of DDR1 to 800Mbps of DDR2 to 1600Mbps of DDR3 to 3200Mbps of DDR4 to 6400Mbps of DDR5 that is about to enter the market. The signal transmission rate has been greatly improved.

[0049] Since DDR SDRAM is a bus based on a source synchronous clock architecture, as the signal rate becomes higher and higher, the timing requirements for signals become more and more stringent. In the design of DDR SDRAM, the wiring design of data (DQ) signals and data strobe (DQS) signals is related, and the wiring design of command (CMD) signals and control (CTL) signals is related to the clock (CLK) signal. Since the rate of DQ signals is twice that of CMD and CTL signals, the transmission delay requirement (i.e. timing requirement) between DQ signals and DQS signals is higher than that between CMD signals, CTL signals and CLK signals respectively.

[0050] As the signal rate of DDR SDRAM continues to increase, in the design of DDR SDRAM (such as DDR5), especially for the wiring design of the transmission delay requirement between DQ signals and DQS signals, designers will be challenged more. At the same time, the timing margin left for the PCB wiring of the source synchronous signal with high timing requirement is less and less, so it is particularly important to accurately know the influence of the PCB wiring on the signal delay in the PCB design stage.

[0051] In the prior PCB design, in order to meet the timing requirements, the same group of signals of the DDR SDRAM needs to be designed with equal length.

[0052] However, in actual projects, due to the wiring space limitation of the PCB, the related signals (such as the data signals of the same group) may appear on different layers.

[0053] For the convenience of understanding, a certain specific link is taken as an example for detailed description: as shown in Figure 1 and Figure 2 The schematic diagram of the DDR signal wiring topology is shown, and the DDR signal from the CPU reaches the terminal through the wiring on the PCB. The DDR signal line can only be in the inner layer L3 of the PCB (as shown in Figure 2 ), and the DDR signal line can have both surface layer L1 wiring and inner layer L2 wiring (as shown in Figure 1 ).

[0054] It can be understood that in addition to the length of the wiring path, the different wiring paths have differences in the effective dielectric constant, the geometric structure of the transmission line cross section, the via parameter and other factors due to the wiring layers they pass through, which will also affect the propagation delay of the wiring path. If the traditional physical wiring length is still used for "round equal length" wiring design, the situation that the length difference of each signal line meets the requirements, but the timing (i.e. the transmission delay difference of each signal line) cannot meet the requirements will occur. For the current timing requirements of high-speed signals, if the timing is problematic, it will greatly increase the design risk, reduce the performance of the product, increase the design cost, lengthen the product development cycle, and reduce the economic benefits of the company.

[0055] In view of the problems in the related art, the wiring design method based on the physical wiring length control is optimized to the wiring design method based on the propagation delay time control, and the total delay determination of the signal line is optimized, thereby improving the timing design accuracy of the high-speed signal wiring, and further improving the performance of the product, reducing the design cost, reducing the workload of the designer, shortening the product development cycle, reducing the development expenditure and increasing the economic benefits.

[0056] The wiring method of the storage device provided by the embodiments of the present application will be described in detail in combination with the drawings and some embodiments and application scenarios.

[0057] In a first aspect, referring to Figure 3 , an implementation flowchart of a wiring method of a storage device provided by the embodiments of the present application is shown. The method can include the following steps:

[0058] Step S101: obtaining a first wiring path of a reference signal line between a processor and a receiving end in a storage device.

[0059] In a specific implementation, the designer can design a first routing path of the reference signal line between a processor (such as a CPU) and a receiving end in advance according to the structural layout and routing space of the storage device. For example, the first routing path A1 can be: CPU-> routing on the PCB surface layer L1-> via Z1-> routing on the first inner layer L2 of the PCB-> via Z2-> receiving end.

[0060] In step S102, total latency corresponding to the reference signal line is determined according to processor latency information and receiving end latency information, and latency information of each routing layer and latency information of each via corresponding to the first routing path.

[0061] The processor latency information and the receiving end latency information refer to latency generated by package-level interconnection (which can be referred to as pin delay or package length), such as latency between a chip and a package pin, or delay on each column of pins in a high-speed connector (such as a bend pin connector); the total latency refers to the sum of latency of signals transmitted on each transmission medium between the processor and the receiving end; and the latency (which can also be referred to as transmission latency) refers to the time taken by an electromagnetic signal or an optical signal to pass through the entire transmission medium.

[0062] In a specific implementation, the processor latency information and the receiving end latency information can be determined according to package-level interconnection length parameters provided by a chip or connector manufacturer, and the processor latency information and the receiving end latency information are introduced into the determination of the total latency to improve the accuracy of the determined total latency.

[0063] In the case where the package-level interconnection length parameter is length data, the pin delay (which can be in picoseconds) can be determined according to the propagation speed of the signal and the length data. The propagation speed of the signal C represents the speed of light in a vacuum, and εr represents the dielectric constant of the signal carrier.

[0064] Taking the first routing path A1 as an example, the total latency of the first routing path A1 is the sum of the pin delay of the processor (i.e., the processor latency information), the pin delay of the receiving end (i.e., the receiving end latency information), the latency on the routing on the PCB surface layer L1 and the latency on the routing on the first inner layer L2 of the PCB (i.e., the latency information of each routing layer), and the latency of the vias Z1 and Z2 (i.e., the latency information of each via).

[0065] As a possible implementation, the reference signal line is used to transmit any one of a data signal, a data strobe signal, and a clock signal;

[0066] In the case where the reference signal line is used to transmit a data signal, the target signal line is used to transmit a same-type signal in a group of the data signal.

[0067] In the case that the reference signal line is used to transmit a data strobe signal, the target signal line is used to transmit a data signal.

[0068] In the case that the reference signal line is used to transmit a clock signal, the target signal line is used to transmit a command signal or a control signal.

[0069] It can be understood that the signal transmitted in the reference signal line and the signal transmitted in the target signal line should be signals that can meet the synchronous transmission requirement, such as each data signal in the same group, a data signal and a data strobe signal, a clock signal and a transmission command signal, or a clock signal and a control signal, which are usually synchronously transmitted.

[0070] In the case that the signal transmitted in the reference signal line and the signal transmitted in the target signal line meet the synchronous transmission requirement, the present application designs the routing path of the target signal line according to the total delay of the reference signal line, so as to accurately control the total delay difference between the reference signal line and the target signal line, and in the case that the transmission delay of the signal transmitted in the reference signal line and the signal transmitted in the target signal line is almost consistent, even if the system has a large maximum clock frequency, as long as the timing sent by the CPU is correct, the receiving end can obtain correct timing, so as to meet the timing requirement of high-speed signals.

[0071] As a possible implementation, in the case that the reference signal line is used to transmit a data signal, the target signal line can include a plurality of first signal lines used to transmit signals of the same type in each group (i.e. other data signals in the same group), and the target delay range can include any delay that makes the difference between the maximum and minimum of the total delay of the current target signal line and each first signal line lower than a set value.

[0072] Step S103: determining a target delay range corresponding to the target signal line according to the total delay corresponding to the reference signal line.

[0073] In the specific implementation, the delay requirement between the reference signal line and the target signal line can be found according to the chip data manual, such as the delay requirement is 8.5 picoseconds, then according to the total delay T1 corresponding to the reference signal line, the target delay range corresponding to the target signal line is between (T1-8.5) and (T1+8.5).

[0074] Step S104: determining the routing path of the target signal line according to the target delay range.

[0075] In a specific implementation, the target delay range provides effective guidance for the routing design of the target signal line, and the designer can perform routing design on each routing layer of the PCB according to the target delay range, and calculate the total delay of the designed routing path in real time. When the total delay of the designed routing path is within the target delay range, the final routing path of the target signal line that meets the timing requirement is obtained.

[0076] It can be understood that, based on the above routing design based on the target delay range, the delay difference between the reference signal line and the target signal line can be accurately controlled, so that the designed routing path can meet the timing requirement of the high-speed signal (such as the DDR signal), and the working efficiency of the designer can be improved and the design cost can be reduced.

[0077] As can be seen from the above technical solution, by comprehensively considering the delays of the reference signal line at the processor, the receiving end, each routing layer, and the via, the total delay of the reference signal line in transmitting the reference signal between the processor and the receiving end can be more accurately determined, the target delay range of the target signal line is determined according to the total delay, and the routing design of the target signal line is performed according to the target delay range. The routing path of the target signal line can be reasonably controlled, so that the timing requirement of the high-speed signal can be met.

[0078] Embodiment one

[0079] This embodiment describes an example of the delay information of the routing layer.

[0080] For each routing layer (such as a PCB surface layer or any inner layer of the PCB) corresponding to the routing path (such as the first routing path) of any signal line, the delay information of the routing layer is determined by the following steps: obtaining the propagation delay of the routing layer; and determining the delay information of the routing layer according to the routing length of the first routing path on the routing layer and the propagation delay of the routing layer.

[0081] It can be understood that the delay is the product of the propagation delay and the transmission length, the propagation delay is the time delay of the electromagnetic signal or the optical signal in the transmission medium (such as the routing layer) in unit length, and the propagation delay is inversely proportional (i.e. reciprocal) to the propagation speed. The unit of propagation delay can be "picoseconds / inch" or "seconds / meter" and the like.

[0082] In a specific implementation, considering that the propagation delay mainly depends on the dielectric constant of the medium material, the dielectric constant of each routing layer on the PCB can be queried from the plate material data in advance, and the propagation speed of each routing layer is determined according to the dielectric constant, and then the propagation delay of the routing layer is obtained.

[0083] Taking a certain routing layer as an FR4 board as an example, according to the board data, the dielectric constant of the routing layer is 4, and the propagation speed Vp of the routing layer is Vp=(3*10^8) / sqrt(4)=1.5*10^8 m / s, and the reciprocal of the propagation speed is the propagation delay of the routing layer.

[0084] Embodiment Two

[0085] This embodiment describes an example of via time delay information.

[0086] For each via (such as via Z1 or Z2 in the first routing path A1) corresponding to a routing path (such as the first routing path) of any signal line, the time delay information of the via is determined by the following steps: determining the parasitic parameter of the via according to the length information of the via; and determining the time delay information of the via according to the parasitic parameter.

[0087] It should be noted that the time delay information of the via refers to the time delay of the signal passing through the via. In PCB design, due to the limitation of PCB wiring space, routing layer switching often occurs, that is, the routing path of the signal line will pass through multiple routing layers. Routing layer switching must rely on vias, but the time delay between vias with equal lengths and routing on the routing layer is not equal. Therefore, the via time delay information is introduced into the total time delay calculation of the signal line to further improve the control accuracy of the time delay difference between the reference signal line and the target signal line.

[0088] As a possible implementation, the parasitic parameter can include parasitic inductance and parasitic capacitance, and the time delay information of the via Wherein, TD_via represents the time delay information of the via; L represents the parasitic inductance of the via, the parasitic inductance L=5.08*h[ln(4h / d)+1], h represents the length of the via, and d represents the diameter of the center drill hole; C represents the parasitic capacitance of the via, the parasitic capacitance C=1.41*k*T*D1 / (D2-D1), D2 is the isolation hole diameter of the via on the ground layer, D1 is the diameter of the via pad, T is the thickness of the PCB board, and k is the dielectric constant of the via board.

[0089] Embodiment Three

[0090] This embodiment describes an example of determining the routing path of the target signal line, such as Figure 4 As shown, it specifically includes the following steps:

[0091] Step S201: According to the routing space of each routing layer between the processor and the receiving end, determine the candidate routing layer combination of the target signal line, and the length information of each via corresponding to the candidate routing layer combination.

[0092] In implementation, at least one candidate routing layer suitable for routing can be determined according to the wiring space of the current PCB, and at least one candidate routing layer combination for composing a routing path can be determined according to the at least one candidate routing layer. For example, for the candidate routing layers L1 and L2, the candidate routing layer combinations can include: L1; L2; L1 and L2. After determining the candidate routing layer combinations, the routing layer required for connecting the via can be determined, and then the length information of the via can be determined.

[0093] In step S202, the delay information of the via corresponding to the candidate routing layer combination is determined according to the length information of the via corresponding to the candidate routing layer combination.

[0094] In implementation, the parasitic parameter of the via can be determined according to the length information of the via, and then the delay information of the via can be determined. The determination of the delay information of the via is specifically described in Embodiment 2, which is not repeated here.

[0095] In step S203, the routing length of each routing layer in the candidate routing layer combination is determined according to the target delay range, the propagation delay of each routing layer in the candidate routing layer combination, and the processor delay information, the receiving end delay information and the delay information of the via corresponding to the candidate routing layer combination.

[0096] In implementation, for any candidate routing layer combination, the sum of the processor delay information, the receiving end delay information and the delay information of the via corresponding to the candidate routing layer combination can be determined as a first delay, and the first delay range required to be met by each routing layer in the candidate routing layer combination can be determined according to the first delay and the target delay range. Then different routing lengths can be set in each routing layer of the candidate routing layer combination, and the current delay sum of each routing layer can be calculated in real time until the delay sum of each routing layer is within the first delay range, and then the routing length corresponding to each routing layer in the candidate routing layer combination can be obtained.

[0097] In step S204, the routing path of the target signal line is determined according to the length information of each via corresponding to the candidate routing layer combination and the routing length corresponding to each routing layer.

[0098] In this embodiment, when there are multiple candidate routing layer combinations of the target signal line, multiple candidate routing paths can be determined according to the length information of each via corresponding to each of the multiple candidate routing layer combinations and the routing length corresponding to each routing layer, and the total delay corresponding to each of the multiple candidate routing paths can be determined.

[0099] After determining the total time delay corresponding to each of the plurality of candidate routing paths, a candidate routing path with the minimum total time delay or the minimum difference in total time delay from the reference signal line can be selected as the routing path of the target signal line according to the total time delay corresponding to the reference signal line and the total time delay corresponding to each of the plurality of candidate routing paths, thereby further achieving time delay control of the target signal line.

[0100] As a possible implementation, the above routing method of the storage device can be implemented by an automation program created based on the Python programming language. The automation program can automatically calculate the propagation delay of each routing layer according to the relevant parameters of the medium material (such as the dielectric constant, the geometric structure of the transmission line cross section (the geometric structure determines the electric field distribution, and the electric field distribution determines the effective dielectric constant), etc.), access a database to obtain the total time delay of the reference signal line, and then determine the target time delay range, and automatically calculate the candidate routing layer combination and the corresponding routing length on each routing layer, thereby providing routing guidance for designers, achieving routing automation, reducing the workload of designers, improving work efficiency, shortening the product development cycle, thereby reducing the company's research and development expenditure and increasing economic benefits.

[0101] In a second aspect, an embodiment of the present application provides a routing device of a storage device, as shown in the accompanying drawings, the device comprises: Figure 5 As shown in the accompanying drawings, the device comprises:

[0102] A first acquisition module 21 is configured to acquire a first routing path of a reference signal line between a processor and a receiving end in a storage device.

[0103] The storage device is a storage device based on a source synchronous clock bus architecture (such as DDR SDRAM, etc.).

[0104] A first processing module 22 is configured to determine a total time delay corresponding to the reference signal line according to processor time delay information and receiving end time delay information corresponding to the first routing path, and time delay information of each routing layer and time delay information of each via corresponding to the first routing path.

[0105] The processor time delay information and the receiving end time delay information refer to the time delay generated by the package-level interconnection (which can be referred to as pin delay or package length); the total time delay refers to the sum of the time delays of the signals transmitted on each transmission medium between the processor and the receiving end; and the time delay (which can also be referred to as transmission time delay) refers to the time taken by an electromagnetic signal or an optical signal to pass through the entire transmission medium.

[0106] A second processing module 23 is configured to determine a target time delay range corresponding to a target signal line according to the total time delay corresponding to the reference signal line.

[0107] The signal transmitted in the reference signal line and the signal transmitted in the target signal line should be signals that can meet the synchronous transmission requirement, such as various data signals in the same group for synchronous transmission, a data signal and a data strobe signal, a clock signal and a transmission command signal, or a clock signal and a control signal.

[0108] The third processing module 24 is configured to determine the routing path of the target signal line according to the target delay range.

[0109] It can be understood that the target delay range provides effective guidance for the routing design of the target signal line. The designer can perform routing design on each routing layer of the PCB according to the target delay range, and calculate the total delay of the designed routing path in real time. When the total delay of the designed routing path is within the target delay range, the final routing path of the target signal line that meets the timing requirement is obtained.

[0110] Based on the routing design according to the target delay range, the delay difference between the reference signal line and the target signal line can be accurately controlled, so that the designed routing path can meet the timing requirement of high-speed signals (such as DDR signals), and the working efficiency of the designer can be improved and the design cost can be reduced.

[0111] Optionally, the third processing module 24 includes:

[0112] A first processing submodule is configured to determine a candidate routing layer combination of the target signal line and length information of each via corresponding to the candidate routing layer combination according to the routing space of each routing layer between the processor and the receiving end.

[0113] A second processing submodule is configured to determine delay information of the via corresponding to the candidate routing layer combination according to the length information of each via corresponding to the candidate routing layer combination.

[0114] A third processing submodule is configured to determine the routing length of each routing layer corresponding to the candidate routing layer combination according to the target delay range, the propagation delay of each routing layer in the candidate routing layer combination, and the processor delay information, the receiving end delay information and the delay information of the via corresponding to the candidate routing layer combination.

[0115] A fourth processing submodule is configured to determine the routing path of the target signal line according to the length information of each via corresponding to the candidate routing layer combination and the routing length of each routing layer.

[0116] Optionally, in the case that there are multiple candidate routing layer combinations of the target signal line, the fourth processing submodule includes:

[0117] a first determining module, configured to determine a plurality of candidate routing paths according to length information of each via corresponding to each of a plurality of candidate routing layer combinations and routing length of each routing layer corresponding to the candidate routing layer combinations;

[0118] a second determining module, configured to determine total time delay corresponding to each of the plurality of candidate routing paths;

[0119] a third determining module, configured to determine a routing path of the target signal line from the plurality of candidate routing paths according to total time delay corresponding to the reference signal line and total time delay corresponding to each of the plurality of candidate routing paths.

[0120] Optionally, for each routing layer corresponding to the first routing path, the first processing module 22 comprises:

[0121] a fifth processing submodule, configured to obtain propagation delay of the routing layer;

[0122] a sixth processing submodule, configured to determine time delay information of the routing layer according to routing length of the first routing path on the routing layer and the propagation delay of the routing layer.

[0123] Optionally, for each via corresponding to the first routing path, the first processing module 22 comprises:

[0124] a seventh processing submodule, configured to determine parasitic parameter of the via according to length information of the via;

[0125] an eighth processing submodule, configured to determine time delay information of the via according to the parasitic parameter.

[0126] wherein the parasitic parameter can include parasitic inductance and parasitic capacitance, and the time delay information of the via is TD_via=L*sqrt(C / L) wherein TD_via represents the time delay information of the via; L represents the parasitic inductance of the via, the parasitic inductance L=5.08*h[ln(4h / d)+1], h represents the length of the via, and d represents the diameter of the center drill hole; C represents the parasitic capacitance of the via, the parasitic capacitance C=1.41*k*T*D1 / (D2-D1), D2 is the isolation hole diameter of the via on the routing layer, D1 is the diameter of the via pad, T is the thickness of the PCB, and k is the dielectric constant of the via plate material.

[0127] Optionally, the reference signal line is configured to transmit any one of a data signal, a data strobe signal and a clock signal;

[0128] in a case where the reference signal line is configured to transmit a data signal, the target signal line is configured to transmit a same type of signal within a group of the data signal;

[0129] In a case where the reference signal line is used to transmit a data strobe signal, the target signal line is used to transmit a data signal.

[0130] In a case where the reference signal line is used to transmit a clock signal, the target signal line is used to transmit a command signal or a control signal.

[0131] It can be seen from the above technical solution that by comprehensively considering the time delay of the reference signal line at the processor, the receiving end, each wiring layer and the via hole, the total time delay of the reference signal line in transmitting the reference signal between the processor and the receiving end can be more accurately determined, the target time delay range of the target signal line is determined according to the total time delay, and the wiring design of the target signal line is performed according to the target time delay range, so that the wiring path of the target signal line can be reasonably controlled in time delay, thereby meeting the timing requirements of high-speed signals.

[0132] It should be noted that the device embodiment is similar to the method embodiment, and therefore the description is relatively simple, and the related parts can be referred to the method embodiment.

[0133] The embodiment of the present application further provides an electronic device, referring to Figure 6 , Figure 6 is a schematic diagram of an electronic device according to the embodiment of the present application. As shown in Figure 6 , the electronic device 100 includes a memory 110 and a processor 120, the memory 110 and the processor 120 are connected by a bus in communication, the memory 110 stores a computer program, the computer program can run on the processor 120, and then the steps in the wiring method of the storage device disclosed by the embodiment of the present application are implemented.

[0134] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program / instruction, and the computer program / instruction is executed by a processor to implement the wiring method of the storage device disclosed by the embodiment of the present application.

[0135] The embodiment of the present application further provides a computer program product, which includes a computer program / instruction, and the computer program / instruction is executed by a processor to implement the wiring method of the storage device disclosed by the embodiment of the present application.

[0136] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0137] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the embodiments of the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0138] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, systems, devices, storage media, and program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and a combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminals to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminals generate an apparatus implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowcharts and / or block diagrams.

[0139] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing terminal to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatuses that implement the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowcharts and / or block diagrams.

[0140] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal, so that a series of operation steps are performed on the computer or other programmable terminal to produce a computer-implemented process, so that the instructions executed on the computer or other programmable terminal provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that implements the functions specified in the flowcharts and / or block diagrams.

[0141] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to the embodiments once they have understood the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0142] Finally, it is to be understood that the phraseology or terminology such as "first" and "second" etc. used herein is merely intended to distinguish one entity or operation from another without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0143] The wiring method, device, equipment, medium and product of the storage device provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above example is only used to help understand the method and core idea of the present application; meanwhile, for those skilled in the art, the specific implementation manner and application range can be changed according to the idea of the present application. In conclusion, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A wiring method for a storage device, characterized in that: The method comprises: Acquire a first routing path of a reference signal line between a processor and a receiving end in a storage device; Determine a total delay corresponding to the reference signal line according to processor delay information and receiving end delay information corresponding to the first routing path, and delay information of each routing layer and delay information of each via corresponding to the first routing path; Determining a target delay range corresponding to a target signal line according to a total delay corresponding to the reference signal line; Determining a routing path of the target signal line according to the target delay range; Determining a routing path of the target signal line according to the target delay range includes: Determining, based on routing spaces of each routing layer between the processor and the receiving end, a candidate routing layer combination of the target signal line and length information of each via corresponding to the candidate routing layer combination; Determining delay information of the vias corresponding to the candidate routing layer combination according to length information of each via corresponding to the candidate routing layer combination; Determine the routing length corresponding to each routing layer in the candidate routing layer combination according to the target delay range, the propagation delay of each routing layer in the candidate routing layer combination, and the processor delay information, the receiving end delay information, and the via delay information corresponding to the candidate routing layer combination; The routing path of the target signal line is determined according to the length information of each via corresponding to the candidate routing layer combination and the routing length corresponding to each routing layer.

2. The method according to claim 1, characterized in that In a case where there are multiple candidate routing layer combinations for the target signal line, determining a routing path for the target signal line according to length information of each via corresponding to the candidate routing layer combination and routing lengths corresponding to each routing layer includes: Determining a plurality of candidate routing paths according to the length information of the respective vias corresponding to the plurality of candidate routing layer combinations and the routing lengths corresponding to the respective routing layers; Determining the total delay corresponding to each of the multiple candidate routing paths; According to the total delay corresponding to the reference signal line and the total delays corresponding to each of the multiple candidate routing paths, a routing path of the target signal line is determined from the multiple candidate routing paths.

3. The method according to claim 1 or 2, characterized in that For each routing layer corresponding to the first routing path, the delay information of the routing layer is determined by the following steps: Obtaining the propagation delay of the routing layer; Delay information of the routing layer is determined according to a routing length of the first routing path in the routing layer and a propagation delay of the routing layer.

4. The method according to claim 1 or 2, characterized in that For each via corresponding to the first routing path, the delay information of the via is determined by the following steps: determining parasitic parameters of the via according to the length information of the via; Delay information of the via is determined according to the parasitic parameters.

5. The method according to claim 1 or 2, characterized in that The reference signal line is used to transmit any one of a data signal, a data strobe signal and a clock signal; In the case where the reference signal line is used to transmit a data signal, the target signal line is used to transmit a signal of the same type within a group of the data signal; In the case where the reference signal line is used to transmit a data strobe signal, the target signal line is used to transmit a data signal; In the case where the reference signal line is used to transmit a clock signal, the target signal line is used to transmit a command signal or a control signal.

6. A wiring device for a storage device, characterized in that: The device comprises: A first acquisition module, configured to acquire a first routing path of a reference signal line between a processor and a receiving end in a storage device; a first processing module, configured to determine a total delay corresponding to the reference signal line based on processor delay information and receiving end delay information corresponding to the first routing path, and delay information of each routing layer and delay information of each via corresponding to the first routing path; A second processing module is configured to determine a target delay range corresponding to a target signal line according to a total delay corresponding to the reference signal line; A third processing module, configured to determine a routing path of the target signal line according to the target delay range; The third processing module is further configured to perform the following steps: Determining, based on routing spaces of each routing layer between the processor and the receiving end, a candidate routing layer combination of the target signal line and length information of each via corresponding to the candidate routing layer combination; Determining delay information of the vias corresponding to the candidate routing layer combination according to length information of each via corresponding to the candidate routing layer combination; Determine the routing length corresponding to each routing layer in the candidate routing layer combination according to the target delay range, the propagation delay of each routing layer in the candidate routing layer combination, and the processor delay information, the receiving end delay information, and the via delay information corresponding to the candidate routing layer combination; The routing path of the target signal line is determined according to the length information of each via corresponding to the candidate routing layer combination and the routing length corresponding to each routing layer.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the storage device wiring method according to any one of claims 1 to 5.

8. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the wiring method of the storage device according to any one of claims 1 to 5 is implemented.

9. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the wiring method of the storage device according to any one of claims 1 to 5 is implemented.

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