Pixel detection device and pixel detection method

Abstract

A pixel detection device includes a data line, a pixel circuit, and a detection circuit. The pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source. The detection circuit is coupled to the data line and the pixel circuit and is configured to receive a drive signal and a detection control signal. The detection circuit, the system low voltage source, and the data line form a first detection loop, which detects whether the pixel circuit is abnormal based on the drive signal and the detection control signal in a first phase. The detection circuit, the first reference voltage source, the system low voltage source, the pixel circuit, and the data line form a second detection loop, which detects whether the pixel circuit is abnormal based on the drive signal and the detection control signal in a second phase.

Description

Technical Field

[0001] This case involves a detection device and a detection method. Specifically, this case involves a pixel detection device and a pixel detection method. Background Art

[0002] Existing mini light-emitting diodes (mini LEDs) require high drive currents. The power supply voltage that generates the drive current is prone to current errors, resulting in different voltages for each pixel and errors in the output current.

[0003] Furthermore, in existing pixel driver circuits, when micro-LEDs need to output high brightness, the driver transistors must generate high currents. When high current flows through the path between two power supply voltages, the transistors along this path tend to enter their linear region, making the drive current difficult to control.

[0004] In addition, the existing pixel driving circuit only has the internal function of the self-compensation circuit. If an abnormality occurs in the pixel driving circuit, the self-compensation function cannot operate.

[0005] Therefore, the above technology still has many defects, and practitioners in this field are waiting to develop other suitable pixel detection devices. Summary of the Invention

[0006] One aspect of this case relates to a pixel detection device. The pixel detection device includes a data line, a pixel circuit, and a detection circuit. The pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source. The detection circuit is coupled to the data line and the pixel circuit and is used to receive a drive signal and a detection control signal. The detection circuit, the system low voltage source, and the data line form a first detection loop, which detects whether the pixel circuit is abnormal based on the drive signal and the detection control signal in a first stage. The detection circuit, the first reference voltage source, the system low voltage source, the pixel circuit, and the data line form a second detection loop, which detects whether the pixel circuit is abnormal based on the drive signal and the detection control signal in a second stage.

[0007] Another aspect of the present invention relates to a pixel detection device. The pixel detection device includes a signal line, a pixel circuit, and a detection circuit. The pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source. The detection circuit is coupled to the signal line, the pixel circuit, and the first reference voltage source, and is used to receive a first drive signal and a detection control signal. The detection circuit, the first reference voltage source, the pixel circuit, and the signal line form a first detection loop, thereby detecting whether the pixel circuit is abnormal according to the first drive signal and the detection control signal in the first stage. The detection circuit, the system low voltage source, the pixel circuit, and the signal line form a second detection loop, thereby detecting whether the pixel circuit is abnormal according to the first drive signal in the second stage.

[0008] Another aspect of the present invention relates to a pixel detection method. The pixel detection method is applicable to a pixel detection device. The pixel detection device includes a signal line, a pixel circuit, and a detection circuit. The pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source. The detection circuit is coupled to the signal line and the pixel circuit. The pixel detection method includes the following steps: in a first stage, a first detection signal is input to the pixel circuit via a first reference voltage source; in the first stage, the first detection signal is received via the detection circuit and the signal line, thereby determining whether the pixel circuit is abnormal based on the first detection signal; in a second stage, a second detection signal is input to the pixel circuit via the system low voltage source; and in the second stage, a second detection signal is received via the detection circuit and the signal line, thereby determining whether the pixel circuit is abnormal based on the second detection signal.

[0009] In view of the above-mentioned shortcomings and deficiencies of the prior art, this case provides a pixel detection device and a pixel detection method. By means of the circuit design of the pixel detection device, the pixels can be detected or externally compensated, and the power consumption of the pixel detection device during display is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The content of this case can be better understood by referring to the embodiments in the following paragraphs and the following figures:

[0011] Figure 1 is a circuit block diagram of a pixel detection device according to some embodiments of the present invention;

[0012] Figure 2 is a signal timing diagram of a pixel detection device according to some embodiments of the present invention;

[0013] Figure 3 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0014] Figure 4 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0015] Figure 5 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0016] Figure 6 1 is a schematic flow chart illustrating the steps of a pixel detection method according to some embodiments of the present invention;

[0017] Figure 7 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0018] Figure 8 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0019] Figure 9 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0020] Figure 10 is a schematic diagram of a pixel detection device according to some embodiments of the present invention;

[0021] Figure 11 is a signal timing diagram of a pixel detection device according to some embodiments of the present invention;

[0022] Figure 12 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0023] Figure 13 is a signal timing diagram of a pixel detection device according to some embodiments of the present invention;

[0024] Figure 14 is a schematic diagram of circuit states of a pixel detection device according to some embodiments of the present invention;

[0025] Figure 15 is a signal timing diagram of a pixel detection device according to some embodiments of the present invention; and

[0026] Figure 16 FIG. 1 is a schematic diagram illustrating circuit states of a pixel detection device according to some embodiments of the present invention.

[0027] The description of the accompanying drawings is as follows:

[0028] 100, 300: Pixel detection device

[0029] 110, 310: Pixel circuit

[0030] 111, 311: Reset circuit

[0031] 112, 312: Compensation circuit

[0032] 113, 313: Write circuit

[0033] 120, 320: Detection circuit

[0034] C1~C2:Capacitors

[0035] DT1, T1~T9: transistors

[0036] LED: Light Emitting Device

[0037] N1 to N5: nodes

[0038] Vref1~Vref2: reference voltage source

[0039] VDD: system high voltage source

[0040] VSS: System low voltage source

[0041] DL: data line

[0042] Data: data voltage

[0043] SN(n-1): reset signal

[0044] SN(n): compensation signal

[0045] SN(n+1): write signal

[0046] VC(n): control signal

[0047] EM(n): driving signal

[0048] AT: Detection control signal

[0049] P1: Position

[0050] I1: Driving stage

[0051] I2: Detection Phase

[0052] I11~I13: Sub-stage

[0053] VGH: High level

[0054] VGL: Low level

[0055] 200: Method

[0056] 210-260: Steps

[0057] AT1~AT6: detection circuit

[0058] AT21~AT22: Detection sub-circuit

[0059] SN2(n): First drive signal

[0060] L1: signal line DETAILED DESCRIPTION

[0061] The following diagrams and detailed descriptions clearly illustrate the spirit of the present invention. After understanding the embodiments of the present invention, anyone skilled in the art can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

[0062] The terms used herein are for describing specific embodiments only and are not intended to be limiting of the present invention. Singular forms such as "a," "the," "this," "this," and "the" as used herein also include plural forms.

[0063] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0064] Unless otherwise noted, the terms used herein generally have their ordinary meanings in the art, in the context of this application, and in the specific context. Certain terms used to describe this application are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art regarding the description of this application.

[0065] Figure 1 FIG. 1 is a circuit block diagram of a pixel detection device 100 according to some embodiments of the present invention. Figure 1 As shown, the pixel detection device 100 includes a data line DL, a pixel circuit 110 and a detection circuit 120. The pixel circuit 110 is coupled to a system high voltage source VDD, a system low voltage source VSS, a first reference voltage source Vref1 and a second reference voltage source Vref2. The detection circuit 120 is coupled to the data line DL and the pixel circuit 110.

[0066] In some embodiments, the detection circuit 120 is configured to receive the driving signal EM(n) and the detection control signal AT. The detection circuit 120, together with the system low voltage source VSS and the data line DL, forms a first detection loop (not shown) to detect whether the pixel circuit 110 is abnormal based on the driving signal EM(n) and the detection control signal AT during the first phase.

[0067] Next, the detection circuit 120, the first reference voltage source Vref1, the pixel circuit 110 and the data line DL form a second detection loop (not shown) to detect whether the pixel circuit 110 is abnormal according to the driving signal EM(n) and the detection control signal AT in the second stage.

[0068] It should be noted that the electronic device includes a plurality of pixel detection devices 100. Each pixel detection device 100 is equivalent to a display pixel.

[0069] In some embodiments, see Figure 1 The pixel circuit 110 includes a reset circuit 111, a compensation circuit 112, a write circuit 113, a first node N1, a second node N2, a third node N3 and a fourth node N4, a light-emitting element LED, a driving transistor DT1, a first transistor T1, a second transistor T2, a first capacitor C1 and a second capacitor C2.

[0070] In some embodiments, the reset circuit 111 is coupled to the third node N3, the fourth node N4 and the second reference voltage source Vref2, and is used to reset the third node N3 to the second reference voltage of the second reference voltage source Vref2, thereby resetting the first node N1 and the second node N2 to the system low voltage of the system low voltage source VSS through the driving transistor DT1.

[0071] In some embodiments, the compensation circuit 112 is coupled to the second node N2 , the third node N3 , the fourth node N4 and the reset circuit 111 , and is configured to compensate the third node N3 to the first reference voltage of the first reference voltage source Vref1 .

[0072] In some embodiments, the write circuit 113 is coupled to the fourth node N4 and the data line DL and is configured to receive the data voltage Data of the data line DL and write the data voltage Data into the third node N3 and the fourth node N4 to store the data voltage Data in the first capacitor C1 .

[0073] In some embodiments, see Figure 1 , with the top and right of the device in the figure as the first end, the driving transistor DT1 includes a first end, a second end, and a control end (i.e., the gate end of the driving transistor DT1). The first end of the driving transistor DT1 is coupled to a first node N1. The second end of the driving transistor DT1 is coupled to a second node N2. The control end of the driving transistor DT1 is coupled to a third node N3 and is used to drive the light-emitting device LED based on the voltage level of the third node N3. The first node N1, the second node N2, and the third node N3 are not at the same point.

[0074] In some embodiments, see Figure 1 The first transistor T1 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the first transistor T1). The first terminal of the first transistor T1 is coupled to a first reference voltage source Vref1 and is configured to receive a first reference voltage from the first reference voltage source Vref1. The second terminal of the first transistor T1 is coupled to a first node N1. The control terminal of the first transistor T1 is configured to receive a control signal VC(n). The first transistor T1 is turned on in response to the control signal VC(n).

[0075] In some embodiments, the second transistor T2 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the second transistor T2). The first terminal of the second transistor T2 is coupled to the driving transistor DT1. The second terminal of the second transistor T2 is coupled to the system low voltage source VSS. The control terminal of the second transistor T2 is configured to receive a driving signal EM(n). The second transistor T2 is turned on in response to the driving signal EM(n).

[0076] In some embodiments, the first capacitor C1 includes a first terminal and a second terminal. The first terminal of the first capacitor C1 is coupled to the third node N3. The second terminal of the first capacitor C1 is coupled to the fourth node N4. In some embodiments, the second capacitor C2 includes a first terminal and a second terminal. The first terminal of the second capacitor C2 is coupled to the first node N1 and the first transistor T1. The second terminal of the second capacitor C2 is coupled to the fourth node N4.

[0077] In some embodiments, the reset circuit 111 includes a third transistor T3 and a fourth transistor T4. Furthermore, the third transistor T3 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the third transistor T3). The first terminal of the third transistor T3 is coupled to the third node N3. The second terminal of the third transistor T3 is coupled to the second reference voltage source Vref2. The control terminal of the third transistor T3 is configured to receive a reset signal SN(n-1). The third transistor T3 resets the third node N3 in response to the reset signal SN(n-1).

[0078] Furthermore, the fourth transistor T4 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the fourth transistor T4). The first terminal of the fourth transistor T4 is coupled to the fourth node N4. The second terminal of the fourth transistor T4 is coupled to the second reference voltage source Vref2. The control terminal of the fourth transistor T4 is configured to receive a reset signal SN(n-1). The fourth transistor T4 is turned on in response to the reset signal SN(n-1).

[0079] In some embodiments, the compensation circuit 112 includes a fifth transistor T5 and a sixth transistor T6. Furthermore, the fifth transistor T5 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the fifth transistor T5). The first terminal of the fifth transistor T5 is coupled to the second node N2. The second terminal of the fifth transistor T5 is coupled to the third node N3. The control terminal of the fifth transistor T5 is configured to receive a compensation signal SN(n). The fifth transistor T5 is turned on in response to the compensation signal SN(n).

[0080] Furthermore, the sixth transistor T6 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the sixth transistor T6). The first terminal of the sixth transistor T6 is coupled to the fourth node N4. The second terminal of the sixth transistor T6 is coupled to the second reference voltage source Vref2. The control terminal of the sixth transistor T6 is configured to receive the compensation signal SN(n). The sixth transistor T6 is turned on in response to the compensation signal SN(n).

[0081] In some embodiments, the write circuit 113 includes a seventh transistor T7. The seventh transistor T7 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the seventh transistor T7). The first terminal of the seventh transistor T7 is coupled to the fourth node N4. The second terminal of the seventh transistor T7 is coupled to the data line DL. The control terminal of the seventh transistor T7 is configured to receive a write signal SN(n+1). The seventh transistor T7 is turned on in response to the write signal SN(n+1).

[0082] In some embodiments, the detection circuit 120 includes a fifth node N5, a first detection transistor T8, and a second detection transistor T9. Furthermore, the first detection transistor T8 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the first detection transistor T8). The first terminal of the first detection transistor T8 is coupled to the fifth node N5. The second terminal of the first detection transistor T8 is coupled to the first node N1 of the pixel circuit 110. The control terminal of the first detection transistor T8 is configured to receive a drive signal EM(n). The first detection transistor T8 is turned on in response to the drive signal EM(n).

[0083] Furthermore, the second detection transistor T9 includes a first terminal, a second terminal, and a control terminal (i.e., the gate terminal of the second detection transistor T9). The first terminal of the second detection transistor T9 is coupled to the data line DL. The second terminal of the second detection transistor T9 is coupled to the first terminal of the first detection transistor T8. The control terminal of the second detection transistor T9 is configured to receive a detection control signal AT. The second detection transistor is turned on in response to the detection control signal AT.

[0084] Figure 2 According to some embodiments of the present invention Figure 1 Schematic diagram of the signal timing of the pixel detection device 100. In some embodiments, Figure 1 The operation of the pixel detection device 100 is easy to understand, please refer to Figure 2 In the first sub-phase I11 of the driving phase I1, the reset circuit 111 resets the third node N3 and the fourth node N4 to the second reference voltage of the second reference voltage source Vref2 according to the reset signal SN(n-1), thereby resetting the first node N1 and the second node N2 through the driving transistor DT1.

[0085] Next, the compensation circuit 112 is turned on according to the compensation signal SN(n) in the second sub-phase I12 of the driving phase I1 to compensate the third node N3 .

[0086] Furthermore, the writing circuit 113 is turned on according to the writing signal SN(n+1) in the third sub-phase I13 of the driving phase I1 to write the data voltage Data of the data line DL into the third node N3 and the fourth node N4 to be stored in the first capacitor C1.

[0087] Then, during a detection phase I2, the driving transistor DT1 generates a driving current according to the data voltage Data of the first capacitor C1 to drive the light-emitting element LED. At this time, the detection circuit 120 is turned on according to the driving signal EM(n) and the detection control signal AT to detect whether the driving current of the pixel circuit 110 is normal.

[0088] It should be noted that when the pixel detection device 100 displays an image, the detection control signal AT is at a high level VGH. When the pixel detection device 100 is being detected, the detection control signal AT is at a low level VGL.

[0089] Figure 3 Schematic diagram of the circuit state of the pixel detection device 100 according to some embodiments of the present invention. Figure 2 and Figure 3 In the first sub-phase I11 of the driving phase I1, the control signal VC(n) and the reset signal SN(n-1) are both at a low level VGL. The compensation signal SN(n) and the write signal SN(n+1) are both at a high level VGH. In the first sub-phase I11 of the driving phase I1, the reset circuit 111 resets the third node N3 and the fourth node N4 to the second reference voltage of the second reference voltage source Vref2 according to the reset signal SN(n-1). This resets the first node N1 and the second node N2 to the first reference voltage of the first reference voltage source Vref1 via the driving transistor DT1.

[0090] Figure 4 Schematic diagram of the circuit state of the pixel detection device 100 according to some embodiments of the present invention. Figure 2 and Figure 4 In the second sub-phase I12 of the driving phase I1, the control signal VC(n) and the compensation signal SN(n) are both at a low level VGL. The reset signal SN(n-1) and the write signal SN(n+1) are both at a high level VGH. The compensation circuit 112 is turned on in response to the compensation signal SN(n) during the second sub-phase I12 of the driving phase I1 to compensate the third node N3.

[0091] In some embodiments, since the driving transistor DT1 is turned on according to the second reference voltage of the third node N3 , the first reference voltage of the first reference voltage source Vref1 compensates the first reference voltage of the first reference voltage source Vref1 at the third node N3 through the first transistor T1 and the driving transistor DT1 .

[0092] In some embodiments, a voltage value of the first reference voltage of the first reference voltage source Vref1 is greater than or equal to a system high voltage of the system high voltage source VDD.

[0093] Figure 5 Schematic diagram of the circuit state of the pixel detection device 100 according to some embodiments of the present invention. Figure 2 and Figure 4 During the third sub-phase I13 of the driving phase I1, the control signal VC(n) and the write signal SN(n+1) are both at a low level VGL. The reset signal SN(n-1) and the compensation signal SN(n) are both at a high level VGH. During the third sub-phase I13 of the driving phase I1, the write circuit 113 is turned on in response to the write signal SN(n+1) to write the data voltage Data of the data line DL to the third node N3 and the fourth node N4, thereby storing the data voltage Data on the data line DL in the first capacitor C1.

[0094] In some embodiments, the data voltage Data is a grayscale voltage for controlling the grayscale of the screen. In some embodiments, the grayscale of the screen ranges from level 0 to level 255. There are 256 grayscale voltages.

[0095] Figure 6 is a flowchart of the steps of a pixel detection method 200 according to some embodiments of the present invention. In some embodiments, the pixel detection method 200 may be Figure 1 The pixel detection device 100 shown in FIG. Figure 6 The operation of the pixel detection method 200 is easy to understand, please refer to Figures 7 to 9 . Figures 7 to 9 is a circuit state diagram of a pixel detection device according to some embodiments of the present invention, corresponding to Figure 1 Pixel detection device 100.

[0096] In step 210 , a first detection signal is input to the pixel circuit via a system low voltage source in a first stage.

[0097] In some embodiments, see Figure 2 、 Figure 6 and Figure 7 , compared to Figure 1 The pixel detection device 100, Figure 7 The pixel detection device 100 is a schematic diagram of the circuit state before the mass transfer technology stage. In short, Figure 7 The pixel detection device 100 has not yet been installed with the light-emitting element LED (i.e., at position P1). In the detection phase I2 before the mass transfer technology phase, the drive signal EM(n) and the detection control signal AT are both at a low level VGL. The detection circuit 120, together with the system low voltage source VSS and a signal line (e.g., data line DL), forms a first detection loop AT1. During this phase, the first detection signal is input to the pixel circuit 110 via the system low voltage source VSS.

[0098] It should be noted that mass transfer technology involves performing a thin-film transfer process after the epitaxial growth process for LED light-emitting devices. This process transfers millions of micron-sized LED light-emitting devices to each pixel in the pixel array of the display panel (i.e., the pixel detection device 100). In some embodiments, the LED light-emitting devices include microlight-emitting diodes (MLDs).

[0099] It is further explained that Figure 2 The embodiments are before the mass transfer technology stage, after the mass transfer technology stage and Figure 1 Detection signal timing diagram of the pixel detection device 100 before leaving the factory.

[0100] In step 220 , in a first stage, a first detection signal is received via a detection circuit and a signal line, so as to determine whether the pixel circuit is abnormal according to the first detection signal.

[0101] In some embodiments, see Figure 2 、 Figure 6 and Figure 7 In the detection phase I2 before the mass transfer technology phase, the driving signal EM(n) and the detection control signal AT are both at a low level VGL. The detection circuit 120 and the signal line (e.g., the data line DL) receive the first detection signal via the first detection loop AT1, thereby determining whether the pixel circuit 110 is abnormal based on the first detection signal.

[0102] In some embodiments, a processor (not shown) of the pixel detection device 100 determines whether the current range of the first detection signal is within a preset range, thereby determining whether the pixel circuit 110 is abnormal.

[0103] In some embodiments, the data lines DL are used to position the pixel detection device 100 (ie, pixels) in the horizontal direction, and the signal lines transmitting the driving signals EM(n) are used to position the pixel detection device 100 in the vertical direction.

[0104] In step 230 , a second detection signal is input to the pixel circuit via the first reference voltage source in the second phase.

[0105] In some embodiments, see Figure 2 、 Figure 6 and Figure 8 The detection circuit 120, the first reference voltage source Vref1, the system low voltage source VSS, the pixel circuit 110, and the signal line (eg, the data line DL) form a second detection loop AT2. The second detection loop AT2 includes a first detection sub-loop AT21 and a second detection sub-loop AT22.

[0106] In the driving phase I1 after the mass transfer technology phase, the control signal VC(n) and the detection control signal AT are both at a low level VGL. The driving signal is at a high level VGH. The second detection signal is input to the node N1 of the pixel circuit 110 via the first reference voltage source Vref1 along the first detection sub-loop AT21.

[0107] In step 240 , in the second stage, a second detection signal is received via the detection circuit and the signal line, so as to determine whether the pixel circuit is abnormal according to the second detection signal.

[0108] In some embodiments, see Figure 2 、 Figure 6 and Figure 8 Following step 230, in the detection phase I2 after the mass transfer technology phase, the driving signal EM(n) and the detection control signal AT are both at a low level VGL. The control signal VC(n) is at a high level VGH. By controlling the voltage of the system low voltage source VSS, the second detection signal at the node N1 of the pixel circuit 110 in the driving phase I1 is guided along the second detection sub-loop AT22 to the detection circuit 120 and the signal line (e.g., the data line DL). The second detection signal is received by the detection circuit 120 and the signal line (e.g., the data line DL), and the pixel circuit 110 is determined to be abnormal based on the second detection signal.

[0109] In some embodiments, a processor (not shown) of the pixel detection device 100 determines whether the current range of the second detection signal is within a preset range, thereby determining whether the pixel circuit 110 is abnormal.

[0110] In step 250 , in the third phase, a third detection signal is input to the light-emitting element of the pixel circuit via the system high voltage source.

[0111] In some embodiments, see Figure 2 、 Figure 6 and Figure 9In the detection phase I2 before and after the mass transfer technology phase, the detection circuit 120 forms a third detection loop AT3 with the system high voltage source VDD, the light-emitting element LED, and the signal line (e.g., the data line DL), and inputs a third detection signal to the light-emitting element LED of the pixel circuit 110 via the system high voltage source VDD.

[0112] In step 260 , in the third stage, a third detection signal is received via the detection circuit and the signal line, so as to determine whether the light emitting element is abnormal according to the third detection signal.

[0113] In some embodiments, see Figure 2 、 Figure 6 and Figure 9 During the detection phase I2 before and after the mass transfer technology phase, the driving signal EM(n) and the detection control signal AT are both at a low level VGL. The detection circuit 120 and a signal line (e.g., data line DL) receive a third detection signal from the third detection loop AT3 to determine whether the light-emitting element LED is abnormal.

[0114] In some embodiments, a processor (not shown) of the pixel detection device 100 determines whether the current range of the third detection signal is within a preset range, thereby determining whether the light-emitting element LED of the pixel circuit 110 is abnormal.

[0115] It should be noted that the light-emitting elements LEDs will be checked for abnormalities before and after the mass transfer technology stage.

[0116] In some embodiments, the driving transistor DT1 and the transistors T1 to T9 are P-type metal-oxide-semiconductor field-effect transistors (PMOS).

[0117] In some embodiments, the driving transistor DT1 and the transistors T1 to T9 are N-type metal-oxide-semiconductor field-effect transistors (PMOS).

[0118] Figure 10 is a schematic diagram of a pixel detection device 300 according to some embodiments of the present invention. In some embodiments, Figure 10As shown, the pixel detection device 300 includes a signal line L1, a pixel circuit 310, and a detection circuit 320. The pixel circuit 310 is coupled to a system high voltage source VDD, a system low voltage source VSS, a first reference voltage source Vref1, and a second reference voltage source Vref2. The detection circuit 320 is coupled to the signal line L1, the pixel circuit 310, and the first reference voltage source Vref1.

[0119] In some embodiments, the detection circuit 320 is configured to receive the first drive signal SN2(n) and the detection control signal AT. The detection circuit 320, together with the first reference voltage source Vref1, the pixel circuit 310, and the signal line L1, forms a first detection loop (not shown) to detect whether the pixel circuit 310 is abnormal in the first phase based on the first drive signal SN2(n) and the detection control signal AT.

[0120] Next, the detection circuit 320, the system low voltage source VSS, the pixel circuit 310 and the signal line L1 form a second detection loop (not shown) to detect whether the pixel circuit 310 is abnormal according to the first driving signal SN2 (n) and the detection control signal AT in the second stage.

[0121] Furthermore, the detection circuit 320, the system high voltage source VDD, the light emitting element LED and the signal line L1 form a third detection loop (not shown) to detect whether the light emitting element LED is abnormal according to the first driving signal SN2 (n) and the detection control signal AT in the third stage.

[0122] It should be noted that compared with Figure 1 An embodiment of Figure 10 Examples and Figure 1 A first difference of the embodiment is that the first detection transistor T8 of the detection circuit 320 and the node N2 of the pixel circuit 310 and the second detection transistor T9 of the detection circuit 320 are coupled to the first reference voltage source Vref1.

[0123] then, Figure 10 Examples and Figure 1 The second difference of the embodiment is that the control terminal of the first detection transistor T8 of the detection circuit 320 is used to receive the first driving signal SN2(n). Figure 10 Examples and Figure 1 The third difference of the embodiment is that the first detection transistor T8 of the detection circuit 320 is coupled to the signal line L1. The rest of the structure and operation are the same as Figure 1 The pixel detection device 100 is the same as that of FIG. 1 and will not be described in detail here.

[0124] In some embodiments, the pixel circuit 310 includes a reset circuit 311, a compensation circuit 312, and a write circuit 313. The remaining structures and operations are similar to those of FIG. Figure 1The pixel detection device 100 is the same as that of FIG. 1 and will not be described in detail here.

[0125] For further explanation, see Figure 10 The signal line L1 is different from the data line DL. During detection, the signal line L1 is used to receive a detection signal and transmit the detection signal to a processor or a driver integrated circuit (not shown) of the pixel detection device 100.

[0126] In some embodiments, the signal line L1 is used to position the pixel detection device 100 (ie, pixel) in the horizontal direction, and the signal line transmitting the first driving signal SN2 (n) is used to position the pixel detection device 300 in the vertical direction.

[0127] In some embodiments, signal line L1 may be a data line DL. During detection, data line DL1 receives a detection signal and transmits the detection signal to a processor or driver integrated circuit (not shown) of pixel detection device 100. During display, data line DL1 receives a data voltage Data from the left side of pixel detection device 100.

[0128] Figure 11 FIG. 1 is a signal timing diagram of the pixel detection device 300 according to some embodiments of the present invention. Figure 2 An embodiment of Figure 11 Examples and Figure 2 The first difference of the embodiment is that the first driving signal SN2(n) is added. Figure 11 Examples and Figure 2 The second difference of the embodiment is that the driving signal EM(n) is at the high level VGH in the detection phase I2.

[0129] Figure 12 Schematic diagram of the circuit state of the pixel detection device 300 according to some embodiments of the present invention. Figure 11 and Figure 12 Before the detection phase I2, the pixel detection device 300 will execute the driving phase I1, and the detailed execution method is the same as Figures 3 to 5 The pixel detection device 100 is the same as that of FIG. 1 and will not be described in detail here. Figure 12 The embodiment of the pixel detection device 300 is to perform mass transfer technology (ie, no pixel is installed at position P1). Figure 10 Schematic diagram of the circuit status before and after the light-emitting element (LED) stage.

[0130] In some embodiments, during the detection phase I2 before and after the mass transfer technology phase, the detection control signal AT is at a low level VGL. The drive signal EM(n) is at a high level VGH. The first drive signal SN2(n) is at a low level VGL and at a high level VGH at all other times. The signal line L1 is used to receive the first detection signal from the detection circuit AT4. During the detection phase I2 before and after the mass transfer technology phase, the pixel circuit 310 is detected based on the first drive signal SN2(n) and the detection control signal AT to determine if there is an abnormality.

[0131] Figure 13 FIG. 1 is a signal timing diagram of the pixel detection device 300 according to some embodiments of the present invention. Figure 11 An embodiment of Figure 13 Examples and Figure 11 The difference between the embodiment of FIG. 1 and FIG. 2 is that the driving signal EM(n) is at the low level VGL and the detection control signal AT is at the high level VGH in the detection phase I2.

[0132] Figure 14 Schematic diagram of the circuit state of the pixel detection device 300 according to some embodiments of the present invention. Figure 13 and Figure 14 Before the detection phase I2, the pixel detection device 300 will execute the driving phase I1, and the detailed execution method is the same as Figures 3 to 5 The pixel detection device 100 is the same as that of FIG. 1 and will not be described in detail here. Figure 12 The embodiment of the pixel detection device 300 is to perform mass transfer technology (ie, no pixel is installed at position P1). Figure 10 Schematic diagram of the circuit status before and after the light-emitting element (LED) stage.

[0133] In some embodiments, during the detection phase I2 before and after the mass transfer technology phase, the drive signal EM(n) is at a low level VGL. The detection control signal AT is at a high level VGH. The first drive signal SN2(n) is at a low level VGL and at a high level VGH at all other times. The signal line L1 is used to receive the second detection signal from the detection circuit AT5. During the detection phase I2 before and after the mass transfer technology phase, the pixel circuit 310 is detected based on the first drive signal SN2(n) and the drive signal EM(n) to determine if there is an abnormality.

[0134] Figure 15 FIG. 1 is a signal timing diagram of the pixel detection device 300 according to some embodiments of the present invention. Figure 11 An embodiment of Figure 13 Examples and Figure 11 The difference between the embodiment of FIG. 1 and FIG. 2 is that the driving signal EM(n) and the detection control signal AT are both at the high level VGH in the detection phase I2.

[0135] Figure 16 Schematic diagram of the circuit state of the pixel detection device 300 according to some embodiments of the present invention. Figure 15 and Figure 16 Before the detection phase I2, the pixel detection device 300 will execute the driving phase I1, and the detailed execution method is the same as Figures 3 to 5 The pixel detection device 100 is the same as that of FIG. 1 and will not be described in detail here. Figure 16 The embodiment is a schematic diagram of the circuit state of the pixel detection device 300 before and after the mass transfer technology (ie, installing the light-emitting element LED) stage.

[0136] In some embodiments, during the detection phase I2 before and after the mass transfer technology phase, the drive signal EM(n) and the detection control signal AT are both at a high level VGH. The first drive signal SN2(n) is at a low level VGL, and at a high level VGH at all other times. Signal line L1 is used to receive a second detection signal from detection circuit AT6. During the detection phase I2 before and after the mass transfer technology phase, the first drive signal SN2(n) is used to detect whether the light-emitting element LED of pixel circuit 310 is abnormal based on the first drive signal SN2(n). It should be noted that detection circuit AT6 can also be used to detect an external compensation voltage.

[0137] In some embodiments, the pixel detection device 100 is applied to a spliced ​​display and a car display and has the function of detecting pixels. In some embodiments, the pixel detection device 300 is applied to a spliced ​​display and a car display and has the function of detecting pixels and externally compensating pixels.

[0138] According to the aforementioned embodiments, the present invention provides a pixel detection device and a pixel detection method. By utilizing the circuit design of the pixel detection device, the pixel circuit, light-emitting element, or external compensation can be detected during the manufacturing process. By reducing the number of elements between the system high voltage source and the system low voltage source, the power consumption of the pixel detection device during display is reduced.

[0139] Although the present invention is disclosed above with detailed embodiments, it does not exclude other feasible implementations. Therefore, the scope of protection of the present invention shall be determined by the appended claims and not be limited by the aforementioned embodiments.

[0140] It is obvious to those skilled in the art that various modifications and alterations can be made to the present invention without departing from the spirit and scope of the present invention. Based on the aforementioned embodiments, all modifications and alterations made to the present invention are also included in the scope of protection of the present invention.

Claims

1. A pixel detection device, comprising: a data cable; a pixel circuit coupled to a system high voltage source, a system low voltage source, and a first reference voltage source; and A detection circuit is coupled to the data line and the pixel circuit and is used to receive a drive signal and a detection control signal, wherein the detection circuit, the system low voltage source, and the data line form a first detection loop, thereby detecting whether the pixel circuit is abnormal according to the drive signal and the detection control signal in a first stage, wherein the detection circuit, the first reference voltage source, the system low voltage source, the pixel circuit, and the data line form a second detection loop, thereby detecting whether the pixel circuit is abnormal according to the drive signal and the detection control signal in a second stage.

2. The pixel detection device as claimed in claim 1 , wherein the pixel circuit comprises: a first node; a second node; a third node; a fourth node; and a light-emitting element configured to emit light according to a driving current of the pixel circuit, wherein the light-emitting element comprises: a first terminal coupled to the system high voltage source; and A second end is coupled to the first node.

3. The pixel detection device as claimed in claim 2 , wherein the detection circuit, the system high voltage source, the light-emitting element and the data line form a third detection loop, so as to detect whether the light-emitting element is abnormal according to the driving signal and the detection control signal in a third stage.

4. The pixel detection device as claimed in claim 2 , wherein the pixel circuit further comprises: A driving transistor comprising: a first end coupled to the first node; a second terminal coupled to the second node; and a control terminal coupled to the third node and configured to drive the light-emitting element according to a voltage level of the third node, wherein the first node, the second node, and the third node are not the same point; a first transistor comprising: a first terminal coupled to the first reference voltage source and configured to receive a first reference voltage from the first reference voltage source; a second terminal coupled to the first node; and a control terminal for receiving a control signal, wherein the first transistor is turned on in response to the control signal; and a second transistor comprising: a first terminal coupled to the driving transistor; a second terminal coupled to the system low voltage source; and A control terminal is used to receive the driving signal, wherein the second transistor is turned on in response to the driving signal.

5. The pixel detection device as claimed in claim 4 , wherein the pixel circuit further comprises: a reset circuit coupled to the third node, the fourth node, and a second reference voltage source, and configured to reset the third node to a second reference voltage of the second reference voltage source, thereby resetting the first node and the second node through the driving transistor, wherein the reset circuit comprises: a third transistor comprising: a first end coupled to the third node; a second terminal coupled to the second reference voltage source; and a control terminal for receiving a reset signal, wherein the third transistor resets the third node in response to the reset signal; and a fourth transistor comprising: a first end coupled to the fourth node; a second terminal coupled to the second reference voltage source; and A control terminal is used to receive the reset signal, wherein the fourth transistor is turned on in response to the reset signal.

6. The pixel detection device as claimed in claim 5 , wherein the pixel circuit further comprises: a compensation circuit coupled to the second node, the third node, the fourth node, and the reset circuit, and configured to compensate for the first reference voltage from the third node to the first reference voltage source, wherein the compensation circuit comprises: a fifth transistor comprising: a first terminal coupled to the second node; a second terminal coupled to the third node; and a control terminal for receiving a compensation signal, wherein the fifth transistor is turned on in response to the compensation signal; and a sixth transistor comprising: a first end coupled to the fourth node; a second terminal coupled to the second reference voltage source; and A control terminal is used to receive the compensation signal, wherein the sixth transistor is turned on in response to the compensation signal.

7. The pixel detection device as claimed in claim 6, wherein the pixel circuit further comprises: a write circuit coupled to the fourth node and the data line and configured to receive a data voltage of the data line to write data into the third node and the fourth node, wherein the write circuit comprises: a seventh transistor comprising: a first end coupled to the fourth node; a second end coupled to the data line; and A control terminal is used to receive a write signal, wherein the seventh transistor is turned on in response to the write signal.

8. The pixel detection device as claimed in claim 2, wherein the detection circuit comprises: a fifth node; a first detection transistor comprising: a first end coupled to the fifth node; a second terminal coupled to the first node of the pixel circuit; and a control terminal for receiving the driving signal, wherein the first detection transistor is turned on in response to the driving signal; and a second detection transistor comprising: a first end coupled to the data line; a second terminal coupled to the first terminal of the first detection transistor; and A control terminal is used to receive the detection control signal, wherein the second detection transistor is turned on in response to the detection control signal.

9. A pixel detection device comprising: a signal line; a pixel circuit coupled to a system high voltage source, a system low voltage source, and a first reference voltage source; and A detection circuit is coupled to the signal line, the pixel circuit and the first reference voltage source, and is used to receive a first drive signal and a detection control signal, wherein the detection circuit, the first reference voltage source, the pixel circuit and the signal line form a first detection loop, thereby detecting whether the pixel circuit is abnormal according to the first drive signal and the detection control signal in a first stage, wherein the detection circuit, the system low voltage source, the pixel circuit and the signal line form a second detection loop, thereby detecting whether the pixel circuit is abnormal according to the first drive signal in a second stage.

10. The pixel detection device as claimed in claim 9, wherein the pixel circuit comprises: a first node; a second node; a third node; a fourth node; and a light-emitting element configured to emit light according to a driving current of the pixel circuit, wherein the light-emitting element comprises: a first terminal coupled to the system high voltage source; and A second end is coupled to the first node.

11. The pixel detection device as claimed in claim 10, wherein the detection circuit, the system high voltage source, the light emitting element and the signal line form a third detection loop, so as to detect whether the light emitting element is abnormal according to the first driving signal in a third stage.

12. A pixel detection device as described in claim 9, wherein the signal line is used to receive a first detection signal from the first detection circuit, thereby detecting whether the pixel circuit is abnormal according to the first drive signal and the detection control signal in the first stage, and is used to receive a second detection signal from the second detection circuit, thereby detecting whether the pixel circuit is abnormal according to the first drive signal in the second stage.

13. The pixel detection device as claimed in claim 10, wherein the pixel circuit further comprises: A driving transistor comprising: a first end coupled to the first node; a second terminal coupled to the second node; and a control terminal coupled to the third node and configured to drive the light-emitting element according to a voltage level of the third node, wherein the first node, the second node, and the third node are not the same point; a first transistor comprising: a first terminal coupled to the first reference voltage source and configured to receive a first reference voltage from the first reference voltage source; a second terminal coupled to the first node; and a control terminal for receiving a control signal, wherein the first transistor is turned on in response to the control signal; and a second transistor comprising: a first terminal coupled to the driving transistor; a second terminal coupled to the system low voltage source; and A control terminal is used to receive a second driving signal, wherein the second transistor is turned on in response to the second driving signal.

14. The pixel detection device as claimed in claim 13, wherein the pixel circuit further comprises: a reset circuit coupled to the third node and a second reference voltage source, and configured to reset the third node to a second reference voltage of the second reference voltage source, thereby resetting the first node and the second node through the driving transistor, wherein the reset circuit comprises: a third transistor comprising: a first end coupled to the third node; a second terminal coupled to the second reference voltage source; and a control terminal for receiving a reset signal, wherein the third transistor resets the third node in response to the reset signal; and a fourth transistor comprising: a first end coupled to the fourth node; a second terminal coupled to the second reference voltage source; and A control terminal is used to receive the reset signal, wherein the fourth transistor is turned on in response to the reset signal.

15. The pixel detection device as claimed in claim 14, wherein the pixel circuit further comprises: a compensation circuit coupled to the second node, the third node, and the reset circuit, and configured to receive a compensation signal and be turned on according to the compensation signal to compensate the third node, wherein the compensation circuit comprises: a fifth transistor comprising: a first terminal coupled to the second node; a second terminal coupled to the third node; and a control terminal for receiving the compensation signal, wherein the fifth transistor is turned on in response to the compensation signal; and a sixth transistor comprising: a first end coupled to the fourth node; a second terminal coupled to the second reference voltage source; and A control terminal is used to receive the compensation signal, wherein the sixth transistor is turned on in response to the compensation signal.

16. The pixel detection device as claimed in claim 15, wherein the pixel circuit further comprises: a write circuit coupled to the fourth node and a data line, and configured to receive a data voltage of the data line to write data into the third node and the fourth node, wherein the write circuit comprises: a seventh transistor comprising: a first end coupled to the fourth node; a second end coupled to the data line; and A control terminal is used to receive a write signal, wherein the seventh transistor is turned on in response to the write signal. The pixel detection device as claimed in claim 16 , wherein the signal line is different from the data line.

18. The pixel detection device as claimed in claim 10, wherein the detection circuit comprises: a first detection transistor comprising: a first end coupled to the signal line; a second terminal coupled to the second node; and a control terminal for receiving the first driving signal, wherein the first detecting transistor is turned on in response to the first driving signal; as well as a second detection transistor comprising: a first terminal coupled to the first reference voltage source; a second terminal coupled to the first node; as well as A control terminal is used to receive the detection control signal, wherein the second detection transistor is turned on in response to the detection control signal.

19. A pixel detection method, applicable to a pixel detection device, wherein the pixel detection device comprises a signal line, a pixel circuit, and a detection circuit, wherein the pixel circuit is coupled to a system high voltage source, a system low voltage source, and a first reference voltage source, wherein the detection circuit is coupled to the signal line and the pixel circuit, wherein the pixel detection method comprises: In a first phase, a first detection signal is input to the pixel circuit via the first reference voltage source; In the first stage, the first detection signal is received by the detection circuit and the signal line, so as to determine whether the pixel circuit is abnormal according to the first detection signal; In a second phase, a second detection signal is input to the pixel circuit via the system low voltage source; and In the second stage, the second detection signal is received by the detection circuit and the signal line, so as to determine whether the pixel circuit is abnormal according to the second detection signal.

20. The pixel detection method of claim 19, wherein the pixel circuit comprises a light emitting element, the light emitting element being coupled between the system high voltage source and the system low voltage source, wherein the pixel detection method further comprises: In a third phase, a third detection signal is input to the light-emitting element of the pixel circuit via the system high voltage source; and In the third stage, the third detection signal is received by the detection circuit and the signal line, so as to determine whether the light emitting element is abnormal according to the third detection signal.

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