An MLVDS receiver circuit based on BiCMOS technology

Abstract

This invention relates to an MLVDS receiver circuit based on BiCMOS technology, comprising a common-mode converter circuit, a pre-amplifier circuit, type 1 and type 2 control circuits, a hysteresis comparator circuit, and a differential-to-single-ended converter circuit. The common-mode converter circuit compresses the input signal with a wide common-mode range; the pre-amplifier circuit identifies and amplifies the compressed differential signal; the type 1 and type 2 control circuits control the operating mode of the MLVDS receiver; the hysteresis comparator introduces hysteresis while amplifying the differential signal, suppressing differential noise and providing anti-interference capability; the differential-to-single-ended converter circuit converts the differential signal to a single-ended signal. This invention provides an MLVDS receiver circuit based on BiCMOS technology. This circuit, implemented using BiCMOS technology, can achieve a wide common-mode range input through a resistor divider network, and simultaneously implements both type 1 and type 2 operating modes, meeting the requirements of the MLVDS standard.

Description

Technical Field

[0001] This invention relates to an MLVDS receiver circuit, and more particularly to a receiver circuit implemented based on BiCMOS technology, belonging to the field of high-speed interface circuit design. Background Technology

[0002] LVDS, through the use of low-swing differential signaling technology, enables high-speed signal transmission over differential PCB lines or balanced twisted-pair cables. Its advantages, including strong anti-interference capabilities, low power consumption, high reliability, and fast transmission rates, have led to its widespread application in point-to-point data transmission. However, LVDS is not suitable for multi-point bus applications. To meet the communication needs between multi-point systems, MLVDS technology was developed based on LVDS.

[0003] To adapt to bus applications, the MLVDS protocol requires the receiver to receive signals in a common-mode range of -1.4V to 3.8V. This voltage range exceeds the normal operating range of MOSFETs or BJTs. Therefore, a corresponding voltage divider network must be designed to convert the voltage of -1.4V to 3.8V into a voltage range that the internal circuit can recognize.

[0004] The MLVDS protocol requires the receiver to have two operating modes. The type 1 mode is the standard operating mode, which can distinguish differential voltages with a differential threshold greater than 50mV. The type 2 mode has a 100mV offset from the type 1 mode and can realize the failure protection function of the MLVDS receiver. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an MLVDS receiver circuit based on BiCMOS technology. This circuit can compress a wide common-mode voltage range to a range recognizable by the internal circuitry, and the type1 and type2 control circuits can control the receiver's operating mode.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] An MLVDS receiver circuit based on BiCMOS technology includes a common-mode converter circuit, a pre-amplifier circuit, type 1 and type 2 control circuits, a hysteresis comparator circuit, and a differential-to-single-ended converter circuit.

[0008] Common-mode converter circuit: Compresses differential input signals with a wide common-mode range so that they can be recognized by the pre-amplifier circuit;

[0009] Pre-amplifier circuit: Identifies the differential signal after compression in the previous stage and amplifies the amplitude of the compressed differential signal to the amplitude before compression;

[0010] Type 1 and Type 2 control circuits: Differential signal offset is achieved by controlling the internal selector, thereby controlling the operating mode of the MLVDS receiver;

[0011] Hysteresis comparator circuit: Differential mode noise is suppressed by introducing hysteresis;

[0012] Differential to single-ended circuit: converts differential signals to single-ended signals to achieve signal output.

[0013] Furthermore, the common-mode converter circuit includes resistors R1, R2, and R3, and capacitors C1, C2, and C3; one end of resistor R1, one end of resistor R2, and one end of resistor R3 are connected together as the output terminal OUT of the common-mode converter circuit; the other end of resistor R1 is connected to the input signal IN, the other end of resistor R2 is connected to the power supply VDD, and the other end of resistor R3 is grounded; capacitors C1, C2, and C3 are connected in parallel with resistors R1, R2, and R3, respectively.

[0014] Furthermore, R1, R2, and R3 are all kΩ level resistors, and R2:R3:R1 = 1:2:3.

[0015] Furthermore, the output voltage V after common-mode conversion O :

[0016]

[0017] Among them, V I Input voltage, V DD This refers to the voltage of the power supply VDD.

[0018] Furthermore, the pre-amplification circuit includes resistors R4, R5, R6, and NPN transistors Q1, Q2, and Q3;

[0019] One end of resistor R4 is connected to the power supply VDD, and the other end is connected to the collector of Q1. The base of Q1 is connected to the input signal IN+, and the emitter is connected to both the collector of transistor Q3 and the emitter of Q2. One end of resistor R5 is connected to the power supply VDD, and the other end is connected to the collector of Q2. The base of Q2 is connected to the input signal IN-. The base of Q3 is connected to the bias voltage Vb, and the emitter is grounded through resistor R6.

[0020] Furthermore, the type1 and type2 control circuits include resistors R7, R8, R9, R10, NPN transistors Q4, Q5, Q6, Q7, and selectors MUX1 and MUX2;

[0021] The collector of Q4 is connected to power supply VDD, the base is connected to the output signal of the preamp, and the emitter is connected to one end of resistor R7 and channel 0 of selector MUX1. The collector of Q5 is connected to power supply VDD, the base is connected to the output signal of the preamp, and the emitter is connected to one end of resistor R8 and channel 0 of selector MUX2. The other end of resistor R7 is connected to the collector of Q6 and channel 1 of selector MUX1. The other end of resistor R8 is connected to the collector of Q7 and channel 1 of selector MUX2. The emitters of Q6 and Q7 are grounded through resistors R9 and R10 respectively, and the bases of Q6 and Q7 are connected together and connected to the reference voltage Vc.

[0022] Furthermore, in type 1 operating mode, both selectors MUX1 and MUX2 select channel 0. In this mode, the type 1 and type 2 control circuits are symmetrical common-collector amplifiers, only performing level shifting. VP -V VM =V diff ;

[0023] Among them, V VP This refers to the voltage V of the output VP of selector MUX2. VM This refers to the voltage, V of the output VM of selector MUX1. diff This refers to the pressure difference;

[0024] In type 2 operating mode, selector MUX1 selects channel 0, and selector MUX1 selects channel 1. Under the same conditions, there is a voltage difference between the VP voltage in type 2 mode and the VP voltage in type 1 mode. The voltage difference is the voltage drop V across resistor R8. R8 ,Right now:

[0025] V VP -V VM =V diff -V R8 ,

[0026] Differential level from type 1 mode V diff The change is V diff -V R8 This achieves the requirement of MLVDS receiver to detect threshold offset.

[0027] Furthermore, R7 = R8, R9 = R10.

[0028] Furthermore, the hysteresis comparator circuit includes resistors R11, R12, R13, R14, R15, R16, R17, and R18, and NPN transistors Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16.

[0029] Resistors R11, R12, R13 and bipolar transistors Q8 and Q9 form a differential comparator; resistors R14, R15, R16, R17 and bipolar transistors Q11, Q12, Q13, Q14 form a common-collector amplifier; and resistor R18 and bipolar transistors Q15, Q16, Q17 form a positive feedback path.

[0030] Furthermore, the differential-to-single-ended circuit includes PMOS transistors P1, P2, P3, and P4, and NMOS transistors N1, N2, N3, and N4;

[0031] The sources of PMOS transistors P1, P2, P3, and P4 are all connected to the power supply VDD. The gate of P1 is connected to the drain of P1, the gate of P3, and the drain of NMOS transistor N1. The gate of P2 is connected to the drain of P2, the gate of P4, and the drain of N2. The source of N1 is grounded, and its gate is connected to the input signal VP. The source of N2 is grounded, and its gate is connected to the input signal VM.

[0032] The drain of P3 is connected to both the drain and source of N3; the drain of P4 is connected to both the drain of N4 and the output Vout; the sources of N3 and N4 are grounded.

[0033] Compared with existing MLVDS receivers, the present invention has the following advantages:

[0034] (1) The common-mode converter circuit of the present invention is based on the principle of resistor voltage division, which has the advantages of simple circuit structure and strong portability.

[0035] (2) The pre-amplifier circuit of the present invention can amplify the compressed differential signal, and the amplitude of the differential signal is consistent with the input signal. The common mode shift of the input signal is achieved by the resistor voltage divider network and the amplifier, and the amplitude of the differential signal remains unchanged.

[0036] (3) The present invention can realize the differential signal to generate a 100mV offset in the circuit through the type1 and type2 control circuits, thereby realizing the MLVDS circuit failure protection function.

[0037] (4) The present invention introduces a positive feedback comparator to achieve receiver hysteresis effect and improve the anti-interference capability of MLVDS receiver. Attached Figure Description

[0038] Figure 1 This is a block diagram of the circuit structure.

[0039] Figure 2 This is a common-mode converter circuit diagram;

[0040] Figure 3 Diagram of the preamplifier and control circuits for type 1 and type 2;

[0041] Figure 4This is a circuit diagram of a hysteresis comparator;

[0042] Figure 5 This is a circuit diagram for a differential to single-ended converter. Detailed Implementation

[0043] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the scope of protection of the present invention is not limited to the following description.

[0044] like Figure 1 As shown, the present invention proposes an MLVDS receiver circuit based on BiCMOS technology, which includes a common-mode conversion circuit, a pre-amplifier circuit, type 1 and type 2 control circuits, a hysteresis comparator circuit, and a differential-to-single-ended circuit.

[0045] The common-mode converter circuit described above can compress voltages from -1.4V to 3.8V to a certain ratio, making them recognizable by the internal circuitry.

[0046] The pre-amplifier circuit can amplify the compressed differential signal, and maintain the amplitude of the differential signal consistent with the input signal after passing through the pre-amplifier circuit. The common-mode shift of the input signal is achieved through the resistor voltage divider network and the amplifier.

[0047] The type1 and type2 control circuits control the differential signal offset by controlling the internal selectors MUX1 and MUX2, thereby controlling the working mode of the MLVDS receiver.

[0048] The hysteresis comparator circuit is a positive feedback amplifier.

[0049] like Figure 2 As shown, the common-mode converter circuit includes resistors R1, R2, and R3, and capacitors C1, C2, and C3. One end of resistor R1 is connected to the input signal IN, and the other end is connected to R2 and R3; one end of resistor R2 is connected to the power supply VDD, and the other end is connected to R1 and R3; one end of resistor R3 is grounded, and the other end is connected to R1 and R2; resistor R1 is connected in parallel with capacitor C1, resistor R2 is connected in parallel with capacitor C2, and resistor R3 is connected in parallel with capacitor C3. The common-mode converter circuit only shifts the voltage. To avoid affecting the normal operation of the MLVDS receiver circuit and to prevent large leakage current, the resistance values ​​of R1, R2, and R3 should be in the kΩ range.

[0050] Preferably, let R2:R3:R1 = 1:2:3.

[0051] Voltage after common-mode conversion:

[0052]

[0053] Among them, V I Input voltage, V DDThis refers to the voltage of the power supply VDD.

[0054] like Figure 3 As shown, the pre-amplification circuit includes resistors R4, R5, and R6, and bipolar transistors Q1, Q2, and Q3 (all NPN type). One end of resistor R4 is connected to the power supply VDD, and the other end is connected to the collector of NPN transistor Q1. The collector of NPN transistor Q1 is connected to resistor R4, its base is connected to the input IN+, and its emitter is connected to both the collector of transistor Q3 and the emitter of transistor Q2. One end of resistor R5 is connected to the power supply VDD, and the other end is connected to the collector of NPN transistor Q2. The collector of NPN transistor Q2 is connected to resistor R5, its base is connected to the input IN-, and its emitter is connected to both the collector of transistor Q3 and the emitter of transistor Q1. The collector of transistor Q3 is connected to both the emitter of transistor Q1 and the emitter of transistor Q2. The base of transistor Q3 is connected to the bias voltage Vb, and the emitter of transistor Q3 is connected to resistor R6; one end of resistor R6 is connected to the emitter of transistor Q3, and the other end is grounded.

[0055] Common-mode converters compress both common-mode and differential signals. Traditional CMOS comparators have relatively low gain and are susceptible to process mismatch. Therefore, high-gain, low-mismatch BiCMOS technology is chosen as the pre-amplifier circuit. By appropriately setting the load resistor, the differential signal after pre-amplification remains consistent with the original input signal. The combination of the common-mode converter and the pre-amplifier circuit achieves the conversion of a wide common-mode range differential signal to a fixed common-mode differential signal while maintaining the amplitude of the differential signal.

[0056] like Figure 3 As shown, the type 1 and type 2 control circuits include resistors R7, R8, R9, and R10, bipolar transistors Q4, Q5, Q6, and Q7 (all NPN type), and selectors MUX1 and MUX2. The collector of transistor Q4 is connected to power supply VDD, the base of transistor Q4 is connected to the output signal of the preceding stage, and the emitter of transistor Q4 is connected to both resistor R7 and the zero terminal of selector MUX1. The collector of transistor Q5 is connected to power supply VDD, the base of transistor Q5 is connected to the output signal of the preceding stage, and the emitter of transistor Q4 is connected to both resistor R8 and the zero terminal of selector MUX2. One end of resistor R7 is connected to the emitter of transistor Q4 and the zero terminal of selector MUX1, and the other end is connected to the collector of transistor Q9 and selector MUX1. Terminal 1 of the circuit is connected to the circuit. One end of resistor R8 is connected to the emitter of transistor Q5 and terminal 0 of selector MUX2, and the other end is connected to the collector of transistor Q10 and terminal 1 of selector MUX2. The collector of transistor Q6 is connected to both resistor R7 and terminal 1 of selector MUX1. The base of transistor Q6 is connected to the base of transistor Q7, and the emitter of transistor Q6 is grounded. The collector of transistor Q7 is connected to both resistor R8 and terminal 1 of selector MUX2. The base of transistor Q7 is connected to the base of transistor Q6, and the emitter of transistor Q7 is grounded.

[0057] In type 1 operating mode, both selectors MUX1 and MUX2 select channel 0. At this time, the control circuits of type 1 and type 2 are symmetrical common-collector amplifiers, only performing level conversion functions.

[0058] V VP -V VM =V diff .

[0059] In Type 2 operating mode, the MLVDS receiver is required to have a +100mV offset in its discrimination threshold. In this mode, selector MUX1 selects channel 0. Under the same conditions, the VP voltage in Type 2 mode has a voltage difference relative to the VP voltage in Type 1 mode. This voltage difference is the voltage drop across resistor R8, i.e.:

[0060] V VP -V VM =V diff -V R8 ,

[0061] Differential level from type 1 mode V diff The change is V diff -V R8 This achieves the requirement of an offset of +100mV for the discrimination threshold of the MLVDS receiver.

[0062] like Figure 4 As shown, the hysteresis comparator circuit includes resistors R11, R12, R13, R14, R15, R16, R17, and R18, and bipolar transistors Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 (all NPN type).

[0063] Resistor R11 is connected to power supply VDD at one end and to the collectors of NPN transistors Q8 and Q15, and the base of Q11 at the other end. The collector of NPN transistor Q8 is connected to resistor R11, the collector of Q15, and the base of Q11. The base of Q8 is connected to the input terminal IN+. The emitter of Q8 is connected to the collector of transistor Q10 and the emitter of transistor Q9. Resistor R12 is connected to power supply VDD at one end and to the collectors of NPN transistors Q9 and Q16, and the base of Q12 at the other end. The collector of NPN transistor Q9 is connected to resistor R12, the collector of Q16, and the base of Q12. The base of Q8 is connected to the input terminal IN-. The emitter of Q9 is connected to the collector of transistor Q10 and the emitter of transistor Q8. The collector of Q10 is connected to the emitter of transistor Q8 and the emitter of transistor Q9. The base of transistor Q10 is connected to the bias voltage Vb, and the emitter of transistor Q10 is connected to resistor R13; one end of resistor R13 is connected to the emitter of transistor Q10, and the other end is grounded. The collector of transistor Q11 is connected to the power supply VDD, and the base of transistor Q11 is connected to resistor R11, the collector of Q15, and the collector of Q8. The emitter of transistor Q11 is connected to resistor R14 and the base of Q12. The collector of transistor Q12 is connected to the power supply VDD, and the base of transistor Q12 is connected to resistor R12, the collector of Q16, and the collector of Q9. The emitter of transistor Q12 is connected to resistor R15 and the base of Q16. The collector of Q13 is connected to resistor R14, the base of Q13 is connected to the base of Q14 and the bias voltage Vc, and the emitter of Q13 is connected to resistor R16. The collector of Q14 is connected to resistor R17, the base of Q14 is connected to the base of Q13 and the bias voltage Vc, and the emitter of Q14 is connected to resistor R17. The collector of Q15 is simultaneously connected to the collector of Q8, resistor R11, and the base of Q11. The base of Q15 is connected to the emitter of Q12 and resistor R15. The emitter of Q15 is simultaneously connected to the collector of Q17 and the emitter of Q16. The collector of Q16 is simultaneously connected to the collector of Q9, resistor R12, and the base of Q12. The base of Q16 is connected to the emitter of Q11 and resistor R14. The emitter of Q16 is simultaneously connected to the collector of Q17 and the emitter of Q15. The collector of transistor Q117 is also connected to the emitter of transistor Q15 and the emitter of transistor Q16. The base of transistor Q17 is connected to the bias voltage Vb, and the emitter of transistor Q17 is connected to resistor R18; one end of resistor R18 is connected to the emitter of transistor Q17, and the other end is grounded.

[0064] Resistors R11, R12, R13 and bipolar transistors Q8 and Q9 form a differential comparator. Resistors R14, R15, R16, R17 and bipolar transistors Q11, Q12, Q13, Q14 form a common-collector amplifier. Resistor R18 and bipolar transistors Q15, Q16, Q17 form a positive feedback path. The hysteresis comparator output VM is connected to Q16, and the output VP is connected to Q15. The differential comparator pre-amplifies the signal, while the common-collector amplifier only pre-amplifies the output signal by reducing the voltage across one PN junction, thus reducing its common-mode voltage. The positive feedback path draws current from the differential amplifier; for example, when V... IN+ >>V IN- When current is drawn from the IN+ branch, Q17 draws current, causing the output VM of the common-collector amplifier to decrease, forming a positive feedback loop. The two switching thresholds of the hysteresis comparator are symmetrical, centered at zero volts. The switching thresholds can be adjusted by changing the value of resistor R6.

[0065] like Figure 5 As shown, the hysteresis comparator circuit includes PMOS transistors P1, P2, P3, and P4, and NMOS transistors N1, N2, N3, and N4.

[0066] The source of PMOS transistor P1 is connected to the power supply VDD, and the gate of P1 is simultaneously connected to the drain of P1, the gate of P3, and the drain of N1. The source of P2 is connected to the power supply VDD, and the gate of P2 is simultaneously connected to the drain of P2, the gate of P4, and the drain of N2. The source of N1 is grounded, the gate of N1 is connected to the input signal VP, and the drain of N1 is simultaneously connected to the gate of P1, the drain of P1, and the gate of P3. The source of N2 is grounded, the gate of N2 is connected to the input signal VN, and the drain of N2 is simultaneously connected to the gate of P2, the drain of P2, and the gate of P4. The source of transistor P3 is connected to power supply VDD. The gate of transistor P3 is simultaneously connected to the drain of transistor P1, the gate of transistor P1, and the drain of transistor N1. The drain of transistor P3 is simultaneously connected to the drain and source of transistor N3. The source of transistor P4 is connected to power supply VDD. The gate of transistor P4 is simultaneously connected to the drain of transistor P2, the gate of transistor P2, and the drain of transistor N2. The drain of transistor P4 is simultaneously connected to the drain of transistor N4 and the output Vout. The drain of transistor N3 is simultaneously connected to the gate of transistor N3 and the drain of transistor P3. The source of transistor N3 is grounded. The drain of transistor N4 is simultaneously connected to the output Vout and the drain of transistor P4. The source of transistor N4 is grounded.

[0067] The present invention provides an MLVDS receiver circuit based on BiCMOS technology. This circuit is implemented using BiCMOS technology and can achieve a wide common-mode input through a resistor divider network. It can also implement two operating modes, type 1 and type 2, and meet the requirements of the MLVDS standard.

[0068] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

[0069] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A BiCMOS process based MLVDS receiver circuit, characterized by, The MLVDS receiver circuit comprises a common mode conversion circuit, a pre-amplification circuit, a type 1 and type 2 control circuit, a hysteresis comparator circuit and a differential-to-single end conversion circuit. The common mode conversion circuit is used for compressing a differential input signal with a wide common mode range, so that the differential input signal can be recognized by the pre-amplification circuit. The pre-amplification circuit is used for recognizing the compressed differential signal and amplifying the amplitude of the compressed differential signal to the amplitude before compression. The type 1 and type 2 control circuit is used for controlling the working mode of the MLVDS receiver by controlling the selection of the internal selector to realize the offset of the differential signal. The hysteresis comparator circuit is used for realizing the suppression of the differential mode noise by introducing hysteresis. The differential-to-single end conversion circuit is used for converting the differential signal into a single end signal and realizing the signal output. The common mode conversion circuit comprises resistors R1, R2 and R3, capacitors C1, C2 and C3; one end of the resistor R1, one end of the resistor R2 and one end of the resistor R3 are connected together as an output terminal OUT of the common mode conversion circuit; the other end of the resistor R1 is connected to an input signal IN, the other end of the resistor R2 is connected to a power supply VDD, and the other end of the resistor R3 is grounded; the capacitors C1, C2 and C3 are connected in parallel with the resistors R1, R2 and R3, respectively. The voltage V output after common mode conversion O : wherein V I is the input voltage, V DD refers to the voltage of the power supply VDD; The pre-amplification circuit comprises resistors R4, R5 and R6, NPN transistors Q1, Q2 and Q3. One end of the resistor R4 is connected to the power supply VDD, the other end is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to the input signal IN+, and the emitter of the transistor Q1 is connected to the collector of the transistor Q3 and the emitter of the transistor Q2; one end of the resistor R5 is connected to the power supply VDD, the other end is connected to the collector of the transistor Q2; the base of the transistor Q2 is connected to the input signal IN-; the base of the transistor Q3 is connected to a bias voltage Vb, and the emitter of the transistor Q3 is grounded through the resistor R6. The type 1 and type 2 control circuit comprises resistors R7, R8, R9 and R10, NPN transistors Q4, Q5, Q6 and Q7, selectors MUX1 and MUX2. The collector of the transistor Q4 is connected to the power supply VDD, the base of the transistor Q4 is connected to the output signal of the previous stage, and the emitter of the transistor Q4 is connected to one end of the resistor R7 and the 0 channel of the selector MUX1; the collector of the transistor Q5 is connected to the power supply VDD, the base of the transistor Q5 is connected to the output signal of the previous stage, and the emitter of the transistor Q5 is connected to one end of the resistor R8 and the 0 channel of the selector MUX2; the other end of the resistor R7 is connected to the collector of the transistor Q6 and the 1 channel of the selector MUX1; the other end of the resistor R8 is connected to the collector of the transistor Q7 and the 1 channel of the selector MUX2; the emitters of the transistors Q6 and Q7 are grounded through the resistors R9 and R10, respectively, the bases of the transistors Q6 and Q7 are connected together and connected to a reference voltage Vc. In the type 1 working mode, the selectors MUX1 and MUX2 select the 0 channel, at this time, the type 1 and type 2 control circuit is a left-right symmetrical common collector amplifier, and only realizes the level conversion function. V VP -V VM =V diff ; wherein V VP is the voltage of the output VP of the selector MUX2, V VM is the voltage of the output VM of the selector MUX1, V diff is the voltage difference; In the type2 working mode, the selector MUX1 selects the 0 channel, the selector MUX1 selects the 1 channel, and under the same conditions, the type2 mode VP voltage exists a pressure difference relative to the type1 mode VP voltage, and the pressure difference value is the voltage drop V on the resistor R8 R8 That is: V VP -V VM =V diff -V R8 , The differential level changes from V diff in type 1 mode to V diff - V R8 , so as to realize the requirement of threshold offset discrimination of the MLVDS receiver. The MLVDS receiver circuit is realized based on the BiCMOS process.

2. The MLVDS receiver circuit based on BiCMOS technology according to claim 1, characterized in that: R1, R2 and R3 are kΩ level resistors, and R2:R3:R1=1:2:

3.

3. The MLVDS receiver circuit based on BiCMOS technology according to claim 1, characterized in that: R7=R8, and R9=R10.

4. The MLVDS receiver circuit based on BiCMOS technology according to claim 1, characterized in that: The hysteresis comparator circuit comprises resistors R11, R12, R13, R14, R15, R16, R17, R18, NPN transistors Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16; The resistors R11, R12, R13 and the transistors Q8, Q9 constitute a differential comparator, the resistors R14, R15, R16, R17 and the transistors Q11, Q12, Q13, Q14 constitute a common collector amplifier, and the resistor R18 and the transistors Q15, Q16, Q17 constitute a positive feedback path.

5. The MLVDS receiver circuit based on BiCMOS technology according to claim 1, characterized in that: The differential-to-single-ended circuit comprises PMOS transistors P1, P2, P3, P4 and NMOS transistors N1, N2, N3, N4. The sources of the PMOS transistors P1, P2, P3, P4 are connected to a power supply VDD, the gate of P1 is connected to the drain of P1, the gate of P3 and the drain of NMOS transistor N1, the gate of P2 is connected to the drain of P2, the gate of P4 and the drain of N2, the source of N1 is connected to ground, and the gate of N1 is connected to an input signal VP; the source of N2 is connected to ground, and the gate of N2 is connected to an input signal VM; The drain of P3 is connected to the drain of N3 and the source of N3, the drain of P4 is connected to the drain of N4 and the output Vout, and the sources of N3 and N4 are connected to ground.

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