A Visible Light Ethernet Rate-Adjustable Communication Method and System Based on FPGA

Abstract

This invention discloses an FPGA-based visible light Ethernet rate-adjustable communication method and system, relating to the field of visible light communication equipment technology. It includes: an off-chip PHY chip, a MAC core, and an FPGA rate conversion and flow control module connected sequentially. The FPGA rate conversion and flow control module is connected to both an FPGA transmit control module and an FPGA receive control module. The FPGA transmit control module and the FPGA receive control module are connected to transceiver circuits, which are then connected to an LED and a photodiode, respectively. This invention addresses the need for visible light-Ethernet communication interface conversion, deeply integrating visible light communication with Ethernet access technology, while simultaneously solving the problem of the traditional single rate of visible light Ethernet, thus broadening the application scenarios of visible light communication.

Description

Technical Field

[0001] This invention relates to the field of visible light communication equipment technology, and in particular to a visible light Ethernet rate-adjustable communication method and system based on FPGA. Background Technology

[0002] Visible light communication is a wireless communication technology that transmits data using visible light. This technology utilizes the high-frequency flickering of light-emitting diodes (LEDs) for information transmission. In recent years, LEDs have replaced traditional incandescent lamps in the market due to their advantages such as high luminous efficiency, low power consumption, no radiation, and long lifespan, thus driving the development of visible light communication. Unlike traditional lighting methods, white LEDs can switch light intensity rapidly and stably without being perceptible to the human eye. When combined with signal modulation in a communication system, this allows for the simultaneous fulfillment of both lighting and communication needs.

[0003] Ethernet, as the most commonly used communication interface and the most widely applied local area network (LAN) technology, is prevalent in current production and daily life. Its simple interface and ease of connection make it crucial in communication transmission. Integrating visible light communication with Ethernet technology can serve as a "last mile" indoor wireless access technology, complementing cellular networks and Wi-Fi systems, providing users with high-speed network access services, and bringing broader application prospects to the field of indoor short-range communication. With its advantages of high speed, high bandwidth, and easy integration, visible light communication has enormous development potential and practical significance in fields such as high-speed wireless transmission and underwater communication. Summary of the Invention

[0004] This invention addresses the problem of the lack of highly practical variable-rate Ethernet access systems in existing visible light communication devices.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] On one hand, the present invention provides an FPGA-based visible light Ethernet rate adjustable communication system, which includes an off-chip PHY chip, a MAC core, an FPGA rate conversion flow control module, an FPGA transmit control module, an FPGA receive control module, a transceiver circuit, an LED, and a photodiode.

[0007] in:

[0008] The external PHY chip, MAC core, and FPGA rate conversion flow control module are connected in sequence. The FPGA rate conversion flow control module is connected to the FPGA transmit control module and the FPGA receive control module, respectively. The FPGA transmit control module and the FPGA receive control module are connected to the transceiver circuit, respectively. The transceiver circuit is connected to the LED and the photodiode, respectively.

[0009] Optionally, an off-chip PHY chip is used to transmit Ethernet data streams to the MAC core via the RGMII interface.

[0010] Optionally, the MAC core is used to connect the external PHY chip to the user-side logic and to configure the external PHY chip by reading and writing registers through MDIO.

[0011] The MAC core's off-chip PHY chip supports 10 / 100 / 1000BASE-T standard and RGMII interface devices.

[0012] The user side of the MAC core interconnects with the user logic through a FIFO data buffer.

[0013] Optionally, the FPGA rate conversion flow control module includes an ON / OFF flow control module and a FIFO data buffer.

[0014] Optionally, the FPGA transmission control module includes a transmission state machine, a 4B / 5B encoding module, and a first parallel-to-serial conversion module.

[0015] Optionally, the FPGA receiver control module includes a clock data recovery (CDR), a second serial-to-parallel conversion module, a 4B / 5B decoding module, and a receiver state machine.

[0016] Optionally, the transceiver circuit includes a transmitting end and a receiving end.

[0017] The transmitting end of the transceiver circuit includes an LED driver circuit.

[0018] The receiving end of the transceiver circuit includes a transimpedance amplifier, a low-pass filter, an amplifier, and a decision circuit.

[0019] Optionally, an LED is used to convert the biased electrical signal into an optical signal output.

[0020] Optionally, a photodiode is used to receive optical signals and convert them into serial digital electrical signals, which are then sent to the transceiver circuit.

[0021] On the other hand, the present invention provides an FPGA-based visible light Ethernet rate adjustable communication method, which is implemented by an FPGA-based visible light Ethernet rate adjustable communication system, including an off-chip PHY chip, a MAC core, an FPGA rate conversion flow control module, an FPGA transmit control module, an FPGA receive control module, a transceiver circuit, an LED, and a photodiode.

[0022] The method includes:

[0023] When the system sends data, the external PHY chip acquires the Ethernet data stream to be transmitted and transmits the Ethernet data stream to the MAC core. After being processed by the FPGA rate conversion flow control module, it is sent to the FPGA transmission control module. The FPGA transmission control module converts the processed Ethernet data stream into a serial digital electrical signal and transmits it to the transceiver circuit. The transceiver circuit processes the serial digital electrical signal and loads it onto the LED to generate a light signal.

[0024] When the system receives data, the photodiode receives the optical signal and converts it into a serial digital electrical signal, which is then transmitted to the FPGA receiving control module via the transceiver circuit. The FPGA receiving control module converts the serial digital electrical signal into an Ethernet data stream and transmits it to the FPGA rate conversion and flow control module for processing. The FPGA rate conversion and flow control module then transmits the processed Ethernet data stream to the MAC core and the external PHY chip. The external PHY chip then transmits the Ethernet data stream to the user equipment.

[0025] Optionally, an off-chip PHY chip is used to transmit Ethernet data streams to the MAC core via the RGMII interface.

[0026] Optionally, the MAC core is used to connect the external PHY chip to the user-side logic and to configure the external PHY chip by reading and writing registers through MDIO.

[0027] The MAC core's off-chip PHY chip supports 10 / 100 / 1000BASE-T standard and RGMII interface devices.

[0028] The user side of the MAC core interconnects with the user logic through a FIFO data buffer.

[0029] Optionally, the FPGA rate conversion flow control module includes an ON / OFF flow control module and a FIFO data buffer.

[0030] Optionally, the FPGA transmission control module includes a transmission state machine, a 4B / 5B encoding module, and a first parallel-to-serial conversion module.

[0031] Optionally, the FPGA receiver control module includes a clock data recovery (CDR), a second serial-to-parallel conversion module, a 4B / 5B decoding module, and a receiver state machine.

[0032] Optionally, the transceiver circuit includes a transmitting end and a receiving end.

[0033] The transmitting end of the transceiver circuit includes an LED driver circuit.

[0034] The receiving end of the transceiver circuit includes a transimpedance amplifier, a low-pass filter, an amplifier, and a decision circuit.

[0035] Optionally, an LED is used to convert the biased electrical signal into an optical signal output.

[0036] Optionally, a photodiode is used to receive optical signals and convert them into serial digital electrical signals, which are then sent to the transceiver circuit.

[0037] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0038] The above solution provides an FPGA-based visible light Ethernet rate-adjustable communication system. By combining visible light communication and Ethernet technologies, and integrating the FPGA terminal with peripheral circuits, it solves the problem of the lack of highly practical communication systems for visible light communication. Simultaneously, the FPGA's internal logic, through rate conversion and flow control mechanisms, eliminates the need for the visible light channel to meet the Ethernet interface rate standard, enabling the adjustment of the Ethernet over-line rate to adapt to different channel environments and bandwidth requirements. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a block diagram of an FPGA-based visible light Ethernet rate-adjustable communication system provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of the internal logic module of the FPGA provided in an embodiment of the present invention;

[0042] Figure 3 This is a flowchart of an FPGA-based visible light Ethernet rate-adjustable communication method provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0044] like Figure 1 As shown, this embodiment of the invention provides an FPGA-based visible light Ethernet rate-adjustable communication system. The system includes an off-chip PHY chip, a MAC core, an FPGA rate conversion flow control module, an FPGA transmit control module, an FPGA receive control module, a transceiver circuit, an LED, and a photodiode.

[0045] in:

[0046] An off-chip PHY (Physical Layer) chip, a MAC (Media Access Control) core, and an FPGA (Field Programmable Gate Array) rate conversion and flow control module are connected in sequence. The FPGA rate conversion and flow control module is connected to the FPGA transmit control module and the FPGA receive control module, respectively. The FPGA transmit control module and the FPGA receive control module are connected to the transceiver circuit, respectively. The transceiver circuit is connected to the LED and the photodiode, respectively.

[0047] One feasible implementation method is, for example Figure 2 As shown, the system logic inside the FPGA, as the core part of the system, includes a MAC core, a speed conversion flow control module, a transmit control module, and a receive control module.

[0048] Optionally, an off-chip PHY chip is used to transmit Ethernet data streams to the MAC core via the RGMII interface.

[0049] Optionally, the MAC core is used to connect the external PHY chip to the user-side logic and to configure the external PHY chip by reading and writing registers through MDIO.

[0050] The MAC core's off-chip PHY chip supports 10 / 100 / 1000BASE-T standard and RGMII interface devices.

[0051] The user side of the MAC core interconnects with the user logic through a FIFO data buffer.

[0052] In one feasible implementation, the RGMII (Reduced Gigabit Media Independent Interface) interface control module primarily handles the correct reception and transmission of Ethernet data, clock signals, and control signals received by the PHY chip from the user equipment via the network cable through the RGMII interface. The MDIO (Management Data Input / Output) control module, driven by the AXI4-Lite bus, employs a three-stage state machine. It initializes and configures the PHY chip by reading and writing registers through the MDIO, ensuring the PHY chip operates in 100Mbps full-duplex mode.

[0053] Optionally, the FPGA rate conversion flow control module includes an ON / OFF flow control module and a FIFO data buffer.

[0054] In one feasible implementation, the FPGA rate conversion flow control module consists of an ON / OFF flow control module and a frame length and data buffer FIFO (First Input First Output) to buffer the transmitted and received Ethernet data frames and frame length information, respectively. The write clock for the transmitting FIFO is the data reception rate of the PHY chip, and the read clock is obtained by dividing the onboard clock. The read rate can be controlled by adjusting the division coefficient. The ON / OFF flow control module controls the reading and writing of the FIFO, ensuring that the FIFO is neither too empty nor too full. The write clock for the receiving FIFO is the serial clock recovered by the receive control module, and the read clock is the data transmission rate of the PHY chip.

[0055] Furthermore, due to the need to convert from high-speed to low-speed signals, asynchronous FIFOs are often used as data buffers for multi-bit transmission across clock domains. However, since the write rate of the FIFO in this system may be much higher than the read rate, the buffer will inevitably become full at times, and there cannot be an infinitely large FIFO to supply buffering capacity. Therefore, it is necessary to discard data frames appropriately. Based on TCP / IP's timeout retransmission rules, the communication device will automatically retransmit discarded data frames. The ON / OFF flow control module uses a waterline-based flow control technology. When the amount of data stored in the FIFO exceeds a high threshold, an OFF signal is triggered, stopping FIFO writing and allowing normal reading; when the amount of data stored in the FIFO falls below a low threshold, an ON signal is triggered, resuming FIFO writing. This avoids data congestion in the buffer, maximizes the utilization of the FIFO capacity, and completes the conversion from high-speed to low-speed signals.

[0056] Optionally, the FPGA transmission control module includes a transmission state machine, a 4B / 5B encoding module, and a first parallel-to-serial conversion module.

[0057] In one feasible implementation, the transmitting state machine is responsible for reassembling the buffered Ethernet data frames into visible light Ethernet physical frames, and sequentially sending the idle code, flag bit, frame length and actual frame data after the FIFO is synchronized.

[0058] Specifically, the FPGA's transmit control module is responsible for converting parallel data from the RGMII interface into serial transmission. During this process, it performs tasks such as rate conversion, flow control, data buffering, 4B / 5B encoding, and serialization. Finally, the serial data is output to the transceiver circuit via the FEP to SMA daughter card.

[0059] Furthermore, the transmitting state machine employs a 10-state cycle, responsible for converting Ethernet data frame formats into custom visible light Ethernet data frames. Within the state cycle, the idle code, flag bits, and, after FIFO synchronization, the frame length and actual frame data are transmitted sequentially. All transmitted data passes through a 4B / 5B encoded FIFO, completing cross-clock domain read / write operations, and is finally converted into a serial signal for output from the SMA interface on the board.

[0060] Furthermore, 4B / 5B encoding uses 5 bits of binary data to represent 4 bits of binary data, which can ensure that there are enough level transitions in optical transmission, prevent long lines of 0 or 1, and help the receiver extract clock information.

[0061] Furthermore, the first parallel-to-serial conversion module is responsible for converting parallel data into serial data and outputting it from the FPGA's IO port.

[0062] Optionally, the FPGA receiver control module includes a CDR (Clock Data Recovery), a second serial-to-parallel conversion module, a 4B / 5B decoding module, and a receiver state machine.

[0063] In one feasible implementation, CDR (clock data recovery) extracts the clock from the serial data by four times oversampling and aligns the recovered clock with the data for bit synchronization.

[0064] Serial-to-parallel conversion transforms serial data into parallel data by aligning it through a free code window.

[0065] 4B / 5B decoding will recover 4 bits of binary data from 5 bits of binary data.

[0066] The receiving state machine uses a recovery clock, idle code, and set flag bits to synchronize with the transmitting end and receives the frame length and the actual transmitted data. It then sends the input data and control signals to the verification module for validation and compares the data with the validation results.

[0067] Specifically, the receiver control module mainly consists of a CDR (Continuous Data Retrieval), serial-to-parallel conversion, 4B / 5B decoding, a receiver state machine, and a CRC (Cyclic Redundancy Check) module. The CDR is responsible for recovering the clock synchronized with the transmitter from the high-speed serial data transmission. It primarily samples the received serial data using a clock four times the serial clock frequency. The rising edge position of the serial data is determined by capturing the transition edges, and the serial clock is recovered in the middle of each bit for bit synchronization. The recovered serial data and clock are frame-synchronized using a predefined idle code and converted into parallel data. The 4B / 5B decoded data is then sent to the receiver state machine, which is responsible for idle code detection, idle code synchronization, preamble flag detection, frame length detection, and data frame detection. The visible light Ethernet physical frames are deframed to recover the Ethernet data frames, which are then sent to the receiving end of the rate conversion module. At the receiving end of the rate conversion module, for the data FIFO, since the read rate may be much higher than the write rate, to ensure the integrity of the Ethernet frame, a complete frame must be written before reading. The number of frames read is determined by the frame length of the frame length FIFO buffer. This process is performed by the frame integrity detection module. Specifically, this includes detecting the flag bit at the end of the written frame, synchronizing the frame end flag bit across the clock domain, and ensuring that the length of the read frame is consistent with the length of the written frame to guarantee the integrity of the read Ethernet frame. Finally, the data is sent to the CRC check module for CRC32 verification and compared with the FCS checksum of the last four bytes in the Ethernet frame to ensure the frame's correctness.

[0068] Optionally, the transceiver circuit includes a transmitting end and a receiving end.

[0069] The transmitting end of the transceiver circuit includes an LED driver circuit.

[0070] The receiving end of the transceiver circuit includes a transimpedance amplifier, a low-pass filter, an amplifier, and a decision circuit.

[0071] In one feasible implementation, the transmitting end of the transceiver circuit mainly consists of an LED driver circuit, which controls a push-pull circuit to drive a high-power LED light source through electrical signals output from the FPGA. The receiving end of the transceiver circuit mainly includes a transimpedance amplifier, which converts the photodiode current signal into a voltage signal; a low-pass filter, which filters out high-frequency signals in the signal; an amplifier, which further amplifies the input electrical signal; and a decision unit, which makes a decision on the input analog electrical signal, and the decision result is a digital 0 or 1 signal, which is then restored to the level standard conforming to the FPGA interface standard.

[0072] Furthermore, after receiving the digital electrical signal, the LED driver circuit of the transceiver circuit processes the digital electrical signal into an amplified electrical signal through a push-pull circuit, providing a large current to the LED light source and ensuring that the LED light output by the LED light source has sufficient brightness to facilitate the transmission of the optical signal.

[0073] Furthermore, the transimpedance amplifier in the transceiver circuit is responsible for converting the photodiode electrical signal into a voltage signal; the low-pass filter is responsible for filtering out high-frequency signals in the signal; the amplifier is responsible for further amplifying the input electrical signal; and the decision unit is responsible for making a decision on the input analog electrical signal, with the decision result being a digital 0 or 1 signal, and restoring it to the level standard that conforms to the FPGA interface standard.

[0074] Optionally, an LED is used to convert the biased electrical signal into an optical signal output.

[0075] In one feasible implementation, the bias electrical signal is directly applied to the LED light source, which converts the bias electrical signal into an optical signal for output.

[0076] Optionally, a photodiode is used to receive optical signals and convert them into serial digital electrical signals, which are then sent to the transceiver circuit.

[0077] In one feasible implementation, a photodiode detects optical signals in the space and converts the optical signals into current signals for the transceiver circuit module.

[0078] This invention provides an FPGA-based visible light Ethernet rate-adjustable communication system. By combining visible light communication and Ethernet technologies, and integrating the FPGA terminal with peripheral circuits, it solves the problem of the lack of highly practical visible light communication systems. Simultaneously, the FPGA's internal logic, through rate conversion and flow control mechanisms, eliminates the need for the visible light channel to meet Ethernet interface rate standards, enabling adjustable Ethernet over-the-line speeds to adapt to different channel environments and bandwidth requirements.

[0079] like Figure 3 As shown, this embodiment of the invention provides an FPGA-based visible light Ethernet rate-adjustable communication method. The method is implemented by an FPGA-based visible light Ethernet rate-adjustable communication system, which includes an off-chip PHY chip, a MAC core, an FPGA rate conversion flow control module, an FPGA transmit control module, an FPGA receive control module, a transceiver circuit, an LED, and a photodiode.

[0080] The method includes:

[0081] When the system sends data, the external PHY chip acquires the Ethernet data stream to be transmitted and transmits the Ethernet data stream to the MAC core. After being processed by the FPGA rate conversion flow control module, it is sent to the FPGA transmission control module. The FPGA transmission control module converts the processed Ethernet data stream into a serial digital electrical signal and transmits it to the transceiver circuit. The transceiver circuit processes the serial digital electrical signal and loads it onto the LED to generate a light signal.

[0082] When the system receives data, the photodiode receives the optical signal and converts it into a serial digital electrical signal, which is then transmitted to the FPGA receiving control module via the transceiver circuit. The FPGA receiving control module converts the serial digital electrical signal into an Ethernet data stream and transmits it to the FPGA rate conversion and flow control module for processing. The FPGA rate conversion and flow control module then transmits the processed Ethernet data stream to the MAC core and the external PHY chip. The external PHY chip then transmits the Ethernet data stream to the user equipment.

[0083] In one feasible implementation, the Ethernet data to be transmitted is sent from an off-chip PHY chip on the development board to the MAC core in the FPGA via the RGMII interface. The FPGA's transmit control module is responsible for converting the parallel data from the RGMII interface into serial transmission. During this process, it performs rate conversion, flow control, data buffering, 4B / 5B encoding, and serialization. Finally, the serial data is output to the transceiver circuit via an FEP-to-SMA daughter card. The transceiver circuit includes a bias circuit, amplifier, automatic gain control, etc. After adjusting the signal bias and amplitude, it is applied to the LED. At the receiving end, the PD converts the optical signal into an electrical signal. The FPGA's receive control module is responsible for recovering the clock and data from the received signal, and deserializing, decoding, buffering, and reassembling the data signal according to the recovered clock signal. After another rate conversion, the Ethernet data is sent to the user at the other end. The rate conversion can achieve any online rate from 100kbps to 100Mbps, reducing the online rate to adapt to low-speed usage scenarios while achieving normal internet communication functions.

[0084] Optionally, the MAC core is used to connect the external PHY chip to the user-side logic and to configure the external PHY chip by reading and writing registers through MDIO.

[0085] The MAC core's off-chip PHY chip supports 10 / 100 / 1000BASE-T standard and RGMII interface devices.

[0086] The user side of the MAC core interconnects with the user logic through a FIFO data buffer.

[0087] Optionally, the FPGA rate conversion flow control module includes an ON / OFF flow control module and a FIFO data buffer.

[0088] Optionally, the FPGA transmission control module includes a transmission state machine, a 4B / 5B encoding module, and a first parallel-to-serial conversion module.

[0089] Optionally, the FPGA receiver control module includes a clock data recovery (CDR), a second serial-to-parallel conversion module, a 4B / 5B decoding module, and a receiver state machine.

[0090] Optionally, the transceiver circuit includes a transmitting end and a receiving end.

[0091] The transmitting end of the transceiver circuit includes an LED driver circuit.

[0092] The receiving end of the transceiver circuit includes a transimpedance amplifier, a low-pass filter, an amplifier, and a decision circuit.

[0093] Optionally, an LED is used to convert the biased electrical signal into an optical signal output.

[0094] Optionally, a photodiode is used to receive optical signals and convert them into serial digital electrical signals, which are then sent to the transceiver circuit.

[0095] This invention provides an FPGA-based visible light Ethernet rate-adjustable communication system. By combining visible light communication and Ethernet technologies, and integrating the FPGA terminal with peripheral circuits, it solves the problem of the lack of highly practical visible light communication systems. Simultaneously, the FPGA's internal logic, through rate conversion and flow control mechanisms, eliminates the need for the visible light channel to meet Ethernet interface rate standards, enabling adjustable Ethernet over-the-line speeds to adapt to different channel environments and bandwidth requirements.

[0096] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A FPGA-based visible light Ethernet rate adjustable communication system, characterized in that, The system comprises an off-chip PHY chip, a MAC core, an FPGA rate conversion flow control module, an FPGA sending control module, an FPGA receiving control module, a transceiver circuit, an LED lamp and a photodiode. Wherein: The off-chip PHY chip, the MAC core and the FPGA rate conversion flow control module are connected in sequence, the FPGA rate conversion flow control module is connected with the FPGA sending control module and the FPGA receiving control module respectively, the FPGA sending control module and the FPGA receiving control module are connected with the transceiver circuit respectively, and the transceiver circuit is connected with the LED lamp and the photodiode respectively. The MAC core configures the off-chip PHY chip through MDIO read-write registers. The FPGA rate conversion flow control module comprises an ON / OFF flow control module, a sending end FIFO data buffer and a receiving end FIFO data buffer, and is based on the timeout retransmission rule of TCP / IP; wherein the writing clock of the sending end FIFO data buffer is the rate of receiving data of the PHY chip, the reading clock is obtained by frequency division of the on-board clock, the frequency division coefficient is controlled through an adjustable parameter, and the purpose of controlling the reading rate is achieved. The FPGA sending control module comprises a sending state machine, a 4B / 5B encoding module and a first parallel-serial conversion module; wherein the sending state machine adopts a 10-state cycle to convert the Ethernet data frame format into a self-defined visible light Ethernet data frame, and sends the idle code, the flag bit, the frame length and the actual frame data in sequence in the state cycle after completing synchronization in the FIFO. The FPGA receiving control module comprises a clock data recovery CDR, a second serial-parallel conversion module, a 4B / 5B decoding module, a receiving state machine, a frame integrity detection module and a CRC check module; wherein the frame integrity detection module is used for detecting the flag bit written in the frame tail, performing cross-clock domain synchronization on the frame tail flag bit, and controlling the frame length read out to be consistent with the frame length written in, so as to ensure the integrity of the read-out Ethernet frame.

2. The system of claim 1, wherein, The off-chip PHY chip is used for transmitting an Ethernet data stream to the MAC core through an RGMII interface.

3. The system of claim 1, wherein, The MAC core is used for connecting the off-chip PHY chip and user-side logic. The off-chip PHY chip side of the MAC core supports 10 / 100 / 1000BASE-T standard and RGMII interface equipment. The user side of the MAC core is interconnected with user logic through a FIFO data buffer.

4. The system of claim 1, wherein, The transceiver circuit comprises a transceiver circuit sending end and a transceiver circuit receiving end. The transceiver circuit sending end comprises an LED driving circuit. The transceiver circuit receiving end comprises a transimpedance amplifier, a low-pass filter, an amplifier and a decision device.

5. The system of claim 1, wherein, The LED lamp is used for converting a biased electrical signal into an optical signal output.

6. The system of claim 1, wherein, The photodiode is used for receiving an optical signal and converting the optical signal into a serial digital electrical signal and sending the serial digital electrical signal to the transceiver circuit.

7. A method for FPGA-based visible light Ethernet rate adjustable communication, characterized in that, The method is realized by a FPGA-based visible light Ethernet rate adjustable communication system, the system comprises an off-chip PHY chip, a MAC core, a FPGA rate conversion flow control module, a FPGA sending control module, a FPGA receiving control module, a transceiver circuit, an LED lamp and a photodiode; The method comprises: When the system sends data, the off-chip PHY chip acquires an Ethernet data stream to be transmitted, and transmits the Ethernet data stream to the MAC core, and after processing by the FPGA rate conversion flow control module, sends the Ethernet data stream to the FPGA sending control module, the FPGA sending control module converts the processed Ethernet data stream into a serial digital electrical signal, and transmits the serial digital electrical signal to the transceiver circuit, the transceiver circuit processes the serial digital electrical signal and loads the serial digital electrical signal on the LED lamp to generate an optical signal; When the system receives data, the photodiode receives an optical signal, and converts the optical signal into a serial digital electrical signal, and transmits the serial digital electrical signal to the FPGA receiving control module through the transceiver circuit, the FPGA receiving control module converts the serial digital electrical signal into an Ethernet data stream, and transmits the Ethernet data stream to the FPGA rate conversion flow control module for processing, the FPGA rate conversion flow control module transmits the processed Ethernet data stream to the MAC core and the off-chip PHY chip, and the off-chip PHY chip transmits the Ethernet data stream to a user equipment; The MAC core configures the off-chip PHY chip through MDIO read-write registers; The FPGA rate conversion flow control module comprises an ON / OFF flow control module, a sending end FIFO data buffer and a receiving end FIFO data buffer, and is based on a TCP / IP timeout retransmission rule; wherein the writing clock of the sending end FIFO data buffer is the rate of receiving data of the PHY chip, the reading clock is obtained by frequency division of a board clock, the frequency division coefficient is controlled through an adjustable parameter, and the purpose of controlling the reading rate is achieved; The FPGA sending control module comprises a sending state machine, a 4B / 5B encoding module and a first parallel-serial conversion module; wherein the sending state machine adopts a 10-state cycle, converts an Ethernet data frame format into a self-defined visible light Ethernet data frame, and sends idle codes, flag bits, frame lengths and actual frame data in sequence in the state cycle after synchronization of the FIFO is completed; The FPGA receiving control module comprises a clock data recovery CDR, a second serial-parallel conversion module, a 4B / 5B decoding module, a receiving state machine, a frame integrity detection module and a CRC check module; wherein the frame integrity detection module is used for detecting a flag bit written in a frame tail, performs cross-clock domain synchronization on the frame tail flag bit, and controls the frame length read out to be consistent with the frame length written in, so as to ensure the integrity of the Ethernet frame read out.

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