Adjustable Fan for Data Center Cooling System

Abstract

Systems and methods for cooling a server chassis are disclosed. In at least one embodiment, a fan switches between an axial operating mode and a centrifugal operating mode to change the direction of airflow within the server chassis.

Description

Technical Field

[0001] At least one embodiment relates to cooling systems, including systems and methods for operating such cooling systems. In at least one embodiment, such cooling systems can be used in data centers that include one or more racks or computing servers. Background Art

[0002] Data center cooling systems use fans to circulate air through server components. Two different types of fans are commonly used. The first type is an axial fan, where air is driven along the fan axis towards a heat sink and heat is dissipated outside the chassis based on the thermal characteristics of the chassis. The second type is a centrifugal fan, where air is driven perpendicular to the fan axis through a heat sink and then exhausted from the chassis. Brief Description of the Drawings

[0003] Figure 1 A chassis having a cooling system according to at least one embodiment is shown;

[0004] Figure 2A A chassis cooling system having a fan for operating in an axial operation mode according to at least one embodiment is shown;

[0005] Figure 2B A chassis cooling system having a fan for operating in a centrifugal operation mode according to at least one embodiment is shown;

[0006] Figure 3 A blade pitch control assembly for a chassis cooling system according to at least one embodiment is shown;

[0007] Figure 4A A blade pitch control assembly for a chassis cooling system according to at least one embodiment is shown;

[0008] Figure 4B A blade pitch control assembly for a chassis cooling system according to at least one embodiment is shown;

[0009] Figure 5A A method for adjusting a fan operation mode according to at least one embodiment is shown;

[0010] Figure 5B A method for adjusting a fan operation mode according to at least one embodiment is shown;

[0011] Figure 6 A distributed system according to at least one embodiment is shown;

[0012] Figure 7 An exemplary data center according to at least one embodiment is shown;

[0013] Figure 8 Shows a client - server network according to at least one embodiment;

[0014] Figure 9 Shows a computer network according to at least one embodiment;

[0015] Figure 10A Shows a networked computer system according to at least one embodiment;

[0016] Figure 10B Shows a networked computer system according to at least one embodiment;

[0017] Figure 10C Shows a networked computer system according to at least one embodiment;

[0018] Figure 11 Shows one or more components of a system environment in which services can be provided as third - party network services;

[0019] Figure 12 Shows a cloud computing environment according to at least one embodiment;

[0020] Figure 13 Shows a set of functional abstraction layers provided by a cloud computing environment according to at least one embodiment;

[0021] Figure 14 Shows a supercomputer at the chip level according to at least one embodiment;

[0022] Figure 15 Shows a supercomputer at the rack module level according to at least one embodiment;

[0023] Figure 16 Shows a supercomputer at the rack level according to at least one embodiment;

[0024] Figure 17 Shows a supercomputer at the whole - system level according to at least one embodiment;

[0025] Figure 18A Shows inference and / or training logic according to at least one embodiment;

[0026] Figure 18B Shows inference and / or training logic according to at least one embodiment;

[0027] Figure 19 Shows the training and deployment of a neural network according to at least one embodiment;

[0028] Figure 20 Shows the architecture of a network system according to at least one embodiment;

[0029] Figure 21 Shows the architecture of a network system according to at least one embodiment;

[0030] Figure 22 Shows the control plane protocol stack according to at least one embodiment;

[0031] Figure 23 Shows the user plane protocol stack according to at least one embodiment;

[0032] Figure 24 Shows the components of a core network according to at least one embodiment;

[0033] Figure 25 Shows the components of a system supporting network function virtualization (NFV) according to at least one embodiment;

[0034] Figure 26 Shows a processing system according to at least one embodiment;

[0035] Figure 27 Shows a computer system according to at least one embodiment;

[0036] Figure 28 Shows a system according to at least one embodiment;

[0037] Figure 29 Shows an exemplary integrated circuit according to at least one embodiment;

[0038] Figure 30 Shows a computing system according to at least one embodiment;

[0039] Figure 31 Shows an APU according to at least one embodiment;

[0040] Figure 32 Shows a CPU according to at least one embodiment;

[0041] Figure 33 Shows an exemplary accelerator integration slice according to at least one embodiment;

[0042] Figure 34A-34B Shows an exemplary graphics processor according to at least one embodiment;

[0043] Figure 35A Shows a graphics core according to at least one embodiment;

[0044] Figure 35B Shows a GPGPU according to at least one embodiment;

[0045] Figure 36AShows a parallel processor according to at least one embodiment;

[0046] Figure 36B Shows a processing cluster according to at least one embodiment;

[0047] Figure 36C Shows a graphics multiprocessor according to at least one embodiment;

[0048] Figure 37 Shows the software stack of a programming platform according to at least one embodiment;

[0049] Figure 38 Shows according to at least one embodiment Figure 37 of the CUDA implementation of the software stack;

[0050] Figure 39 Shows according to at least one embodiment Figure 37 of the ROCm implementation of the software stack;

[0051] Figure 40 Shows according to at least one embodiment Figure 37 of the OpenCL implementation of the software stack;

[0052] Figure 41 Shows software supported by a programming platform according to at least one embodiment; and

[0053] Figure 42 Shows according to at least one embodiment for use in Figure 37-40 compiled code to be executed on the programming platform. Detailed Description

[0054] In at least one embodiment, the server chassis 100 may include a chassis cooling system 102, as Figure 1 shown. In at least one embodiment, the server chassis 100 may form at least a portion of a rack within a data center. In at least one embodiment, the server chassis 100 houses one or more computing units or cards 104, which may include one or more computing devices 106 supported by a base 108 (such as a printed circuit board (PCB)). In at least one embodiment, the computing device 106 or data center device includes a graphics processing unit, a switch, a dual in-line memory module (DIMM), or a central processing unit (CPU). In at least one embodiment, the associated computing device or data center device may be a processing card having one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each GPU, switch, and CPU may be a heat generating feature of the computing device. In at least one embodiment, a GPU, CPU, or switch may have one or more cores, and each core may be a heat generating feature.

[0055] In at least one embodiment, a plurality of cards 104 may be stacked along the vertical height of the chassis 100, where each card 104 may include its own chassis cooling system 102 or may share the chassis cooling system 102 with another card. In at least one embodiment, a heat sink 110 is also provided that extends from the base 108 and may cover at least a portion of the computing device 106. In at least one embodiment, the heat sink 110 includes fins that are selected to have a high surface area to absorb and dissipate the heat generated by the computing device 106.

[0056] In at least one embodiment, the chassis cooling system 102 further includes a fan 112. In at least one embodiment, the fan 112 directs a cooling air flow along the heat sink 110. In at least one embodiment, the fan 112 may be configured to operate in an axial operation mode, where heat is directed in a downward direction along the fan axis and toward the base 108, where the heat is then dissipated through the chassis 100. In at least one embodiment, the fan 112 may be configured to operate in a centrifugal operation mode, where heat is directed through the heat sink 110 and exhausted from the chassis 100.

[0057] In at least one embodiment, the balance between thermal efficiency and acoustic noise reduction may result in one or more trade - offs. In at least one embodiment, an air - cooling method that directs a cooling air flow in a direction parallel to the fan axis may be adopted by the chassis 100, where the heat is dissipated through the chassis 100. In at least one embodiment, when several components are operating at high temperatures to accommodate the computer load in today's computing components, the thermal efficiency of the chassis 100 may not be efficient or may be ineffective for dissipating heat from the chassis 100. In at least one embodiment, an air - cooling method that directs a cooling air flow in a direction perpendicular to the fan axis may be discharged from the chassis 100. In at least one embodiment, these fans 112 have an undesired acoustic noise level and are generally less thermally efficient than fans 112 that direct air in a direction parallel to the fan axis.

[0058] In at least one embodiment, the chassis 100 may include one or more fans 112 that are configured to operate in two different modes. In at least one embodiment, one or more fans may operate in an axial operation mode, where air is directed in a direction parallel to the fan axis, and may also operate in a centrifugal operation mode, where air is directed in a direction perpendicular to the fan axis. In at least one embodiment, one or more fans 112 may switch between operation modes based on the thermal characteristics of the chassis 100. In at least one embodiment, the fan 112 may switch between operation modes based on acoustic characteristics.

[0059] In at least one embodiment, the fan 112 is configured to operate in both an axial operating mode and a centrifugal operating mode. In at least one embodiment, the fan 112 can switch between operating modes based on information provided by one or more sensors 114 within the chassis 100. In at least one embodiment, one or more of the sensors 114 includes a temperature sensor that measures the internal chassis temperature. In at least one embodiment, one or more of the sensors 114 includes an acoustic sensor that measures the internal chassis sound level. In at least one embodiment, one or more of the sensors 114 are arranged at specifically selected locations and may include duplicate sensors 114.

[0060] In at least one embodiment, the fan 112 operates in an axial operating mode as Figure 2A shown. In at least one embodiment, the operation of the fan 112 directs the airflow 200 in a first direction 202 that is generally parallel to the fan axis 204. In at least one embodiment, the airflow 200 is directed toward the computing device 106, through the heat sink 110, and into the server chassis 100. In at least one embodiment, the heat within the airflow 200 is absorbed by the server chassis 100 and dissipated into the surrounding atmosphere. In at least one embodiment, the airflow 200 cools the computing device 106, but the heat within the airflow 200 remains inside the server chassis 100. In at least one embodiment, the sensor 114 can record a temperature reading within the server chassis 100 to evaluate the cooling efficiency within the server chassis 100.

[0061] In at least one embodiment, the fan 112 includes blades 206 coupled to a hub 208. In at least one embodiment, the hub 208 is driven to rotate about the fan axis 204 by a motor (not shown) for example. In at least one embodiment, the axial operating mode at least partially corresponds to the airflow 200 in the first direction 202. In at least one embodiment, the airflow 200 is directed in the first direction 202 at least partially by the blade angle 210. In at least one embodiment, the blade angle 210 is represented by the angle between the blade profile 212 and the fan axis 204. In at least one embodiment, an acute blade angle value corresponds to the axial operating mode. In at least one embodiment, the value of the blade angle is between about 10 degrees and about 80 degrees. In at least one embodiment, the value of the blade angle is selected particularly based on the expected operating conditions of the fan 112 such as speed. In at least one embodiment, the value of the blade angle is selected particularly based on the physical parameters of the fan 112 such as blade length, fan diameter, blade curvature, or any other reasonable physical parameter of the fan 112.

[0062] In at least one embodiment, the operation of the fan 112 in the axial operation mode provides a strong heat dissipation capacity and low noise. In at least one embodiment, it is desirable to provide high heat dissipation for cooling the computing device 106. In at least one embodiment, low noise may also be desirable. In at least one embodiment, the operation in the axial operation mode can provide sufficient cooling for the computing device 106 while also balancing the noise level.

[0063] In at least one embodiment, the server chassis 100 may have a heat dissipation capacity below the desired level. In at least one embodiment, as Figure 2B shown, by changing the operation mode of the fan 112 from the axial operation mode to the centrifugal operation mode, the air flow 200 can be dissipated from the server chassis 100 through the vent 214. In at least one embodiment, when in the centrifugal operation mode, the air flow 200 is directed in a second direction 216 perpendicular to the fan axis 204. In at least one embodiment, the air flow 200 exits an opening formed in the shroud of the fan 112, interacts with the heat sink 110 to remove heat from the computing device 106, and is discharged from the interior of the server chassis 100. In at least one embodiment, removing heat from the server chassis 100 enables the use of a server chassis with a reduced heat dissipation capacity. In at least one embodiment, as Figure 2A shown, by discharging the air flow 200 instead of retaining the air flow 200 within the server chassis 100, the internal temperature of the server chassis 100 can be reduced.

[0064] In at least one embodiment, the blades 206 are positioned such that the blade profile 212 is generally parallel to the fan axis 204 in the centrifugal operation mode. In at least one embodiment, the blades 206 rotate about a pivot axis to change the position of the blade profile 212 relative to the fan axis 204. In at least one embodiment, the alignment of the blade profile 212 with the fan axis 204 drives the air flow 200 in the second direction 216. In at least one embodiment, the blades 206 are curved or arcuate to facilitate the movement of the air flow 200. In at least one embodiment, the curvature of the blades 206 is specifically selected based on the expected operating conditions.

[0065] In at least one embodiment, the fan 112 can operate in both an axial operation mode and a centrifugal operation mode to realize the benefits provided by each system. In at least one embodiment, the operation in the axial operation mode provides improved cooling by directing the airflow 200 directly towards the computing device 106. In at least one embodiment, the operation in the axial operation mode can be quieter than the centrifugal operation mode. In at least one embodiment, periodic ventilation of the server chassis 100 may be desirable to reduce the temperature level within the server chassis 100. In at least one embodiment, the fan 112 can switch between the axial operation mode and the centrifugal operation mode. In at least one embodiment, the switch between the axial operation mode and the centrifugal operation mode can be responsive to information received from the sensor 114 within the server chassis 100. In at least one embodiment, the switch between the axial operation mode and the centrifugal operation mode can be performed periodically without input from the sensor 114. In at least one embodiment, the switch between the axial operation mode and the centrifugal operation mode can be performed without shutting down the fan 112.

[0066] In at least one embodiment, the fan 112 includes a blade pitch control assembly 300 for adjusting the blade position. In at least one embodiment, the blade profile 212 is adjusted relative to the fan axis 204 to change the operation of the fan 112 between the axial operation mode and the centrifugal operation mode. In at least one embodiment, the blade profile 212 is substantially parallel to the fan axis 204, as Figure 3 shown, to operate in the centrifugal operation mode. In at least one embodiment, the blade pitch control assembly 300 can drive the blade 206 to rotate about the pivot axis 302 to adjust the blade position to switch to the axial operation mode.

[0067] In at least one embodiment, the blade pitch control assembly 300 includes a blade motor 304 that includes a shaft 306 that engages a blade bearing 308 to enable the blade 206 to rotate about a pivot axis 302. In at least one embodiment, the pivot axis 302 is perpendicular to the fan axis 204. In at least one embodiment, the blade 206 includes a mounting member 310 coupled to the blade bearing 308. In at least one embodiment, the blade bearing 308 is a journal bearing that enables rotation about the pivot axis 302 in response to a rotational force or torque applied to the mounting member 310. In at least one embodiment, the shaft 306 engages the mounting member 310 and transfers the rotational force to the mounting member 310 to drive the blade 206 to rotate about the pivot axis 302. In at least one embodiment, power is provided by the blade motor 304, which can be a servo motor or any other reasonable type of motor for applying torque to the blade 206. In at least one embodiment, each blade 206 has an independent blade motor 304, but it should be understood that multiple blades 206 can share the blade motor 304.

[0068] In at least one embodiment, the blade motor 304 receives instructions such as a control signal to apply a rotational force to the blade 206, such as via the shaft 306. In at least one embodiment, the blade pitch control assembly 300 responds to a controller that receives information from the sensor 114. In at least one embodiment, in response to a threshold reading from one or more sensors 114, the blade pitch control assembly 300 can change its operating mode between an axial operating mode and a centrifugal operating mode.

[0069] In at least one embodiment, the blade 206 rotates about the pivot axis 302 via the blade bearing 308 in response to the rotational force. In at least one embodiment, the blade motor 304 applies a predetermined amount of energy to move the blade 206 between a first position corresponding to the axial operating mode and a second position corresponding to the centrifugal operating mode. In at least one embodiment, a stop limiter or rotation limiter is included to stop the rotation of the blade 206 when it exceeds a predetermined position. In at least one embodiment, the blade motor 304 is disposed within the hub 208 and is axially aligned with the pivot axis 302, forming a directional connection between the blade 206 and the shaft 406, but it should be understood that brakes, gearboxes, and other control elements, such as elements for preventing unintentional rotation of the blade 206, can also be included.

[0070] In at least one embodiment, the blade pitch control assembly 300 includes a push rod assembly 400 for adjusting the blade position between the axial operating mode and the centrifugal operating mode, as Figure 4A and Figure 4BAs shown. In at least one embodiment, the push rod assembly 400 includes a vane motor 402 for driving the push rod 404 in a first direction 406 and a second direction 408. In at least one embodiment, the vane motor 402 is a bidirectional motor that enables operation in both the first direction 406 and the second direction 408 to adjust the vane position. In at least one embodiment, the drive head 410 includes a link arm 412 that is coupled to a pin 414 (not shown) associated with the blade 206. In at least one embodiment, the inner ring 416 is rotatable about a pivot axis 302 and is mounted on the outer ring 418. In at least one embodiment, the axial movement of the push rod 404 is transmitted by the pin 414, and the pin 414 drives the rotation of the inner ring 416 about the pivot axis 302. In at least one embodiment, the rotation of the inner ring 416 is transmitted to the blade 206, thereby adjusting the blade profile 212 and changing the orientation of the blade 206.

[0071] In at least one embodiment, the push rod position 420 is represented by the length 422 between the drive head 410 and the vane motor 402. In at least one embodiment, as the length 422 changes, the position of the pin 414 also changes, and as a result, the blade 206 rotates about the pivot axis 302. In at least one embodiment, Figure 4A corresponds to the axial operation mode, Figure 4B corresponds to the centrifugal operation mode. In at least one embodiment, the length 422 varies between Figure 4A and Figure 4B such that the length 422 is less than the length 424. In at least one embodiment, the change in the length 422 or the length 424 also adjusts the pin position, which corresponds to the rotation of the inner ring 416 and the rotation of the blade 406. In at least one embodiment, the vane motor 402 can receive a command to drive the movement of the push rod 404, and the push rod 404 is translated to the inner ring 416 to adjust the position of the blade 206. In at least one embodiment, the drive head 410 includes a plurality of link arms 412, and each link arm is coupled to a different inner ring 416 for a different blade 206. In at least one embodiment, the push rod 404 is arranged along and substantially parallel to the fan axis 204.

[0072] In at least one embodiment, the process 500 for controlling the fan operation mode can be executed as Figure 5A shown. In at least one embodiment, 502 provides a fan with a pitch control assembly. In at least one embodiment, the blade pitch control assembly enables adjustment of the fan operation mode. In at least one embodiment, 504 enables the axial operation mode. In at least one embodiment, 506 enables the centrifugal operation mode. In at least one embodiment, 508 switches the operation mode between the axial operation mode and the centrifugal operation mode.

[0073] In at least one embodiment, the process 520 for controlling the fan operation mode based on temperature values may be performed as Figure 5B shown. In at least one embodiment, 522 provides a fan with a pitch control component. In at least one embodiment, 524 enables the axial operation mode. In at least one embodiment, 526 determines one or more temperature values of the chassis. In at least one embodiment, it may be determined 528 whether any one of these one or more temperature values exceeds a threshold or falls outside an allowed or specified range. In at least one embodiment, if not, the process may continue. In at least one embodiment, if one or more temperature values exceed such a threshold or fall outside such a range, then 530 enables the centrifugal operation mode. In at least one embodiment, the process may then continue, continuously monitoring the temperature values and switching between operation modes.

[0074] Server and Data Center

[0075] The following figures illustrate, but are not limited to, systems that may be used to implement at least one embodiment based on an exemplary network server and data center.

[0076] Figure 6 A distributed system 600 is shown in accordance with at least one embodiment. In at least one embodiment, the distributed system 600 includes one or more client computing devices 602, 604, 606, and 608 that are configured to execute and operate client applications, such as a web browser, a proprietary client, and / or variants thereof, over one or more networks 610. In at least one embodiment, the server 612 may be communicatively coupled to the remote client computing devices 602, 604, 606, and 608 via the network 610.

[0077] In at least one embodiment, the server 612 may be adapted to run one or more services or software applications, such as services and applications that can manage session activities for single sign-on (SSO) access across multiple data centers. In at least one embodiment, the server 612 may also provide other services, or software applications, which may include non-virtual and virtual environments. In at least one embodiment, these services may be provided to users of the client computing devices 602, 604, 606, and / or 608 as web-based services or cloud services or under a software as a service (SaaS) model. In at least one embodiment, users operating the client computing devices 602, 604, 606, and / or 608 may in turn utilize one or more client applications to interact with the server 612 to utilize the services provided by these components.

[0078] In at least one embodiment, the software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or the services provided by these components may also be implemented by one or more of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, a user operating a client computing device may then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components may be implemented in hardware, firmware, software, or a combination thereof. It should be understood that various different system configurations are possible, which may differ from distributed system 600. Thus, Figure 6 The illustrated embodiment is at least one embodiment of a distributed system for implementing an embodiment system and is not intended to be limiting.

[0079] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 may include different types of computing systems. In at least one embodiment, client computing devices may include portable handheld devices (e.g., cellular phones, computing tablets, personal digital assistants (PDAs)), or wearable devices (e.g., Google head-mounted displays), running software (such as Microsoft Windows ) and / or various mobile operating systems (such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS, and / or variants thereof). In at least one embodiment, the devices may support different applications, such as different Internet-related applications, email, short message service (SMS) applications, and may use various other communication protocols. In at least one embodiment, client computing devices may also include general-purpose personal computers, which in at least one embodiment include personal computers and / or laptop computers running various versions of Microsoft Apple and / or Linux operating systems.

[0080] In at least one embodiment, client computing devices may be workstation computers running any of various commercially available or UNIX-like operating systems, including but not limited to various GNU / Linux operating systems, such as Google Chrome OS. In at least one embodiment, client computing devices may also include electronic devices capable of communicating via one or more networks 610, such as thin client computers, Internet-enabled gaming systems (e.g., with or without a Microsoft Xbox game console with gesture input device), and / or a personal messaging device. Although Figure 6 the distributed system 600 in

[0081] In at least one embodiment, the network 610 in the distributed system 600 can be any type of network capable of supporting data communication using any of a variety of available protocols, including but not limited to TCP / IP (Transmission Control Protocol / Internet Protocol), SNA (System Network Architecture), IPX (Internetwork Packet Exchange), AppleTalk, and / or their variants. In at least one embodiment, the network 610 can be a local area network (LAN), an Ethernet-based network, Token Ring, a wide area network, the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., a network operating under any one of the Institute of Electrical and Electronics Engineers (IEEE) 802.11 protocol groups, and / or any other wireless protocol), and / or any combination of these and / or other networks.

[0082] In at least one embodiment, the server 612 can be composed of one or more general-purpose computers, dedicated server computers (in at least one embodiment, including PC (Personal Computer) servers, servers, midrange servers, mainframe computers, rack-mounted servers, etc.), server farms, server clusters, or any other suitable arrangement and / or combination. In at least one embodiment, the server 612 can include one or more virtual machines running a virtual operating system or other computing architectures involving virtualization. In at least one embodiment, one or more flexible logical storage device pools can be virtualized to maintain virtual storage devices for the server. In at least one embodiment, a virtual network can be controlled by the server 612 using software-defined networking. In at least one embodiment, the server 612 can be adapted to run one or more services or software applications.

[0083] In at least one embodiment, the server 612 can run any operating system, as well as any commercially available server operating system. In at least one embodiment, the server 612 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP (Hypertext Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, Servers, database servers, and / or their variants. In at least one embodiment, exemplary database servers include, but are not limited to, those commercially available from Oracle, Microsoft, Sybase, IBM (International Business Machines), and / or their variants.

[0084] In at least one embodiment, server 612 may include one or more applications for analyzing and consolidating data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, the data feeds and / or event updates may include, but are not limited to, feeds, updates, or real-time updates received from one or more third-party information sources and continuous data streams, which may include real-time events related to sensor data applications, financial quote providers, network performance measurement tools (e.g., network monitoring and business management applications), clickstream analysis tools, automotive traffic monitoring, and / or their variations. In at least one embodiment, server 612 may also include one or more applications for displaying the data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0085] In at least one embodiment, distributed system 600 may also include one or more databases 614 and 616. In at least one embodiment, the databases may provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 614 and 616 may reside in various locations. In at least one embodiment, one or more of databases 614 and 616 may reside on a non-transitory storage medium local to server 612 (and / or reside within server 612). In at least one embodiment, databases 614 and 616 may be remote from server 612 and communicate with server 612 via a network-based connection or a dedicated connection. In at least one embodiment, databases 614 and 616 may reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing the functions attributed to server 612 may be appropriately stored locally on server 612 and / or remotely. In at least one embodiment, databases 614 and 616 may include relational databases, such as databases adapted to store, update, and retrieve data in response to SQL-formatted commands.

[0086] Figure 7 An exemplary data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, but is not limited to, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0087] In at least one embodiment, as Figure 7 shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“node C.R.”) 716(1)-716(N), where “N” represents any whole positive integer. In at least one embodiment, the node C.R. 716(1)-716(N) may include, but is not limited to, any number of central processing units (“CPU”) or other processors (including accelerators, field programmable gate arrays (“FPGA”), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 716(1)-716(N) may be a server having one or more of the above computing resources.

[0088] In at least one embodiment, the grouped computing resources 714 may include separate groupings (not shown) of node C.R. housed within one or more racks, or many racks (also not shown) within data centers at various geographical locations. The separate groupings of node C.R. within the grouped computing resources 714 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0089] In at least one embodiment, the resource coordinator 712 may configure or otherwise control one or more of the node C.R. 716(1)-716(N) and / or the grouped computing resources 714. In at least one embodiment, the resource coordinator 712 may include a software design infrastructure (“SDI”) management entity for the data center 700. In at least one embodiment, the resource coordinator 712 may include hardware, software, or some combination thereof.

[0090] In at least one embodiment, as Figure 7As shown, the framework layer 720 includes, but is not limited to, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, the framework layer 720 may include a framework for software 752 that supports the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 752 or the application 742 may include, respectively, web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open-source software web application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 738 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of the workloads supported by the various layers of the data center 700. In at least one embodiment, the configuration manager 734 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and the distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 is capable of managing the cluster or grouped computing resources mapped to or allocated for supporting the distributed file system 738 and the job scheduler 732. In at least one embodiment, the cluster or grouped computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0091] In at least one embodiment, the software 752 included in the software layer 730 may include software used by at least a portion of the nodes C.R. 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0092] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the nodes C.R. 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. One or more types of applications may include, but are not limited to, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variants thereof.

[0093] In at least one embodiment, any one of the configuration manager 734, the resource manager 736, and the resource coordinator 712 can implement any number and type of self-modifying actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions can relieve the data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilization and / or poorly performing portions of the data center.

[0094] Figure 8 A client-server network 804 formed by a plurality of interconnected network server computers 802 is shown in accordance with at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible to other network server computers 802 and to client computers 806 and networks 808 linked to the wide area network 804. In at least one embodiment, the configuration of the client-server network 804 can change over time as client computers 806 and one or more networks 808 connect to and disconnect from the network 804, and as one or more backbone server computers 802 are added to or removed from the network 804. In at least one embodiment, when client computers 806 and networks 808 are connected to network server computers 802, the client-server network includes such client computers 806 and networks 808. In at least one embodiment, the term computer includes any device or machine capable of accepting data, applying a prescribed process to the data, and providing the results of the process.

[0095] In at least one embodiment, the client-server network 804 stores information accessible to the network server computer 802, the remote network 808, and the client computer 806. In at least one embodiment, the network server computer 802 is formed by a mainframe, a minicomputer, and / or a microcomputer each having one or more processors. In at least one embodiment, the server computers 802 are linked together by wired and / or wireless transmission media such as wires, fiber optic cables, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, the client computer 806 accesses the network server computer 802 through a similar wired or wireless transmission media. In at least one embodiment, the client computer 806 can be linked to the client-server network 804 using a modem and a standard telephone communication network. In at least one embodiment, alternative carrier systems such as cable and satellite communication systems can also be used to link to the client-server network 804. In at least one embodiment, other private or time-sharing carrier systems can be used. In at least one embodiment, the network 804 is a global information network such as the Internet. In at least one embodiment, the network is a private intranet using a protocol similar to the Internet but with added security measures and restricted access controls. In at least one embodiment, the network 804 is a private or semi-private network using a proprietary communication protocol.

[0096] In at least one embodiment, the client computer 806 is any end-user computer and can also be a mainframe, a minicomputer, or a microcomputer having one or more microprocessors. In at least one embodiment, the server computer 802 can sometimes be used as a client computer accessing another server computer 802. In at least one embodiment, the remote network 808 can be a local area network, a network added to a wide area network through an independent service provider (ISP) for the Internet, or another group of computers interconnected by wired or wireless transmission media having a fixed or time-varying configuration. In at least one embodiment, the client computer 806 can be linked to and access the network 804 independently or through the remote network 808.

[0097] Figure 9A computer network 908 that connects one or more computing machines according to at least one embodiment is shown. In at least one embodiment, network 908 can be any type of electrically connected group of computers, including, for example, the following networks: the Internet, an intranet, a local area network (LAN), a wide area network (WAN), or an interconnected combination of these network types. In at least one embodiment, the connections within network 908 can be a remote modem, Ethernet (IEEE 802.3), Token Ring (IEEE 802.5), Fiber Distributed Data Link Interface (FDDI), Asynchronous Transfer Mode (ATM), or any other communication protocol. In at least one embodiment, the computing devices linked to the network can be desktop computers, servers, portable, handheld, set-top boxes, personal digital assistants (PDAs), terminals, or any other desired type or configuration. In at least one embodiment, depending on their functionality, network-connected devices can vary widely in processing power, internal memory, and other performance aspects.

[0098] In at least one embodiment, the communication within the network and the communication to or from the computing devices connected to the network can be wired or wireless. In at least one embodiment, network 908 can at least partially include the worldwide public Internet, which generally connects multiple users according to the client-server model according to the Transmission Control Protocol / Internet Protocol (TCP / IP) specification. In at least one embodiment, the client-server network is the dominant model for communication between two computers. In at least one embodiment, a client computer (“client”) issues one or more commands to a server computer (“server”). In at least one embodiment, the server fulfills the client commands by accessing available network resources and returning information to the client according to the client commands. In at least one embodiment, the client computer system and the network resources residing on the network server are assigned network addresses for identification during communication between the elements of the network. In at least one embodiment, the communication from other network-connected systems to the server will include the network address of the relevant server / network resource as part of the communication, so that the appropriate destination of the data / request is identified as the recipient. In at least one embodiment, when network 908 includes the global Internet, the network address is an IP address in TCP / IP format, which can at least partially route data to an email account, a website, or other Internet tools residing on the server. In at least one embodiment, the information and services residing on the network server can be available to the web browser of the client computer through a domain name (e.g., www.site.com), which maps to the IP address of the network server.

[0099] In at least one embodiment, multiple clients 902, 904, and 906 are connected to network 908 via respective communication links. In at least one embodiment, each of these clients can access network 908 via any desired form of communication, such as via a dial-up modem connection, cable link, digital subscriber line (DSL), wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine compatible with network 908, such as a personal computer (PC), workstation, dedicated terminal, personal data assistant (PDA), or other similar device. In at least one embodiment, clients 902, 904, and 906 may or may not be located in the same geographical area.

[0100] In at least one embodiment, multiple servers 910, 912, and 914 are connected to network 918 to serve clients communicating with network 918. In at least one embodiment, each server is generally a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, a server includes computer-readable data storage media for storing program instructions and data, such as a hard disk drive and RAM memory. In at least one embodiment, servers 910, 912, 914 run application programs in response to client commands. In at least one embodiment, server 910 can run a web server application for responding to client requests for HTML pages and can also run a mail server application for receiving and routing email. In at least one embodiment, other application programs, such as an FTP server or media server for streaming audio / video data to clients, can also be run on server 910. In at least one embodiment, different servers can be dedicated to performing different tasks. In at least one embodiment, server 910 can be a dedicated web server for managing website-related resources for different users, while server 912 can be dedicated to providing email management. In at least one embodiment, other servers can be dedicated to media (audio, video, etc.), file transfer protocol (FTP), or any combination of two or more services generally available or provided over the network. In at least one embodiment, each server can be located in the same or a different location from other servers. In at least one embodiment, multiple servers can perform mirror tasks for users, thereby alleviating congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, 914 are under the control of a web hosting provider in the business of maintaining and delivering third-party content over network 918.

[0101] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which may be referred to as a browser, requests content such as web pages, email messages, video clips, etc. from servers 910, 912, 914. In at least one embodiment, a second type, which may be referred to as a user, hires the web hosting provider to maintain a network resource such as a website and make it available to browsers. In at least one embodiment, the user contracts with the web hosting provider to make memory space, processor capacity, and communication bandwidth available for their desired network resource in accordance with the amount of server resources the user wishes to utilize.

[0102] In at least one embodiment, in order for the web hosting provider to serve these two clients, the application that manages the network resources hosted by the servers must be appropriately configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially controls the application's response to browser requests and also at least partially defines the server resources available to a particular user.

[0103] In one embodiment, an intranet server 916 communicates with a network 908 via a communication link. In at least one embodiment, the intranet server 916 communicates with a server manager 918. In at least one embodiment, the server manager 918 includes a database of application configuration parameters used in servers 910, 912, 914. In at least one embodiment, the user modifies the database 920 via the intranet 916, and the server manager 918 interacts with servers 910, 912, 914 to modify the application parameters so that they match the contents of the database. In at least one embodiment, the user logs into the intranet 916 by connecting to the intranet 916 via a computer 902 and entering authentication information such as a username and password.

[0104] In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that permits the user to access configuration parameters for a particular application. In at least one embodiment, a plurality of modifiable text boxes are presented to the user that describe aspects of the configuration of the user's website or other network resources. In at least one embodiment, if the user desires to increase the memory space reserved on the server for their website, a field is provided to the user in which the user specifies the desired memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards this information to the appropriate server and uses the new parameters during application operation. In at least one embodiment, the intranet server 916 is configured to provide the user with access to the configuration parameters of the hosted network resources (e.g., web pages, email, FTP sites, media sites, etc.) that the user has contracted with a web hosting service provider for.

[0105] Figure 10A Shown is a networked computer system 1000A according to at least one embodiment. In at least one embodiment, the networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, the personal computer or node 1002 includes a processor 1014, a memory 1016, a camera 1004, a microphone 1006, a mouse 1008, speakers 1010, and a monitor 1012. In at least one embodiment, the PCs 1002, 1018, 1020 may each run one or more desktop servers, such as an internal network within a given company, or may be servers for a general network not limited to a particular environment. In at least one embodiment, each PC node of the network has a server such that each PC node of the network represents a particular network server with a specific network URL address. In at least one embodiment, each server defaults to the default web page for the users of that server, which default web page itself may contain embedded URLs that point to further sub-pages for that user on that server, or to other servers or pages on other servers on the network.

[0106] In at least one embodiment, nodes 1002, 1018, 1020 and other nodes of the network are interconnected via medium 1022. In at least one embodiment, medium 1022 can be a communication channel such as an Integrated Services Digital Network (“ISDN”). In at least one embodiment, the various nodes of the networked computer system can be connected via various communication media, including a Local Area Network (“LAN”), Plain Old Telephone Service (“POTS”) (sometimes referred to as the Public Switched Telephone Network (“PSTN”)), and / or variants thereof. In at least one embodiment, the various nodes of the network can also constitute users of computer systems interconnected via a network such as the Internet. In at least one embodiment, each server on the network (operating from a particular node of the network at a given instance) has a unique address or identity within the network, which can be specified according to a URL.

[0107] In at least one embodiment, multiple Multipoint Control Units (“MCUs”) can thus be used to transmit data to and from the various nodes or “endpoints” of the conferencing system. In at least one embodiment, in addition to various other communication media (such as nodes connected via the Internet), the nodes and / or MCUs can be interconnected via an ISDN link or via a Local Area Network (“LAN”). In at least one embodiment, the nodes of the conferencing system can generally be directly connected to a communication medium such as a LAN or via an MCU, and the conferencing system can include other nodes or elements such as routers, servers, and / or variants thereof.

[0108] In at least one embodiment, processor 1014 is a general-purpose programmable processor. In at least one embodiment, the processors of the nodes of networked computer system 1000A can also be dedicated video processors. In at least one embodiment, the different peripheral devices and components of the nodes (such as those of node 1002) can be different from those of other nodes. In at least one embodiment, node 1018 and node 1020 can be configured to be the same as or different from node 1002. In at least one embodiment, in addition to PC systems, the nodes can be implemented on any suitable computer system.

[0109] Figure 10BIllustrates a networked computer system 1000B according to at least one embodiment. In at least one embodiment, system 1000B illustrates a network (such as LAN 1024) that can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are a plurality of nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, the nodes can also be connected to the LAN via a network server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, and for at least one embodiment, it includes routers, servers, and nodes.

[0110] Figure 10C Illustrates a networked computer system 1000C according to at least one embodiment. In at least one embodiment, system 1000C illustrates a WWW system having communication across a backbone communication network (such as the Internet 1032), and the backbone communication network can be used to interconnect various nodes of the network. In at least one embodiment, the WWW is a set of protocols operating on top of the Internet, and allows a graphical interface system to operate thereon to access information via the Internet. In at least one embodiment, attached to the Internet 1032 in the WWW are a plurality of nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, the nodes dock with other nodes of the WWW via WWW HTTP servers (such as servers 1034, 1036). In at least one embodiment, PC 1044 can be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although for illustrative purposes Figure 10C PC 1044 and server 1036 are shown separately in

[0111] In at least one embodiment, the WWW is a distributed type of application, characterized by the WWW HTTP, the protocol of the WWW, which runs on top of the Transmission Control Protocol / Internet Protocol (“TCP / IP”) of the Internet. In at least one embodiment, the WWW can thus be characterized by a set of protocols (i.e., HTTP) running on the Internet as its “backbone”.

[0112] In at least one embodiment, a web browser is an application that runs on a node of a network in a network system compatible with the WWW type, which allows users of a particular server or node to view such information and thus allows users to search for graphical and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understands HTTP. In at least one embodiment, when a user uses another server on a network such as the Internet to retrieve a given web page of a first server associated with a first node, the retrieved document may have different hypertext links embedded therein and a local copy of the user's locally created page is retrieved. In at least one embodiment, when a user clicks on a hypertext link, the locally stored information associated with the selected hypertext link is generally sufficient to allow the user's machine to open a connection over the Internet to the server indicated by the hypertext link.

[0113] In at least one embodiment, more than one user can be coupled to each HTTP server via a LAN (such as LAN 1038, as shown with respect to WWW HTTP server 1034). In at least one embodiment, system 1000C can also include other types of nodes or elements. In at least one embodiment, the WWW HTTP server is an application that runs on a machine such as a PC. In at least one embodiment, each user can be considered to have a unique "server", as shown with respect to PC 1044. In at least one embodiment, a server can be considered to be a server such as WWW HTTP server 1034 that provides access to the network for a LAN or multiple nodes or multiple LANs. In at least one embodiment, there are multiple users, each having a desktop PC or a node of the network, and each desktop PC potentially establishing a server for its user. In at least one embodiment, each server is associated with a specific network address or URL that, when accessed, provides the user with a default web page. In at least one embodiment, a web page can contain further links (embedded URLs) that point to further sub-pages of the user on that server, or to other servers on the network or to pages on other servers on the network.

[0114] Cloud computing and services

[0115] The following figures illustrate, but are not limited to, exemplary cloud-based systems that can be used to implement at least one embodiment.

[0116] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and typically virtualized resources are provided as a service over the Internet. In at least one embodiment, users do not need to have knowledge of, expertise in, or control over the technical infrastructure that supports them, which can be referred to as "in the cloud". In at least one embodiment, cloud computing incorporates infrastructure as a service, platform as a service, software as a service, and other variants with a common theme of relying on the Internet to meet the computing needs of users. In at least one embodiment, a typical cloud deployment (such as in a private cloud (e.g., an enterprise network) or a public cloud (e.g., the Internet)) data center (DC) can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel, or Ethernet Fibre Channel (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, the cloud can also consist of network service infrastructure, such as IPsec VPN hubs, firewalls, load balancers, wide area network (WAN) optimizers, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services through a connection via a VPN tunnel (such as an IPsec VPN tunnel).

[0117] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage devices, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction.

[0118] In at least one embodiment, cloud computing is characterized by on-demand self-service, in which consumers can automatically and unilaterally provision computing capabilities, such as server time and network storage, as needed without human interaction with each service provider. In at least one embodiment, cloud computing is characterized by broad network access, in which the capabilities are available over a network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, in which a provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically assigned and reassigned according to consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally have no control or knowledge of the exact location of the resources provided, but may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0119] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, where capabilities can be rapidly and elastically provisioned (automatically in some cases) to quickly scale down and quickly release to quickly scale up. In at least one embodiment, to the consumer, the capabilities available for provisioning generally appear unlimited and can be purchased in any quantity at any time. In at least one embodiment, cloud computing is characterized by measured service, where the cloud system automatically controls and optimizes resource use by leveraging metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage can be monitored, controlled, and reported, providing transparency for both the provider and consumer of the utilized service.

[0120] In at least one embodiment, cloud computing can be associated with various services. In at least one embodiment, cloud software as a service (SaaS) can refer to a service where the capabilities provided to the consumer are to use the provider's applications running on the cloud infrastructure. In at least one embodiment, the applications can be accessed from different client devices through a thin client interface such as a web browser (e.g., web-based email). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including the network, servers, operating systems, storage, or even the individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0121] In at least one embodiment, cloud platform as a service (PaaS) can refer to a service where the capabilities provided to the consumer are to deploy the application programs created or acquired by the consumer onto the cloud infrastructure, and these application programs are created using programming languages and tools supported by the provider. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure including the network, servers, operating systems, or storage, but has control over the deployed application programs and possibly the application hosting environment configuration.

[0122] In at least one embodiment, cloud infrastructure as a service (IaaS) can refer to a service where the capabilities provided to the consumer are to provide processing, storage, network, and other basic computing resources that the consumer can deploy and run any software that may include operating systems and applications. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure, but has control over the operating systems, storage, deployed application programs, and possibly limited control over selected networking components (e.g., host firewall).

[0123] In at least one embodiment, cloud computing can be deployed in different ways. In at least one embodiment, a private cloud may refer to a cloud infrastructure that is operated only for an organization. In at least one embodiment, a private cloud can be managed by an organization or a third party and can exist on-premises or off-premises. In at least one embodiment, a community cloud may refer to a cloud infrastructure that is shared by several organizations and supports a specific community with shared concerns (e.g., tasks, security requirements, policies, and compliance considerations). In at least one embodiment, a community cloud can be managed by an organization or a third party and can exist on-premises or off-premises. In at least one embodiment, a public cloud may refer to a cloud infrastructure that is available to the general public or large industry groups and is owned by an organization that provides cloud services. In at least one embodiment, a hybrid cloud may refer to a cloud infrastructure that is a composition of two or more clouds (private, community, or public), which remain distinct entities but are bound together through standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds). In at least one embodiment, a cloud computing environment is service-oriented, focusing on statelessness, low coupling, modularity, and semantic interoperability.

[0124] Figure 11 Illustrates one or more components of a system environment 1100 according to at least one embodiment, where services can be provided as third-party network services. In at least one embodiment, the third-party network can be referred to as a cloud, cloud network, cloud computing network, and / or variants thereof. In at least one embodiment, the system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which can be used by users to interact with a third-party network infrastructure system 1102 that provides third-party network services (which can be referred to as cloud computing services). In at least one embodiment, the third-party network infrastructure system 1102 can include one or more computers and / or servers.

[0125] It should be understood that Figure 11 the third-party network infrastructure system 1102 depicted in Figure 11 may have other components in addition to those depicted. Further, Figure 11 an embodiment of the third-party network infrastructure system is depicted. In at least one embodiment, the third-party network infrastructure system 1102 may have more or fewer components than

[0126] In at least one embodiment, client computing devices 1104, 1106, and 1108 may be configured to operate client applications, such as a web browser, a proprietary client application, or some other application that can be used by a user of the client computing device to interact with the third-party network infrastructure system 1102 to use services provided by the third-party network infrastructure system 1102. Although the exemplary system environment 1100 is shown as having three client computing devices, any number of client computing devices may be supported. In at least one embodiment, other devices, such as devices having sensors, etc., may interact with the third-party network infrastructure system 1102. In at least one embodiment, one or more networks 1110 may facilitate communication and data exchange between client computing devices 1104, 1106, and 1108 and the third-party network infrastructure system 1102.

[0127] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include a host of services that are available on demand to users of the third-party network infrastructure system. In at least one embodiment, various services may also be provided, including but not limited to online data storage and backup solutions, web-based email services, hosted office suites and document collaboration services, database management and processing, managed technical support services, and / or variants thereof. In at least one embodiment, the services provided by the third-party network infrastructure system may be dynamically scaled to meet the needs of its users.

[0128] In at least one embodiment, a particular instantiation of the services provided by the third-party network infrastructure system 1102 may be referred to as a "service instance". In at least one embodiment, generally, any service that is available to a user from a third-party network service provider system via a communication network (such as the Internet) is referred to as a "third-party network service". In at least one embodiment, in a common third-party network environment, the servers and systems that make up the third-party network service provider system are different from the servers and systems within the customer's own premises. In at least one embodiment, the third-party network service provider system may host applications, and users may order and use the applications on demand via a communication network (such as the Internet).

[0129] In at least one embodiment, services in a computer network third-party network infrastructure can include protected computer network access to storage, hosting databases, hosting web servers, software applications, or other services provided by a third-party network provider to users. In at least one embodiment, the services can include password-protected access over the Internet to remote storage devices on a third-party network. In at least one embodiment, the services can include a hosted relational database and a scripting language middleware engine based on a network service for private use by networked developers. In at least one embodiment, the services can include access to an email software application hosted on a website of a third-party network provider.

[0130] In at least one embodiment, the third-party network infrastructure system 1102 can include a set of application, middleware, and database service offerings delivered to customers in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, the third-party network infrastructure system 1102 can also provide "big data"-related computing and analysis services. In at least one embodiment, the term "big data" is generally used to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by the infrastructure system at many levels and in different scales. In at least one embodiment, dozens, hundreds, or thousands of processors linked in parallel can act on such data to present the data or simulate external forces on the data or what it represents. In at least one embodiment, these data sets can involve structured data (such as structured data stored in a database or otherwise organized according to a structured model) and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging the capabilities of the embodiments to relatively quickly focus more (or less) computing resources on a target, the third-party network infrastructure system can be better available for performing tasks on large data sets based on the needs from enterprises, government agencies, research organizations, private individuals, groups of like-minded individuals or organizations, or other entities.

[0131] In at least one embodiment, the third-party network infrastructure system 1102 may be adapted to automatically provide, manage, and track a customer's subscription to services provided by the third-party network infrastructure system 1102. In at least one embodiment, the third-party network infrastructure system 1102 may provide third-party network services via different deployment models. In at least one embodiment, services may be provided under a public third-party network model, where the third-party network infrastructure system 1102 is owned by an organization selling third-party network services and makes the services available to the general public or different industry enterprises. In at least one embodiment, services may be provided under a private third-party network model, in which the third-party network infrastructure system 1102 operates only for a single organization and may provide services for one or more entities within the organization. In at least one embodiment, third-party network services may also be provided under a community third-party network model, where the third-party network infrastructure system 1102 and the services provided by the third-party network infrastructure system 1102 are shared by several organizations in a related community. In at least one embodiment, third-party network services may also be provided under a hybrid third-party network model, which is a combination of two or more different models.

[0132] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include one or more services provided under a software as a service (SaaS) category, a platform as a service (PaaS) category, an infrastructure as a service (IaaS) category, or other service categories including hybrid services. In at least one embodiment, a customer may order one or more services provided by the third-party network infrastructure system 1102 via a subscription order. In at least one embodiment, the third-party network infrastructure system 1102 then performs processing to provide the services in the customer's subscription order.

[0133] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include, but are not limited to, application services, platform services, and infrastructure services. In at least one embodiment, the application services may be provided by the third-party network infrastructure system via a SaaS platform. In at least one embodiment, the SaaS platform may be configured to provide third-party network services belonging to the SaaS category. In at least one embodiment, the SaaS platform may provide the ability to build and deliver a set of on-demand applications on an integrated development and deployment platform. In at least one embodiment, the SaaS platform may manage and control the underlying software and infrastructure for providing the SaaS services. In at least one embodiment, by leveraging the services provided by the SaaS platform, customers may utilize applications executed on the third-party network infrastructure system. In at least one embodiment, customers may obtain application services without the need for customers to purchase separate licenses and support. In at least one embodiment, various different SaaS services may be provided. In at least one embodiment, this may include, but is not limited to, services that provide solutions for sales performance management, enterprise integration, and business agility for large organizations.

[0134] In at least one embodiment, the platform services may be provided by the third-party network infrastructure system 1102 via a PaaS platform. In at least one embodiment, the PaaS platform may be configured to provide third-party network services belonging to the PaaS category. In at least one embodiment, the platform services may include, but are not limited to, services that enable an organization to consolidate existing applications on a shared common architecture, and the ability to build new applications that utilize the shared services provided by the platform. In at least one embodiment, the PaaS platform may manage and control the underlying software and infrastructure for providing the PaaS services. In at least one embodiment, customers may obtain the PaaS services provided by the third-party network infrastructure system 1102 without the need for customers to purchase separate licenses and support.

[0135] In at least one embodiment, by leveraging the services provided by the PaaS platform, customers may adopt programming languages and tools supported by the third-party network infrastructure system and also control the deployed services. In at least one embodiment, the platform services provided by the third-party network infrastructure system may include database third-party network services, middleware third-party network services, and third-party network services. In at least one embodiment, the database third-party network services may support a shared service deployment model that enables an organization to pool database resources and provide database as a service to customers in the form of a database third-party network. In at least one embodiment, in the third-party network infrastructure system, the middleware third-party network services may provide a platform for customers to develop and deploy different business applications, and the third-party network services may provide a platform for customers to deploy applications.

[0136] In at least one embodiment, various different infrastructure services may be provided by an IaaS platform in a third-party network infrastructure system. In at least one embodiment, the infrastructure services facilitate the management and control by customers of underlying computing resources (such as storage, networking, and other basic computing resources) that utilize services provided by SaaS platforms and PaaS platforms.

[0137] In at least one embodiment, the third-party network infrastructure system 1102 may also include infrastructure resources 1130 for providing resources for delivering various services to customers of the third-party network infrastructure system. In at least one embodiment, the infrastructure resources 1130 may include a pre-integrated and optimized combination of hardware (such as servers, storage, and networking resources) for performing services and other resources provided by PaaS platforms and SaaS platforms.

[0138] In at least one embodiment, resources in the third-party network infrastructure system 1102 may be shared by multiple users and dynamically reallocated on demand. In at least one embodiment, resources may be allocated to users in different time zones. In at least one embodiment, the third-party network infrastructure system 1102 may enable a first group of users in a first time zone to utilize the resources of the third-party network infrastructure system for a specified number of hours, and then enable the same resources to be reallocated to another group of users located in a different time zone, thereby maximizing resource utilization.

[0139] In at least one embodiment, a plurality of internal shared services 1132 shared by different components or modules of the third-party network infrastructure system 1102 may be provided for implementing services provided by the third-party network infrastructure system 1102. In at least one embodiment, these internal shared services may include, but are not limited to, security and identity services, integration services, enterprise library services, enterprise manager services, virus scanning and whitelisting services, high availability, backup and recovery services, services for enabling third-party network support, email services, notification services, file transfer services, and / or variants thereof.

[0140] In at least one embodiment, the third-party network infrastructure system 1102 may provide comprehensive management of third-party network services (such as SaaS, PaaS, and IaaS services) in the third-party network infrastructure system. In at least one embodiment, the third-party network management function may include the ability to provision, manage, and track subscriptions of customers received by the third-party network infrastructure system 1102 and / or variants thereof.

[0141] In at least one embodiment, as Figure 11As shown, the third-party network management function may be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order supply module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules may include one or more computers and / or servers or use one or more computers and / or servers to provide, and the one or more computers and / or servers may be general-purpose computers, dedicated server computers, server farms, server clusters, or any other suitable arrangement and / or combination.

[0142] In at least one embodiment, at step 1134, a customer using a client device (such as client computing devices 1104, 1106, or 1108) may interact with the third-party network infrastructure system 1102 by requesting one or more services provided by the third-party network infrastructure system 1102 and placing an order for a subscription to one or more services provided by the third-party network infrastructure system 1102. In at least one embodiment, the customer may access a third-party network user interface (UI), such as third-party network UI 1112, third-party network UI 1114, and / or third-party network UI 1116, and place an order via these UIs. In at least one embodiment, the order information received by the third-party network infrastructure system 1102 in response to the customer placing an order may include information identifying the customer and one or more services provided by the third-party network infrastructure system 1102 that the customer wishes to subscribe to.

[0143] In at least one embodiment, at step 1136, the order information received from the customer may be stored in the order database 1118. In at least one embodiment, if this is a new order, a new record may be created for the order. In at least one embodiment, the order database 1118 may be one of several databases operated by the third-party network infrastructure system 1118 and operating in conjunction with other system elements.

[0144] In at least one embodiment, at step 1138, the order information may be forwarded to the order management module 1120, which may be configured to perform billing and accounting functions related to the order, such as verifying the order and, after verification, reserving an order.

[0145] In at least one embodiment, at step 1140, information about the order can be transmitted to the order coordination module 1122, which is configured to coordinate the supply of services and resources for an order placed by a customer. In at least one embodiment, the order coordination module 1122 can use the services of the order provisioning module 1124 for provisioning. In at least one embodiment, the order coordination module 1122 enables the management of business processes associated with each order and applies business logic to determine whether an order should continue to be provisioned.

[0146] In at least one embodiment, at step 1142, when a new subscription order is received, the order coordination module 1122 sends a request to the order provisioning module 1124 to allocate resources and configure the resources required to fulfill the subscription order. In at least one embodiment, the order provisioning module 1124 implements resource allocation for the services ordered by the customer. In at least one embodiment, the order provisioning module 1124 provides an abstraction level between the third-party network services provided by the third-party network infrastructure system 1100 and the physical implementation layer for provisioning the resources used to provide the requested services. In at least one embodiment, this enables the order coordination module 1122 to be isolated from implementation details, such as whether the services and resources are actually provisioned in real time or pre-provisioned and only allocated / assigned upon request.

[0147] In at least one embodiment, at step 1144, once the services and resources are provisioned, a notification indicating that the requested service is now ready to use can be sent to the subscribing customer. In at least one embodiment, information (e.g., a link) can be sent to the customer, which enables the customer to start using the requested service.

[0148] In at least one embodiment, at step 1146, the order subscribed by the customer can be managed and tracked by the order management and monitoring module 1126. In at least one embodiment, the order management and monitoring module 1126 can be configured to collect usage statistics regarding the use of the subscribed service by the customer. In at least one embodiment, statistics can be collected for the amount of storage used, the amount of data transmitted, the number of users, and the amount and / or variation of system power-on time and system power-off time.

[0149] In at least one embodiment, the third-party network infrastructure system 1100 may include an identity management module 1128 configured to provide identity services such as access management and authorization services in the third-party network infrastructure system 1100. In at least one embodiment, the identity management module 1128 may control information about customers who wish to utilize the services provided by the third-party network infrastructure system 1102. In at least one embodiment, such information may include information for authenticating the identities of such customers and information describing what actions those customers are authorized to perform relative to various system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, the identity management module 1128 may also include managing descriptive information about each customer and about how such descriptive information can be accessed and modified and by whom.

[0150] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, the cloud computing environment 1202 includes one or more computer systems / servers 1204, and computing devices such as personal digital assistants (PDAs) or cellular telephones 1206A, desktop computers 1206B, laptop computers 1206C, and / or in-vehicle computer systems 1206N communicate with the one or more computer systems / servers 1204. In at least one embodiment, this allows infrastructure, platform, and / or software as a service to be provided from the cloud computing environment 1202 so that each client does not need to separately maintain such resources. It should be understood that Figure 12 the types of computing devices 1206A-N shown are intended to be illustrative only, and the cloud computing environment 1202 may communicate with any type of computerized device via any type of network and / or network / addressable connection (e.g., using a web browser).

[0151] In at least one embodiment, the computer system / server 1204, which may be represented as a cloud computing node, may operate with many other general-purpose or special-purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations suitable for use with the computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems or devices, and / or variations thereof.

[0152] In at least one embodiment, the computer system / server 1204 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. In at least one embodiment, the exemplary computer system / server 1204 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In at least one embodiment, in a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0153] Figure 13 FIG. shows a set of functional abstraction layers provided by a cloud computing environment 1202 ( Figure 12 ). It should be understood in advance that Figure 13 the components, layers, and functions shown in are only illustrative, and the components, layers, and functions may vary.

[0154] In at least one embodiment, the hardware and software layer 1302 includes hardware and software components. In at least one embodiment, the hardware components include mainframes, servers based on various RISC (Reduced Instruction Set Computer) architectures, various computing systems, supercomputing systems, storage devices, networks, networking components, and / or their variants. In at least one embodiment, the software components include web application server software, various application server software, various database software, and / or their variants.

[0155] In at least one embodiment, the virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities may be provided: virtual servers, virtual storage, virtual networks (including virtual private networks), virtual applications, virtual clients, and / or their variants.

[0156] In at least one embodiment, the management layer 1306 provides various functions. In at least one embodiment, resource provisioning provides for the dynamic acquisition of computing resources and other resources for performing tasks within a cloud computing environment. In at least one embodiment, metering provides usage tracking when resources are utilized within a cloud computing environment, as well as billing or invoicing for the consumption of those resources. In at least one embodiment, resources can include application software licenses. In at least one embodiment, security provides authentication for users and tasks, as well as protection for data and other resources. In at least one embodiment, the user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides cloud computing resource allocation and management such that the required service levels are met. In at least one embodiment, service level agreement (SLA) management provides for the pre-provisioning and acquisition of cloud computing resources, anticipating future demand for the cloud computing resources according to the SLA.

[0157] In at least one embodiment, the workload layer 1308 provides functions for leveraging the cloud computing environment. In at least one embodiment, the workloads and functions that can be provided from this layer include: maps and navigation, software development and management, educational services, data analysis and processing, transaction processing, and service delivery.

[0158] Supercomputing

[0159] The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that can be used to implement at least one embodiment.

[0160] In at least one embodiment, a supercomputer can refer to a hardware system that exhibits significant parallelism and includes at least one chip, where the chips in the system are interconnected via a network and are placed in trays with a hierarchical organization. In at least one embodiment, a large hardware system that fills a computer room with a number of racks is at least one embodiment of a supercomputer, where each rack contains a number of boards / rack modules, and each board / rack module contains a number of chips all interconnected by a scalable network. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits significant parallelism and contains a number of hardware components can also be considered a supercomputer, as the number of hardware components that can be incorporated in a single chip may increase as feature sizes may decrease.

[0161] Figure 14Shows a chip - level supercomputer according to at least one embodiment. In at least one embodiment, inside an FPGA or ASIC chip, the main computation is executed within a finite - state machine (1404) called a thread unit. In at least one embodiment, a task and synchronization network (1402) connects the finite - state machines and is used to dispatch threads and execute operations in the correct order. In at least one embodiment, a memory network (1406, 1410) is used to access a multi - level partitioned on - chip cache hierarchy (1408, 1412). In at least one embodiment, a memory controller (1416) and an off - chip memory network (1414) are used to access off - chip memory. In at least one embodiment, when the design is not suitable for a single logic chip, an I / O controller (1418) is used for cross - chip communication.

[0162] Figure 15 Shows a supercomputer at the rack - module level according to at least one embodiment. In at least one embodiment, within a rack - module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that constitute the main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its adjacent FPGA / ASIC chip using a wide bus on the board with differential high - speed signaling (1506). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high - speed serial communication cable.

[0163] Figure 16 Shows a rack - level supercomputer according to at least one embodiment. Figure 17 Shows a supercomputer at the entire - system level according to at least one embodiment. In at least one embodiment, refer to Figure 16 and Figure 17, between rack modules in a rack and across the racks of an entire system, a scalable, potentially incomplete hypercube network is implemented using high-speed serial optical or copper cables (1602, 1702). In at least one embodiment, one of the FPGA / ASIC chips of the accelerator is connected to the host system (1704) via a PCI-Express connection. In at least one embodiment, the host system includes a host microprocessor (1708) on which the software part of the application runs and a memory consisting of one or more host memory DRAM units (1706) that are consistent with the memory on the accelerator. In at least one embodiment, the host system can be a separate module on one of the racks or can be integrated with one of the modules of a supercomputer. In at least one embodiment, a cube-connected cyclic topology provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a group of FPGA / ASIC chips on a rack module can act as a single hypercube node, such that the total number of external links per group is increased compared to a single chip. In at least one embodiment, the group includes chips A, B, C, and D on a rack module that has an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables connecting the rack module to the outside world. In at least one embodiment, chip A on the rack module is connected to serial communication cables 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, chip D is connected to 9, 10, 11. In at least one embodiment, the entire group {A, B, C, D} that makes up the rack module can form a hypercube node within a supercomputer system, where there are up to 2^12 = 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B using an on-board differential wide bus connection. In at least one embodiment, a message arriving at the group {A, B, C, D} (i.e., arriving at B) on link 4 destined for chip A must also first be routed to the correct destination chip (A) within the group {A, B, C, D}. In at least one embodiment, parallel supercomputer systems of other sizes can also be implemented.

[0164] Artificial Intelligence

[0165] The following figures illustrate, but are not limited to, exemplary artificial intelligence-based systems that can be used to implement at least one embodiment.

[0166] Figure 18AShown is inference and / or training logic 1815 for performing inference and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 1815 are provided below in conjunction with Figure 18A and / or Figure 18B to provide details regarding inference and / or training logic 1815.

[0167] In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, code and / or data storage 1801 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, training logic 1815 may include or be coupled to code and / or data storage 1801 for storing graph code or other software to control timing and / or sequencing, where weight and / or other parameter information will be loaded to configure the logic, including integer and / or floating point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network corresponding to such code. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network that is trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1801 may be included with other on-chip or off-chip data storage devices, including the processor's L1, L2, or L3 cache memory or system memory.

[0168] In at least one embodiment, any portion of code and / or data storage 1801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1801 may be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, the choice of whether code and / or code and / or data storage 1801 is internal or external to the processor, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or some combination of these factors.

[0169] In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to: code and / or data storage 1805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data storage 1805 stores weight parameters and / or input / output data for each layer of the neural network, which is combined with one or more embodiments during the input / output data and / or backpropagation of weight parameters during the training and / or inference using aspects of one or more embodiments. In at least one embodiment, the training logic 1815 may include or be coupled to the code and / or data storage 1805 to store graph code or other software to control timing and / or sequence, where weights and / or other parameter information will be loaded to configure the logic, including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)).

[0170] In at least one embodiment, the code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to such code. In at least one embodiment, any portion of the code and / or data storage 1805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash), or other storage devices. In at least one embodiment, the choice of whether the code and / or data storage 1805 is internal or external to the processor, or includes DRAM, SRAM, flash, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0171] In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 may be separate storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 may be combined storage structures. In at least one embodiment, code and / or data store 1801 and code and / or data store 1805 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data store 1801 and code and / or data store 1805 may be included with other on-chip or off-chip data stores (including the L1, L2, or L3 cache of the processor or system memory).

[0172] In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1810, including integer and / or floating point units, for performing logical and / or mathematical operations at least in part based on training and / or inference code (e.g., graphics code) or as directed by training and / or inference code (e.g., graphics code), the results of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 1820, which is a function of input / output and / or weight parameter data stored in code and / or data store 1801 and / or code and / or data store 1805. In at least one embodiment, the activations stored in activation store 1820 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 1810 in response to executing instructions or other code, where the weight values stored in code and / or data store 1805 and / or data store 1801 are used as operands along with other values (such as bias values, gradient information, momentum values, or other parameters or hyperparameters), any or all of which other values may be stored in code and / or data store 1805 or code and / or data store 1801 or another storage on or off the chip.

[0173] In at least one embodiment, one or more ALUs 1810 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1810 may be external to the processors or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, the ALU 1810 may be included within the execution unit of a processor or otherwise within an ALU library accessible by the execution unit of the processor, where the execution unit of the processor is within the same processor or distributed among different types of different processors (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, the code and / or data storage 1801, the code and / or data storage 1805, and the activation storage 1820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation storage 1820 may be included with other on-chip or off-chip data storage, where the other on-chip or off-chip data storage includes the L1, L2, or L3 cache of the processor or system memory. Additionally, the inference and / or training code may be stored together with other code accessible by the processor or other hardware logic or circuit and using the fetch, decode, schedule, execute, retirement, and / or other logic circuits of the processor to fetch and / or process.

[0174] In at least one embodiment, the activation storage 1820 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash), or other storage devices. In at least one embodiment, the activation storage 1820 may be fully or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation storage 1820 is internal or external to the processor, or in at least one embodiment, or includes DRAM, SRAM, flash, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0175] In at least one embodiment, Figure 18A the inference and / or training logic 1815 shown in may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the TM processing unit from Google, the (e.g., “Lake Crest”) processor. In at least one embodiment, Figure 18A the inference and / or training logic 1815 shown in FIG. may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0176] Figure 18B FIG. shows inference and / or training logic 1815 according to at least one embodiment. In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise combined and used exclusively with weight values or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B the inference and / or training logic 1815 shown in FIG. may be used in conjunction with an application specific integrated circuit (ASIC) such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore, or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 18B the inference and / or training logic 1815 shown in FIG. may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage 1801 and code and / or data storage 1805, which may be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 18B at least one embodiment illustrated in FIG., each of code and / or data storage 1801 and code and / or data storage 1805 is respectively associated with dedicated computing resources (e.g., computing hardware 1802 and computing hardware 1806). In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform only mathematical functions (such as linear algebra functions) on the information stored in code and / or data storage 1801 and code and / or data storage 1805, the results of which are stored in activation storage 1820.

[0177] In at least one embodiment, each of the code and / or data stores 1801 and 1805, and the corresponding computing hardware 1802 and 1806, respectively correspond to different layers of a neural network, such that the result activation from one of the storage / computation pairs 1801 / 1802 in the code and / or data store 1801 and the computing hardware 1802 is provided as an input to the next storage / computation pair 1805 / 1806 in the code and / or data store 1805 and the computing hardware 1806, so as to mirror the conceptual organization of the neural network. In at least one embodiment, each of the storage / computation pairs 1801 / 1802 and 1805 / 1806 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 1815 after or in parallel with the storage / computation pairs 1801 / 1802 and 1805 / 1806.

[0178] Figure 19 Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 1906 is trained using a training data set 1902. In at least one embodiment, the training framework 1904 is the PyTorch framework, while in other embodiments, the training framework 1904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1904 trains the untrained neural network 1906 and enables it to be trained using the processing resources described herein to generate a trained neural network 1908. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, the training may be performed in a supervised, partially supervised, or unsupervised manner.

[0179] In at least one embodiment, a supervised learning is used to train an untrained neural network 1906, where the training dataset 1902 includes inputs paired with expected outputs for the inputs, or where the training dataset 1902 includes inputs with known outputs and the outputs of the neural network 1906 are manually graded. In at least one embodiment, the untrained neural network 1906 is trained in a supervised manner, and the inputs from the training dataset 1902 are processed and the resulting outputs are compared with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1906. In at least one embodiment, the training framework 1904 adjusts the weights controlling the untrained neural network 1906. In at least one embodiment, the training framework 1904 includes tools for monitoring how well the untrained neural network 1906 converges towards a model (such as a trained neural network 1908) that is adapted to generate correct answers (such as results 1914) based on input data (such as a new dataset 1912). In at least one embodiment, the training framework 1904 repeatedly trains the untrained neural network 1906 while using a loss function and an adjustment algorithm (such as stochastic gradient descent) to adjust the weights to refine the output of the untrained neural network 1906. In at least one embodiment, the training framework 1904 trains the untrained neural network 1906 until the untrained neural network 1906 achieves the desired accuracy. In at least one embodiment, the trained neural network 1908 can then be deployed to perform any number of machine learning operations.

[0180] In at least one embodiment, an unsupervised learning is used to train an untrained neural network 1906, where the untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1902 will include input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1906 can learn groupings within the training dataset 1902 and can determine how individual inputs relate to the untrained dataset 1902. In at least one embodiment, the unsupervised training can be used to generate self-organizing maps in the trained neural network 1908 that are useful for performing operations in reducing the dimensionality of a new dataset 1912. In at least one embodiment, the unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 1912 that deviate from the normal patterns of the new dataset 1912.

[0181] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training data set 1902. In at least one embodiment, the training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1908 to adapt to a new data set 1912 without forgetting the knowledge injected into the trained neural network 1408 during initial training.

[0182] 5G network

[0183] The following figures illustrate, but are not limited to, exemplary 5G network-based systems that can be used to implement at least one embodiment.

[0184] Figure 20 The architecture of a system 2000 of a network according to at least one embodiment is shown. In at least one embodiment, system 2000 is shown to include user equipment (UE) 2002 and UE 2004. In at least one embodiment, UE 2002 and 2004 are shown as smart phones (e.g., handheld touchscreen mobile computing devices that can be connected to one or more cellular networks), but can also include any mobile or non-mobile computing device, such as a personal digital assistant (PDA), pager, laptop computer, desktop computer, wireless handheld device, or any computing device including a wireless communication interface.

[0185] In at least one embodiment, any one of UE 2002 and UE 2004 can include an Internet of Things (IoT) UE, which can include a network access layer designed for low-power IoT applications that utilize short-lived UE connections. In at least one embodiment, the IoT UE can utilize techniques such as for exchanging data with an MTC server or device via a public land mobile network (PLMN), proximity-based services (ProSe), or device-to-device (D2D) communication, sensor networks, or IoT networks, such as machine-to-machine (M2M) or machine type communication (MTC). In at least one embodiment, the M2M or MTC data exchange can be machine-initiated data exchange. In at least one embodiment, an IoT network describes interconnected IoT UEs, which can include uniquely identifiable embedded computing devices (within the Internet infrastructure) having short-lived connections. In at least one embodiment, the IoT UE can execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate the connection of the IoT network.

[0186] In at least one embodiment, UEs 2002 and 2004 may be configured to connect (e.g., communicatively couple) to a radio access network (RAN) 2016. In at least one embodiment, the RAN 2016 may be an evolved universal mobile telecommunications system (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN in at least one embodiment. In at least one embodiment, UEs 2002 and 2004 utilize connections 2012 and 2014, respectively, each of which includes a physical communication interface or layer. In at least one embodiment, connections 2012 and 2014 are shown as air interfaces for enabling communicative coupling and may be consistent with cellular communication protocols such as the global system for mobile communications (GSM) protocol, code division multiple access (CDMA) network protocol, push-to-talk (PTT) protocol, cellular PTT (POC) protocol, universal mobile telecommunications system (UMTS) protocol, 3GPP long term evolution (LTE) protocol, fifth generation (5G) protocol, new radio (NR) protocol, and variants thereof.

[0187] In at least one embodiment, UEs 2002 and 2004 may also directly exchange communication data via the ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 may alternatively be referred to as a sidelink interface and includes one or more logical channels, including but not limited to a physical sidelink control channel (PSCCH), a physical sidelink shared channel (PSSCH), a physical sidelink discovery channel (PSDCH), and a physical sidelink broadcast channel (PSBCH).

[0188] In at least one embodiment, UE 2004 is shown as being configured to access an access point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 may include a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, where the AP 2010 will include a Wi-Fi router. In at least one embodiment, the AP 2010 is shown as being connected to the Internet without being connected to the core network of the wireless system.

[0189] In at least one embodiment, RAN 2016 may include one or more access nodes enabling connections 2012 and 2014. In at least one embodiment, these access nodes (ANs) may be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next-generation NodeBs (gNBs), RAN nodes, etc., and may include terrestrial stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographical area (e.g., a cell). In at least one embodiment, RAN 2016 may include one or more RAN nodes for providing macro cells (e.g., macro RAN node 2018) and one or more RAN nodes for providing femto cells or pico cells (e.g., cells having a smaller coverage area, a smaller user capacity, or a higher bandwidth compared to a macro cell) (e.g., low-power (LP) RAN node 2020).

[0190] In at least one embodiment, either of RAN nodes 2018 and 2020 may terminate the air interface protocol and may be the first point of contact for UEs 2002 and 2004. In at least one embodiment, either of RAN nodes 2018 and 2020 may implement various logical functions of RAN 2016, including but not limited to radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling and mobility management.

[0191] In at least one embodiment, UEs 2002 and 2004 may be configured to communicate with each other or with either of RAN nodes 2018 and RAN node 2020 over a multi-carrier communication channel using orthogonal frequency division multiplexing (OFDM) communication signals according to various communication technologies, such as but not limited to orthogonal frequency division multiple access (OFDMA) communication technology (e.g., for downlink communication) or single-carrier frequency division multiple access (SC-FDMA) communication technology (e.g., for uplink and ProSe or sidelink communication), and / or variants thereof. In at least one embodiment, the OFDM signal may include a plurality of orthogonal subcarriers.

[0192] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from either of RAN nodes 2018 and 2020 to UEs 2002 and 2004, and uplink transmissions can utilize similar techniques. In at least one embodiment, the grid can be a time-frequency grid, called a resource grid or a time-frequency resource grid, which is the physical resources in the downlink in each time slot. In at least one embodiment, such a time-frequency plane representation is a common practice in OFDM systems, which makes it intuitive for radio resource allocation. In at least one embodiment, each column and each row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to one time slot in a radio frame. In at least one embodiment, the smallest time-frequency unit in the resource grid is represented as a resource element. In at least one embodiment, each resource grid includes a plurality of resource blocks, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block includes a set of resource elements. In at least one embodiment, in the frequency domain, this can represent the smallest number of resources that can currently be allocated. In at least one embodiment, there are several different physical downlink channels transmitted using such resource blocks.

[0193] In at least one embodiment, the physical downlink shared channel (PDSCH) can carry user data and higher layer signaling to UEs 2002 and 2004. In at least one embodiment, the physical downlink control channel (PDCCH) can carry information such as about the transmission format and resource allocation related to the PDSCH channel. In at least one embodiment, it can also notify UEs 2002 and 2004 of the transmission format, resource allocation, and HARQ (Hybrid Automatic Repeat reQuest) information related to the uplink shared channel. In at least one embodiment, generally, downlink scheduling (allocating control and shared channel resource blocks to UE 2002 within a cell) can be performed at either of RAN nodes 2018 and 2020 based on channel quality information fed back from either of UEs 2002 and 2004. In at least one embodiment, the downlink resource allocation information can be sent on the PDCCH for each of UEs 2002 and 2004 (e.g., allocated to).

[0194] In at least one embodiment, the PDCCH may use control channel elements (CCEs) to transmit control information. In at least one embodiment, before being mapped to resource elements, the PDCCH complex-valued symbols may first be organized into quadruples and then permuted using a sub-block interleaver for rate matching. In at least one embodiment, one or more of these CCEs may be used to transmit each PDCCH, where each CCE may correspond to nine sets of four physical resource elements referred to as resource element groups (REGs). In at least one embodiment, four quadrature phase shift keying (QPSK) symbols may be mapped to each REG. In at least one embodiment, depending on the size of the downlink control information (DCI) and the channel conditions, one or more CCEs may be used to transmit the PDCCH. In at least one embodiment, there may be four or more different PDCCH formats (e.g., aggregation levels, L = 1, 2, 4, or 8) with different numbers of CCEs defined in LTE.

[0195] In at least one embodiment, the enhanced physical downlink control channel (EPDCCH) using PDSCH resources may be used for control information transmission. In at least one embodiment, one or more enhanced control channel elements (ECCEs) may be used to transmit the EPDCCH. In at least one embodiment, each ECCE may correspond to nine sets of four physical resource elements referred to as enhanced resource element groups (EREGs). In at least one embodiment, the ECCE may have other numbers of EREGs in some cases.

[0196] In at least one embodiment, RAN 2016 is shown communicatively coupled to the core network (CN) 2038 via the S1 interface 2022. In at least one embodiment, the CN 2038 may be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, the S1 interface 2022 is divided into two parts: the S1-U interface 2026, which carries traffic data between the RAN nodes 2018 and 2020 and the serving gateway (S-GW) 2030; and the S1-mobility management entity (MME) interface 2024, which is a signaling interface between the RAN nodes 2018 and 2020 and the MME 2028.

[0197] In at least one embodiment, CN 2038 includes a Mobility Management Entity (MME) 2028, a Serving Gateway (S-GW) 2030, a Packet Data Network (PDN) Gateway (P-GW) 2034, and a Home Subscriber Server (HSS) 2032. In at least one embodiment, the MME 2028 can be functionally similar to the control plane of a traditional Serving General Packet Radio Service (GPRS) Support Node (SGSN). In at least one embodiment, the MME 2028 can manage aspects of mobility in access, such as gateway selection and Tracking Area List management. In at least one embodiment, the HSS 2032 can include a database for network users, which includes subscription-related information for supporting network entities to handle communication sessions. In at least one embodiment, CN 2038 can include one or more HSSs 2032, depending on the number of mobile users, the capacity of the devices, the organization of the network, etc. In at least one embodiment, the HSS 2032 can provide support for routing / roaming, authentication, authorization, name / address resolution, location dependency, etc.

[0198] In at least one embodiment, the S-GW 2030 can terminate the S1 interface 2022 towards the Radio Access Network (RAN) 2016 and route data packets between the RAN 2016 and the CN 2038. In at least one embodiment, the S-GW 2030 can be a local mobility anchor for inter-RAN node handover and can also provide an anchor for mobility between 3GPPs. In at least one embodiment, other responsibilities can include lawful interception, charging, and some policy enforcement.

[0199] In at least one embodiment, the P-GW 2034 can terminate the SGi interface towards the PDN. In at least one embodiment, the P-GW 2034 can route data packets between the EPC network 2038 and an external network (such as a network including an Application Server 2040 (or referred to as Application Function (AF))) via an Internet Protocol (IP) interface 2042. In at least one embodiment, the Application Server 2040 can be an element that provides an application using IP bearer resources with a core network (e.g., UMTS Packet Service (PS) domain, LTE PS data service, etc.). In at least one embodiment, the P-GW 2034 is shown communicatively coupled to the Application Server 2040 via the IP communication interface 2042. In at least one embodiment, the Application Server 2040 can also be configured to support one or more communication services (such as Internet Protocol Voice (VoIP) sessions, Push-to-Talk (PTT) sessions, group communication sessions, social network services, etc.) for the UEs 2002 and 2004 via the CN 2038.

[0200] In at least one embodiment, the P-GW 2034 may also be a node for policy enforcement and charging data collection. In at least one embodiment, the Policy and Charging Rules Function (PCRF) 2036 is the policy and charging control element of the CN 2038. In at least one embodiment, in a non-roaming scenario, there may be a single PCRF in the Home Public Land Mobile Network (HPLMN) associated with the Internet Protocol Connectivity Access Network (IP-CAN) session of the UE. In at least one embodiment, in a roaming scenario with local traffic breakout, there may be two PCRFs associated with the IP-CAN session of the UE: a Home PCRF (H-PCRF) within the HPLMN and a Visited PCRF (V-PCRF) within the Visited Public Land Mobile Network (VPLMN). In at least one embodiment, the PCRF 2036 may be communicatively coupled to the application server 2040 via the P-GW 2034. In at least one embodiment, the application server 2040 may signal the PCRF 2036 to indicate a new service flow and select appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, the PCRF 2036 may supply this rule to the Policy and Charging Enforcement Function (PCEF) (not shown) of a QoS class (QCI) with an appropriate Traffic Flow Template (TFT) and identifier, and the PCEF starts the QoS and charging specified by the application server 2040.

[0201] Figure 21 FIG. 2100 shows the architecture of a system 2100 of a network according to some embodiments. In at least one embodiment, the system 2100 is shown to include a UE 2102, a 5G access node or Radio Access Network (RAN) node (shown as (R)AN node 2108), a User Plane Function (shown as UPF 2104), a Data Network (DN 2106), which in at least one embodiment may be an operator service, Internet access, or a third-party service, and a 5G Core Network (5GC) (shown as CN 2110).

[0202] In at least one embodiment, the CN 2110 includes an Authentication Server Function (AUSF 2114); a Core Access and Mobility Management Function (AMF 2112); a Session Management Function (SMF 2118); a Network Exposure Function (NEF 2116); a Policy Control Function (PCF 2122); a Network Function (NF) Repository Function (NRF 2120); a Unified Data Management (UDM 2124); and an Application Function (AF 2126). In at least one embodiment, the CN 2110 may also include other elements not shown, such as a Structured Data Storage Network Function (SDSF), an Unstructured Data Storage Network Function (UDSF), and variations thereof.

[0203] In at least one embodiment, the UPF 2104 can act as an anchor point for mobility within and between RATs, an external PDU session point interconnected to the DN 2106, and a branching point for supporting multi-homed PDU sessions. In at least one embodiment, the UPF 2104 can also perform packet routing and forwarding, packet inspection, enforce the user plane part of policy rules, lawful intercept packets (UP collection); service usage reporting, perform QoS handling for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), perform uplink traffic verification (e.g., SDF to QoS flow mapping), transport-level packet marking in the uplink and downlink, and downlink packet buffering and downlink data notification triggering. In at least one embodiment, the UPF 2104 can include an uplink classifier for supporting routing traffic flows to data networks. In at least one embodiment, the DN 2106 can represent various network operator services, Internet access, or third-party services.

[0204] In at least one embodiment, the AUSF 2114 can store data for the authentication of the UE 2102 and handle functions related to authentication. In at least one embodiment, the AUSF 2114 can facilitate a common authentication framework for various access types.

[0205] In at least one embodiment, the AMF 2112 can be responsible for registration management (e.g., for registering the UE 2102, etc.), connection management, reachability management, mobility management, lawful intercept of AMF-related events, and access authentication and authorization. In at least one embodiment, the AMF 2112 can provide the transmission of SM messages for the SMF 2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, the AMF 2112 can also provide the transmission of short message service (SMS) messages between the UE 2102 and the SMS function (SMSF) ( Figure 21 (not shown). In at least one embodiment, the AMF 2112 can act as a security anchoring function (SEA), which can include interactions with the AUSF 2114 and the UE 2102 and receive the intermediate key established as a result of the UE 2102 authentication process. In at least one embodiment, in the case of using USIM-based authentication, the AMF 2112 can retrieve security material from the AUSF 2114. In at least one embodiment, the AMF 2112 can also include a security context management (SCM) function, which receives the key it uses to derive the access network-specific key from the SEA. Additionally, in at least one embodiment, the AMF 2112 can be a termination point for the RAN CP interface (N2 reference point), a termination point for NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0206] In at least one embodiment, the AMF 2112 may also support NAS signaling with the UE 2102 via the N3 Interworking Function (IWF) interface. In at least one embodiment, the N3IWF may be used to provide access to untrusted entities. In at least one embodiment, the N3IWF may be the termination point for the N2 and N3 interfaces of the control plane and the user plane respectively. Therefore, it can handle N2 signaling from the SMF and the AMF for PDU sessions and QoS, encapsulate / de-encapsulate packets for IPSec and N3 tunnels, mark N3 user plane packets in the uplink, and enforce QoS corresponding to N3 packet marking considering the QoS requirements associated with such marking received via N2. In at least one embodiment, the N3IWF may also relay uplink and downlink control plane NAS (NI) signaling between the UE 2102 and the AMF 2112, and relay uplink and downlink user plane packets between the UE 2102 and the UPF 2104. In at least one embodiment, the N3IWF also provides a mechanism for establishing an IPsec tunnel with the UE 2102.

[0207] In at least one embodiment, the SMF 2118 may be responsible for session management (e.g., session establishment, modification, and release, including tunnel maintenance between the UPF and the AN node); UE IP address allocation and management (including optional authorization); selection and control of the UPF function; configuration of traffic steering at the UPF to route traffic to the appropriate destination; termination of the interface towards the policy control function; the control part of policy enforcement and QoS; lawful interception (for SM events and the interface to the LI system); termination of the SM part of NAS messages; downlink data notification; initiator of AN-specific SM information, which is sent to the AN via the AMF on N2; determination of the SSC mode of the session. In at least one embodiment, the SMF 2118 may include the following roaming functions: handling local enforcement to apply QoS SLAB (VPLMN); charging data collection and charging interface (VPLMN); lawful interception (for SM events in the VPLMN and interface to the LI system); supporting interaction with external DNs to transmit signaling for PDU session authorization / authentication by the external DNs.

[0208] In at least one embodiment, the NEF 2116 may provide means for securely exposing services and capabilities provided by 3GPP network functions to third parties, internal exposure / re-exposure, application functions (e.g., AF 2126), edge computing or fog computing systems, etc. In at least one embodiment, the NEF 2116 may authenticate, authorize, and / or throttle the AF. In at least one embodiment, the NEF 2116 may also transform the information exchanged with the AF 2126 and the information exchanged with internal network functions. In at least one embodiment, the NEF 2116 may transform between AF service identifiers and internal 5GC information. In at least one embodiment, the NEF 2116 may also receive information from other network functions (NFs) based on the exposed capabilities of other network functions. In at least one embodiment, this information may be stored at the NEF 2116 as structured data, or stored at a data storage NF using a standardized interface. In at least one embodiment, the stored information may then be re-exposed by the NEF 2116 to other NFs and AFs, and / or used for other purposes, such as analysis.

[0209] In at least one embodiment, the NRF 2120 may support a service discovery function, receive NF discovery requests from NF instances, and provide information on the discovered NF instances to NF instances. In at least one embodiment, the NRF 2120 also maintains information on available NF instances and the services they support.

[0210] In at least one embodiment, the PCF 2122 may provide policy rules to control plane functions for them to enforce, and may also support a unified policy framework to manage network behavior. In at least one embodiment, the PCF 2122 may also implement a front end (FE) for accessing subscription information related to policy decisions in the UDR of the UDM 2124.

[0211] In at least one embodiment, the UDM 2124 may process subscription-related information to support network entities in handling communication sessions, and may store the subscription data of the UE 2102. In at least one embodiment, the UDM 2124 may include two parts, an application FE and a user data repository (UDR). In at least one embodiment, the UDM may include a UDM FE that is responsible for handling credentials, location management, subscription management, etc. In at least one embodiment, several different front ends may serve the same user in different transactions. In at least one embodiment, the UDM-FE accesses the sub-subscription information stored in the UDR and performs authentication credential processing; user identity processing; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR may interact with the PCF 2122. In at least one embodiment, the UDM 2124 may also support SMS management, where the SMS-FE implements similar application logic as described above.

[0212] In at least one embodiment, AF 2126 may provide application impact on service routing, access to network capability exposure (NCE), and interaction with a policy framework for policy control. In at least one embodiment, NCE may be a mechanism that allows the 5GC and AF 2126 to provide information to each other via the NEF 2116, and the NEF 2116 may be used for edge computing implementation. In at least one embodiment, network operators and third-party services may be hosted near the attachment access point of the UE 2102 to achieve efficient service delivery by reducing end-to-end latency and the load on the transport network. In at least one embodiment, for edge computing implementation, the 5GC may select a UPF 2104 close to the UE 2102 and perform service steering from the UPF 2104 to the DN 2106 via the N6 interface. In at least one embodiment, this may be based on UE subscription data, UE location, and information provided by the AF 2126. In at least one embodiment, the AF 2126 may influence UPF (re)selection and service routing. In at least one embodiment, based on operator deployment, when the AF 2126 is considered a trusted entity, the network operator may allow the AF 2126 to directly interact with relevant NFs.

[0213] In at least one embodiment, the CN 2110 may include an SMSF, which may be responsible for SMS subscription checking and verification and relay SM messages to / from the UE 2102 to / from other entities, such as an SMS-GMSC / IWMSC / SMS router. In at least one embodiment, the SMS may also interact with the AMF 2112 and the UDM 2124 for a notification process that the UE 2102 can use for SMS delivery (e.g., set the UE unreachable flag and notify the UDM 2124 when the UE 2102 is available for SMS).

[0214] In at least one embodiment, the system 2100 may include the following service-based interfaces: Namf: A service-based interface presented by the AMF; Nsmf: A service-based interface presented by the SMF; Nnef: A service-based interface presented by the NEF; Npcf: A service-based interface presented by the PCF; Nudm: A service-based interface presented by the UDM; Naf: A service-based interface presented by the AF; Nnrf: A service-based interface presented by the NRF; and Nausf: A service-based interface presented by the AUSF.

[0215] In at least one embodiment, system 2100 may include the following reference points: N1: the reference point between the UE and the AMF; N2: the reference point between the (R)AN and the AMF; N3: the reference point between the (R)AN and the UPF; N4: the reference point between the SMF and the UPF; and N6: the reference point between the UPF and the data network. In at least one embodiment, there may be more reference points and / or service-based interfaces between the NF services in the NF. However, for clarity, these interfaces and reference points have been omitted. In at least one embodiment, the NS reference point may be between the PCF and the AF; the N7 reference point may be between the PCF and the SMF; the N11 reference point is between the AMF and the SMF, and so on. In at least one embodiment, the CN 2110 may include the Nx interface, which is the inter-CN interface between the MME and the AMF 2112 to enable interworking between the CN 2110 and the CN 7221.

[0216] In at least one embodiment, system 2100 may include multiple RAN nodes (such as the (R)AN node 2108), where an Xn interface is defined between two or more (R)AN nodes 2108 (e.g., gNB) connected to the 5GC 410, between the (R)AN node 2108 (e.g., gNB) connected to the CN 2110 and the eNB (e.g., macro RAN node), and / or between two eNBs connected to the CN 2110.

[0217] In at least one embodiment, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, the Xn-U may provide an unguaranteed delivery of user plane PDUs and support / provide data forwarding and flow control functions. In at least one embodiment, the Xn-C may provide management and error handling functions, functions for managing the Xn-C interface; mobility support for the UE 2102 in the connected mode (e.g., CM-CONNECTED), which includes functions for managing the mobility of the UE in the connected mode between one or more (R)AN nodes 2108. In at least one embodiment, the mobility support may include context transfer from the old (source) serving (R)AN node 2108 to the new (target) serving (R)AN node 2108; and control of the user plane tunnel between the old (source) serving (R)AN node 2108 and the new (target) serving (R)AN node 2108.

[0218] In at least one embodiment, the protocol stack of Xn-U may include a transport network layer built on the Internet Protocol (IP) transport layer and a GTP-U layer for carrying user plane PDUs on top of UDP and / or one or more IP layers. In at least one embodiment, the protocol stack of Xn-C may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on the SCTP layer. In at least one embodiment, the SCTP layer may be on top of the IP layer. In at least one embodiment, the SCTP layer provides guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, the protocol stack of Xn-U and / or the protocol stack of Xn-C may be the same as or similar to the user plane and / or control plane protocol stacks shown and described herein.

[0219] Figure 22 is an illustration of a control plane protocol stack according to some embodiments. In at least one embodiment, the control plane 2200 is shown as a communication protocol stack between the UE 2002 (or alternatively, the UE 2004), the RAN 2016, and the MME 2028.

[0220] In at least one embodiment, the PHY layer 2202 may send or receive information used by the MAC layer 2204 via one or more air interfaces. In at least one embodiment, the PHY layer 2202 may also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers (e.g., the RRC layer 2210). In at least one embodiment, the PHY layer 2202 may further perform error detection on the transport channel, forward error correction (FEC) encoding / decoding of the transport channel, modulation / demodulation of the physical channel, interleaving, rate matching, mapping to the physical channel, and multiple input multiple output (MIMO) antenna processing.

[0221] In at least one embodiment, the MAC layer 2204 may perform mapping between logical channels and transport channels, multiplex MAC service data units (SDUs) from one or more logical channels onto transport blocks (TBs) to be delivered to the PHY via the transport channel, demultiplex MAC SDUs from the transport blocks (TBs) delivered from the PHY via the transport channel onto one or more logical channels, multiplex MAC SDUs onto TBs, scheduling information reporting, error correction via hybrid automatic repeat request (HARD), and logical channel prioritization.

[0222] In at least one embodiment, the RLC layer 2206 can operate in multiple operation modes, including: Transparent Mode (TM), Unacknowledged Mode (UM), and Acknowledged Mode (AM). In at least one embodiment, the RLC layer 2206 can perform the transmission of upper layer protocol data units (PDUs), error correction through Automatic Repeat reQuest (ARQ) for AM data transmission, and concatenation, segmentation, and reassembly of RLC service data units (SDUs) for UM and AM data transmission. In at least one embodiment, the RLC layer 2206 can also perform resegmentation of RLC data PDUs for AM data transmission, reordering of RLC data PDUs for UM and AM data transmission, detection of duplicate data for UM and AM data transmission, discarding of RLC SDUs for UM and AM data transmission, detection of protocol errors for AM data transmission, and perform RLC re-establishment.

[0223] In at least one embodiment, the PDCP layer 2208 can perform header compression and decompression of IP data, maintain the PDCP sequence number (SN), perform in-sequence delivery of higher layer PDUs when reconstructing lower layers, eliminate duplication of lower layer SDUs when reconstructing lower layers for radio bearers mapped on RLC AM, encrypt and decrypt control plane data, perform integrity protection and integrity verification on control plane data, discard data based on a control timer, and perform security operations (e.g., encryption, decryption, integrity protection, integrity verification, etc.).

[0224] In at least one embodiment, the main services and functions of the RRC layer 2210 can include broadcasting of system information (e.g., included in the Master Information Block (MIB) or System Information Blocks (SIBs) related to the Non-Access Stratum (NAS)), broadcasting of system information related to the Access Stratum (AS), paging, establishment, maintenance, and release of the RRC connection between the UE and the E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance, and release of point-to-point radio bearers, security functions including key management, Radio Access Technology (RAT) inter-system mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, the MIB and SIB can include one or more Information Elements (IEs), and each information element can include individual data fields or data structures.

[0225] In at least one embodiment, the UE 2002 and the RAN 2016 can utilize the Uu interface (e.g., the LTE-Uu interface) to exchange control plane data via a protocol stack including the PHY layer 2202, the MAC layer 2204, the RLC layer 2206, the PDCP layer 2208, and the RRC layer 2210.

[0226] In at least one embodiment, the Non-Access Stratum (NAS) protocol (NAS protocol 2212) forms the top layer of the control plane between the UE 2002 and the MME 2028. In at least one embodiment, the NAS protocol 2212 supports the mobility and session management procedures of the UE 2002 to establish and maintain an IP connection between the UE 2002 and the P-GW 2034.

[0227] In at least one embodiment, the Signaling Radio Access Network Application Part (Si-AP) layer (Si-AP layer 2222) may support the functions of the Si interface and include Elementary Procedures (EPs). In at least one embodiment, the EPs are the interaction units between the RAN 2016 and the CN 2028. In at least one embodiment, the S1-AP layer services may include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including but not limited to: Evolved Universal Terrestrial Radio Access Network (E-UTRAN) Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transmission, Radio Access Network Information Management (RIM), and configuration transfer.

[0228] In at least one embodiment, the Stream Control Transmission Protocol (SCTP) layer (alternatively referred to as the Stream Control Transmission Protocol / Internet Protocol (SCTP / IP) layer) (SCTP layer 2220) may ensure the reliable delivery of signaling messages between the RAN 2016 and the MME 2028, partially based on the IP protocol supported by the IP layer 2218. In at least one embodiment, the L2 layer 2216 and the L1 layer 2214 may refer to the communication links (e.g., wired or wireless) used by the RAN nodes and the MME to exchange information.

[0229] In at least one embodiment, the RAN 2016 and one or more MMEs 2028 may utilize the S1-MME interface to exchange control plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the IP layer 2218, the SCTP layer 2220, and the Si-AP layer 2222.

[0230] Figure 23 is a diagram of a user plane protocol stack according to at least one embodiment. In at least one embodiment, the user plane 2300 is shown as a communication protocol stack between the UE 2002, the RAN 2016, the Serving Gateway (S-GW) 2030, and the Packet Data Network Gateway (P-GW) 2034. In at least one embodiment, the user plane 2300 may utilize the same protocol layers as the control plane 2200. In at least one embodiment, the UE 2002 and the RAN 2016 may utilize the Uu interface (e.g., the LTE-Uu interface) to exchange user plane data via a protocol stack including the Physical (PHY) layer 2202, the Medium Access Control (MAC) layer 2204, the Radio Link Control (RLC) layer 2206, and the Packet Data Convergence Protocol (PDCP) layer 2208.

[0231] In at least one embodiment, the General Packet Radio Service (GPRS) Tunneling Protocol (GTP-U) layer (GTP-U layer 2304) for the user plane can be used to carry user data within the GPRS core network and between the radio access network and the core network. In at least one embodiment, the user data transmitted can be packets in any format of IPv4, IPv6, or PPP format. In at least one embodiment, the User Datagram Protocol and Internet Protocol Security (UDP / IP) layer (UDP / IP layer 2302) can provide a checksum for data integrity, port numbers for different functions in source and destination addressing, and encryption and authentication for selected data streams. In at least one embodiment, the RAN 2016 and the S-GW 2030 can utilize the S1-U interface to exchange user plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the UDP / IP layer 2302, and the GTP-U layer 2304. In at least one embodiment, the S-GW 2030 and the P-GW 2034 can utilize the S5 / S8a interface to exchange user plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the UDP / IP layer 2302, and the GTP-U layer 2304. In at least one embodiment, as discussed above with respect to Figure 22 the NAS protocol supports the mobility and session management processes of the UE 2002 to establish and maintain an IP connection between the UE 2002 and the P-GW 2034.

[0232] Figure 24 Components 2400 of a core network according to at least one embodiment are shown. In at least one embodiment, the components of the CN 2038 can be implemented in one physical node or separate physical nodes, the separate physical nodes including components for reading and executing instructions from a machine-readable medium or a computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, Network Function Virtualization (NFV) is used to virtualize any or all of the above network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). In at least one embodiment, the logical instantiation of the CN 2038 can be referred to as a network slice 2402 (e.g., the network slice 2402 is shown as including the HSS 2032, the MME 2028, and the S-GW 2030). In at least one embodiment, the logical instantiation of a part of the CN 2038 can be referred to as a network sub-slice 2404 (e.g., the network sub-slice 2404 is shown as including the P-GW 2034 and the PCRF 2036).

[0233] In at least one embodiment, an NFV architecture and infrastructure can be used to virtualize one or more network functions onto physical resources including a combination of industry standard server hardware, storage hardware, or switches, where the network functions would otherwise be performed by dedicated hardware. In at least one embodiment, an NFV system can be used to perform a virtual or reconfigurable implementation of one or more EPC components / functions.

[0234] Figure 25 FIG. 2500 is a block diagram illustrating components of a system 2500 for supporting network function virtualization (NFV) according to at least one embodiment. In at least one embodiment, system 2500 is shown to include a virtualization infrastructure manager (shown as VIM 2502), a network function virtualization infrastructure (shown as NFVI 2504), a VNF manager (shown as VNFM 2506), virtualized network functions (shown as VNF 2508), an element manager (shown as EM 2510), an NFV coordinator (shown as NFVO 2512), and a network manager (shown as NM 2514).

[0235] In at least one embodiment, VIM 2502 manages the resources of NFVI 2504. In at least one embodiment, NFVI 2504 can include physical or virtual resources and applications (including hypervisors) for executing system 2500. In at least one embodiment, VIM 2502 can utilize NFVI 2504 to manage the lifecycle of virtual resources (e.g., creation, maintenance, and tear-down of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, faults, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0236] In at least one embodiment, VNFM 2506 can manage VNF 2508. In at least one embodiment, VNF 2508 can be used to perform EPC components / functions. In at least one embodiment, VNFM 2506 can manage the lifecycle of VNF 2508 and track the performance, faults, and security of the virtual aspects of VNF 2508. In at least one embodiment, EM 2510 can track the performance, faults, and security of the functional aspects of VNF 2508. In at least one embodiment, tracking data from VNFM 2506 and EM 2510 can include, in at least one embodiment, performance measurement (PM) data used by VIM 2502 or NFVI 2504. In at least one embodiment, both VNFM 2506 and EM 2510 can scale the number of VNFs of system 2500 up / down.

[0237] In at least one embodiment, the NFVO 2512 may coordinate, authorize, release, and occupy resources of the NFVI 2504 to provide the requested services (e.g., to perform EPC functions, components, or slices). In at least one embodiment, the NM 2514 may provide end-user function packages responsible for managing a network, which may include network elements with VNFs, non-virtualized network functions, or both (management of VNFs may occur via the EM 2510).

[0238] Computer-based system

[0239] The following figures present, but are not limited to, exemplary computer-based systems that may be used to implement at least one embodiment.

[0240] Figure 26 A processing system 2600 according to at least one embodiment is shown. In at least one embodiment, the system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and may be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2602 or processor cores 2607. In at least one embodiment, the processing system 2600 is a processing platform integrated within a system-on-chip (SoC) integrated circuit for mobile, handheld, or embedded devices.

[0241] In at least one embodiment, the processing system 2600 may be included in or incorporated into a server-based gaming platform, including a game console such as a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 2600 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 2600 may also be coupled to or integrated within a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0242] In at least one embodiment, each of one or more processors 2602 includes one or more processor cores 2607 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2607 is configured to process a particular instruction set 2609. In at least one embodiment, the instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions that help to emulate other instruction sets. In at least one embodiment, processor core 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0243] In at least one embodiment, processor 2602 includes a cache memory 2604. In at least one embodiment, processor 2602 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among the various components of processor 2602. In at least one embodiment, processor 2602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share the logic among processor cores 2607 using known cache coherence techniques. In at least one embodiment, a register file 2606 is further included in processor 2602, and processor 2602 can include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2606 can include general-purpose registers or other registers.

[0244] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transfer communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610 can be a processor bus, such as a version of the Direct Media Interface (DMI) bus, in one embodiment. In at least one embodiment, the interface bus 2610 is not limited to the DMI bus and can include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a Platform Controller Hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between the storage device and other components of the processing system 2600, while the Platform Controller Hub (PCH) 2630 provides connections to input / output (I / O) devices via a local I / O bus.

[0245] In at least one embodiment, the memory device 2620 can be a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a flash memory device, a Phase Change Memory device, or have suitable performance to be used as processor memory. In at least one embodiment, the storage device 2620 can be used as the system memory of the processing system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute an application or process. In at least one embodiment, the memory controller 2616 is also coupled to an optional external graphics processor 2612, which can communicate with one or more graphics processors 2608 in the processor 2602 to perform graphics and media operations. In at least one embodiment, a display device 2611 can be connected to the processor 2602. In at least one embodiment, the display device 2611 can include one or more of an internal display device, such as in a mobile electronic device or a portable computer device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2611 can include a Head-Mounted Display (HMD), such as a stereoscopic display device for Virtual Reality (VR) applications or Augmented Reality (AR) applications.

[0246] In at least one embodiment, the platform controller hub 2630 enables peripheral devices to be connected to the storage device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include but are not limited to an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, a touch sensor 2625, and a data storage device 2624 (e.g., a hard disk drive, a flash memory, etc.). In at least one embodiment, the data storage device 2624 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2625 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2628 enables communication with the system firmware, and in at least one embodiment, it can be a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 2634 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2610. In at least one embodiment, the audio controller 2646 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 2600. In at least one embodiment, the platform controller hub 2630 can also be connected to one or more Universal Serial Bus (USB) controllers 2642, which connect input devices, such as a keyboard and mouse 2643 combination, a camera 2644, or other USB input devices.

[0247] In at least one embodiment, instances of the memory controller 2616 and the platform controller hub 2630 can be integrated into a discrete external graphics processor, such as the external graphics processor 2612. In at least one embodiment, the platform controller hub 2630 and / or the storage controller 2616 can be external to one or more processors 2602. In at least one embodiment, the processing system 2600 can include an external storage controller 2616 and a platform controller hub 2630, which can be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2602.

[0248] Figure 27FIG. 2700 shows a computer system 2700 according to at least one embodiment. In at least one embodiment, the computer system 2700 may be a system with interconnected devices and components, a SOC, or some combination. In at least one embodiment, the computer system 2700 is formed by a processor 2702, which may include execution units for executing instructions. In at least one embodiment, the computer system 2700 may include, but is not limited to, components such as the processor 2702, which employs execution units including logic to execute algorithms for processing data. In at least one embodiment, the computer system 2700 may include a processor, such as a processor family, XeonTM, XScaleTM, and / or StrongARMTM Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 2700 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces may also be used.

[0249] In at least one embodiment, the computer system 2700 may be used in other devices, such as handheld devices and embedded applications. Some of at least one embodiment of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors (“DSPs”), SoCs, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may execute one or more instructions according to at least one embodiment.

[0250] In at least one embodiment, the computer system 2700 may include, but is not limited to, a processor 2702, which may include, but is not limited to, one or more execution units 2708, which may be configured to execute Compute Unified Device Architecture (“CUDA”) ( (Developed by NVIDIA Corporation, Santa Clara, California) program. In at least one embodiment, the CUDA program is at least a part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 2700 is a single-processor desktop or server system. In at least one embodiment, the computer system 2700 can be a multi-processor system. In at least one embodiment, the processor 2702 can include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing an instruction set combination, or any other processor device, and in at least one embodiment, such as a digital signal processor. In at least one embodiment, the processor 2702 can be coupled to a processor bus 2710, which can transfer data signals between the processor 2702 and other components in the computer system 2700.

[0251] In at least one embodiment, the processor 2702 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 2704. In at least one embodiment, the processor 2702 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside outside the processor 2702. In at least one embodiment, the processor 2702 can include a combination of internal and external caches. In at least one embodiment, the register file 2706 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0252] In at least one embodiment, an execution unit 2708, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 2702. The processor 2702 can also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode for certain macro instructions. In at least one embodiment, the execution unit 2708 can include logic for processing a packet instruction set 2709. In at least one embodiment, by including the packet instruction set 2709 in the instruction set of the general-purpose processor 2702 and the associated circuitry for the instructions to be executed, operations used by many multimedia applications can be performed using the packet data in the general-purpose processor 2702. In at least one embodiment, operations can be performed on the packet data by using the full width of the processor's data bus to accelerate and more efficiently execute many multimedia applications, which may not require transferring smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0253] In at least one embodiment, execution unit 2708 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, computer system 2700 may include, but is not limited to, memory 2720. In at least one embodiment, memory 2720 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage devices. Memory 2720 may store instructions 2719 and / or data 2721 represented by data signals that may be executed by processor 2702.

[0254] In at least one embodiment, the system logic chip may be coupled to processor bus 2710 and memory 2720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 2716, and processor 2702 may communicate with MCH 2716 via processor bus 2710. In at least one embodiment, MCH 2716 may provide a high-bandwidth memory path 2718 to memory 2720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2716 may initiate data signals among processor 2702, memory 2720, and other components in computer system 2700, and may bridge data signals among processor bus 2710, memory 2720, and system I / O 2722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2716 may be coupled to memory 2720 via high-bandwidth memory path 2718, and graphics / video card 2712 may be coupled to MCH 2716 via an Accelerated Graphics Port (“AGP”) interconnect 2714.

[0255] In at least one embodiment, the computer system 2700 may use the system I / O 2722 as a proprietary hub interface bus to couple the MCH 2716 to an I / O controller hub (“ICH”) 2730. In at least one embodiment, the ICH 2730 may provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 2720, the chipset, and the processor 2702. Examples may include, but are not limited to, an audio controller 2729, a firmware hub (“Flash BIOS”) 2728, a wireless transceiver 2726, a data storage 2724, a legacy I / O controller 2723 that includes user input 2725 and a keyboard interface, a serial expansion port 2777 (e.g., USB), and a network controller 2734. The data storage 2724 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage devices.

[0256] In at least one embodiment, Figure 27 A system including interconnected hardware devices or “chips” is shown. In at least one embodiment, Figure 27 An exemplary SoC may be shown. In at least one embodiment, Figure 27 The devices shown in may be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the system 2700 use a Compute Express Link (CXL) interconnect to interconnect.

[0257] Figure 28 System 2800 according to at least one embodiment is shown. In at least one embodiment, system 2800 is an electronic device that utilizes a processor 2810. In at least one embodiment, system 2800 may be, in at least one embodiment but not limited to, a laptop computer, a tower server, a rack server, a blade server, a notebook computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0258] In at least one embodiment, system 2800 may include, but is not limited to, a processor 2810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 2810 is coupled using a bus or interface, such as an I2C bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high definition audio (“HDA”) bus, a serial advanced technology attachment (“SATA”) bus, a USB (version 1, 2, 3), or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment,Figure 28 illustrates a system that includes interconnected hardware devices or “chips”. In at least one embodiment, Figure 28 an exemplary SoC may be shown. In at least one embodiment, Figure 28 the devices shown therein may be interconnected with proprietary interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 28 one or more components of are interconnected using Compute Express Link (CXL) interconnects.

[0259] In at least one embodiment, Figure 28 it may include a display 2824, a touch screen 2825, a touchpad 2830, a Near Field Communication unit (“NFC”) 2845, a sensor hub 2840, a thermal sensor 2846, an Embedded Controller (“EC”) 2835, a Trusted Platform Module (“TPM”) 2838, BIOS / Firmware / Flash (“BIOS, FW Flash”) 2822, a DSP 2860, a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”) 2820, a Wireless Local Area Network unit (“WLAN”) 2850, a Bluetooth unit 2852, a Wireless Wide Area Network unit (“WWAN”) 2856, a Global Positioning System (GPS) 2855, a camera (“USB 3.0 camera”) 2854 (e.g., a USB3.0 camera), or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 2815 implemented to the LPDDR3 standard in at least one embodiment. These components may each be implemented in any suitable manner.

[0260] In at least one embodiment, other components may be communicatively coupled to the processor 2810 via the components discussed above. In at least one embodiment, an accelerometer 2841, an ambient light sensor (“ALS”) 2842, a compass 2843, and a gyroscope 2844 may be communicatively coupled to the sensor hub 2840. In at least one embodiment, a thermal sensor 2839, a fan 2837, a keyboard 2846, and a touchpad 2830 may be communicatively coupled to the EC 2835. In at least one embodiment, a speaker 2863, headphones 2864, and a microphone (“mic”) 2865 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 2864, which may in turn be communicatively coupled to the DSP 2860. In at least one embodiment, the audio unit 2864 may include, but is not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a subscriber identity module (“SIM”) 2857 may be communicatively coupled to the WWAN unit 2856. In at least one embodiment, components such as the WLAN unit 2850, the Bluetooth unit 2852, and the WWAN unit 2856 may be implemented in a next-generation form factor (NGFF).

[0261] Figure 29 An exemplary integrated circuit 2900 is shown in accordance with at least one embodiment. In at least one embodiment, the exemplary integrated circuit 2900 is a system-on-a-chip (SoC) that may be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and may additionally include an image processor 2915 and / or a video processor 2920, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 2900 includes peripheral or bus logic that includes a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I2S / I2C controller 2940. In at least one embodiment, the integrated circuit 2900 may include a display device 2945 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2950 and a mobile industry processor interface (MIPI) display interface 2955. In at least one embodiment, storage may be provided by a flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits further include an embedded security engine 2970.

[0262] Figure 30FIG. 3000 shows a computing system 3000 according to at least one embodiment. In at least one embodiment, the computing system 3000 includes a processing subsystem 3001 having one or more processors 3002 and a system memory 3004 that communicate via an interconnect path that may include a memory hub 3005. In at least one embodiment, the memory hub 3005 may be a separate component within a chipset component or may be integrated within one or more processors 3002. In at least one embodiment, the memory hub 3005 is coupled to an I / O subsystem 3011 via a communication link 3006. In at least one embodiment, the I / O subsystem 3011 includes an I / O hub 3007 that enables the computing system 3000 to receive input from one or more input devices 3008. In at least one embodiment, the I / O hub 3007 enables a display controller, which is included in one or more processors 3002, to provide output to one or more display devices 3010A. In at least one embodiment, one or more display devices 3010A coupled to the I / O hub 3007 may include local, internal, or embedded display devices.

[0263] In at least one embodiment, the processing subsystem 3001 includes one or more parallel processors 3012 coupled to the memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, the communication link 3013 may be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 3012 form a parallel or vector processing system in a computing cluster that may include a large number of processing cores and / or processing clusters, such as a Many Integrated Core (MIC) processor. In at least one embodiment, one or more parallel processors 3012 form a graphics processing subsystem that can output pixels to one of the one or more display devices 3010A coupled via the I / O hub 3007. In at least one embodiment, one or more parallel processors 3012 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 3010B.

[0264] In at least one embodiment, the system storage unit 3014 can be connected to the I / O hub 3007 to provide a storage mechanism for the computing system 3000. In at least one embodiment, the I / O switch 3016 can be used to provide an interface mechanism to enable connections between the I / O hub 3007 and other components, such as a network adapter 3018 and / or a wireless network adapter 3019 that can be integrated into the platform, and various other devices that can be added via one or more additional devices 3020. In at least one embodiment, the network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices that include one or more radios.

[0265] In at least one embodiment, the computing system 3000 can include other components not explicitly shown, including USB or other port connections, an optical storage drive, a video capture device, and / or variants thereof, which can also be connected to the I / O hub 3007. In at least one embodiment, Figure 30 the communication paths interconnecting the various components can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0266] In at least one embodiment, one or more parallel processors 3012 include circuitry optimized for graphics and video processing (in at least one embodiment, including video output circuitry) and constitute a Graphics Processing Unit (GPU). In at least one embodiment, one or more parallel processors 3012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computing system 3000 can be integrated with one or more other system elements on a single integrated circuit. In at least one embodiment, one or more parallel processors 3012, the memory hub 3005, the processor 3002, and the I / O hub 3007 can be integrated into a System-on-Chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 3000 can be integrated into a single package to form a System-in-Package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 3000 can be integrated into a Multi-Chip Module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, the I / O subsystem 3011 and the display device 3010B are omitted from the computing system 3000.

[0267] Processing system

[0268] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0269] Figure 31 An Accelerated Processing Unit (“APU”) 3100 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 3100 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, the APU 3100 can be configured to execute applications such as CUDA programs. In at least one embodiment, the APU 3100 includes, but is not limited to, a Core Complex 3110, a Graphics Complex 3140, a fabric 3160, an I / O interface 3170, a Memory Controller 3180, a Display Controller 3192, and a Multimedia Engine 3194. In at least one embodiment, the APU 3100 can include any combination of any number of Core Complexes 3110, any number of Graphics Complexes 3140, any number of Display Controllers 3192, and any number of Multimedia Engines 3194. For illustrative purposes, multiple instances of similar objects are denoted by reference numerals herein, where the reference numeral identifies the object and the number in parentheses identifies the instance desired.

[0270] In at least one embodiment, the Core Complex 3110 is a CPU, the Graphics Complex 3140 is a GPU, and the APU 3100 is a processing unit that integrates, but is not limited to, 3110 and 3140 onto a single chip. In at least one embodiment, some tasks can be assigned to the Core Complex 3110 while other tasks can be assigned to the Graphics Complex 3140. In at least one embodiment, the Core Complex 3110 is configured to execute the main control software associated with the APU 3100, such as an operating system. In at least one embodiment, the Core Complex 3110 is the main processor of the APU 3100 that controls and coordinates the operation of other processors. In at least one embodiment, the Core Complex 3110 issues commands that control the operation of the Graphics Complex 3140. In at least one embodiment, the Core Complex 3110 can be configured to execute host-executable code derived from CUDA source code, and the Graphics Complex 3140 can be configured to execute device-executable code derived from CUDA source code.

[0271] In at least one embodiment, the Core Complex 3110 includes, but is not limited to, cores 3120(1)-3120(4) and an L3 cache 3130. In at least one embodiment, the Core Complex 3110 can include any combination of any number of cores 3120 and any number and type of caches. In at least one embodiment, the cores 3120 are configured to execute instructions of a particular Instruction Set Architecture (“ISA”). In at least one embodiment, each core 3120 is a CPU core.

[0272] In at least one embodiment, each core 3120 includes, but is not limited to, a fetch / decode unit 3122, an integer execution engine 3124, a floating point execution engine 3126, and an L2 cache 3128. In at least one embodiment, the fetch / decode unit 3122 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 3124 and the floating point execution engine 3126. In at least one embodiment, the fetch / decode unit 3122 can dispatch one micro-instruction to the integer execution engine 3124 and another micro-instruction to the floating point execution engine 3126 simultaneously. In at least one embodiment, the integer execution engine 3124 performs operations including, but not limited to, integer and memory operations. In at least one embodiment, the floating point engine 3126 performs operations including, but not limited to, floating point and vector operations. In at least one embodiment, the fetch-decode unit 3122 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 3124 and the floating point execution engine 3126.

[0273] In at least one embodiment, each core 3120(i) can access the L2 cache 3128(i) included in the core 3120(i), where i is an integer representing a particular instance of the core 3120. In at least one embodiment, each core 3120 included in the core complex 3110(j) is connected to other cores 3120 included in the core complex 3110(j) via the L3 cache 3130(j) included in the core complex 3110(j), where j is an integer representing a particular instance of the core complex 3110. In at least one embodiment, the cores 3120 included in the core complex 3110(j) can access all of the L3 caches 3130(j) included in the core complex 3110(j), where j is an integer representing a particular instance of the core complex 3110. In at least one embodiment, the L3 cache 3130 can include, but is not limited to, any number of slices.

[0274] In at least one embodiment, the graphics complex 3140 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 3140 is configured to perform graphics pipeline operations such as draw commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 3140 is configured to perform operations that are not related to graphics. In at least one embodiment, the graphics complex 3140 is configured to perform both operations related to graphics and operations not related to graphics.

[0275] In at least one embodiment, the graphics complex 3140 includes, but is not limited to, any number of compute units 3150 and an L2 cache 3142. In at least one embodiment, the compute units 3150 share the L2 cache 3142. In at least one embodiment, the L2 cache 3142 is partitioned. In at least one embodiment, the graphics complex 3140 includes, but is not limited to, any number of compute units 3150 and any number (including zero) and type of caches. In at least one embodiment, the graphics complex 3140 includes, but is not limited to, any number of dedicated graphics hardware.

[0276] In at least one embodiment, each compute unit 3150 includes, but is not limited to, any number of SIMD units 3152 and a shared memory 3154. In at least one embodiment, each SIMD unit 3152 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 3150 can execute any number of thread blocks, but each thread block is executed on a single compute unit 3150. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3152 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can synchronize together and communicate via the shared memory 3154.

[0277] In at least one embodiment, the fabric 3160 is a system interconnect that facilitates data and control transfers across the core complex 3110, graphics complex 3140, I / O interfaces 3170, memory controller 3180, display controller 3192, and multimedia engine 3194. In at least one embodiment, in addition to or instead of the fabric 3160, the APU 3100 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to the APU 3100. In at least one embodiment, the I / O interfaces 3170 represent any number and type of I / O interfaces (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to the I / O interfaces 3170. In at least one embodiment, the peripheral devices coupled to the I / O interfaces 3170 may include, but are not limited to, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0278] In at least one embodiment, the display controller AMD92 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 3180 facilitates data transfers between the APU 3100 and the unified system memory 3190. In at least one embodiment, the core complex 3110 and the graphics complex 3140 share the unified system memory 3190.

[0279] In at least one embodiment, the APU 3100 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 3100 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which may be component-private or shared among any number of components (e.g., cores 3120, core complex 3110, SIMD units 3152, compute units 3150, and graphics complex 3140).

[0280] Figure 32Shows a CPU 3200 according to at least one embodiment. In at least one embodiment, the CPU 3200 is developed by AMD Corporation, Santa Clara, California. In at least one embodiment, the CPU 3200 can be configured to execute application programs. In at least one embodiment, the CPU 3200 is configured to execute main control software, such as an operating system. In at least one embodiment, the CPU 3200 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 3200 can be configured to execute host-executable code derived from CUDA source code, and the external GPU can be configured to execute device-executable code derived from such CUDA source code. In at least one embodiment, the CPU 3200 includes, but is not limited to, any number of core complexes 3210, a structure 3260, an I / O interface 3270, and a memory controller 3280.

[0281] In at least one embodiment, the core complex 3210 includes, but is not limited to, cores 3220(1)-3220(4) and an L3 cache 3230. In at least one embodiment, the core complex 3210 can include, but is not limited to, any number of cores 3220 and any combination of any number and type of caches. In at least one embodiment, the cores 3220 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 3220 is a CPU core.

[0282] In at least one embodiment, each core 3220 includes, but is not limited to, a fetch / decode unit 3222, an integer execution engine 3224, a floating-point execution engine 3226, and an L2 cache 3228. In at least one embodiment, the fetch / decode unit 3222 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 3224 and the floating-point execution engine 3226. In at least one embodiment, the fetch / decode unit 3222 can dispatch one micro-instruction to the integer execution engine 3224 and another micro-instruction to the floating-point execution engine 3226 simultaneously. In at least one embodiment, the integer execution engine 3224 executes operations not limited to integers and memory. In at least one embodiment, the floating-point engine 3226 executes operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 3222 dispatches micro-instructions to a single execution engine that replaces both the integer execution engine 3224 and the floating-point execution engine 3226.

[0283] In at least one embodiment, each core 3220(i) can access the L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a specific instance of the core 3220. In at least one embodiment, each core 3220 included in the core complex 3210(j) is connected to other cores 3220 in the core complex 3210(j) via the L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a specific instance of the core complex 3210. In at least one embodiment, the cores 3220 included in the core complex 3210(j) can access all the L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a specific instance of the core complex 3210. In at least one embodiment, the L3 cache 3230 can include, but is not limited to, any number of slices.

[0284] In at least one embodiment, the structure 3260 is a system interconnect that facilitates data and control transfer across the core complexes 3210(1)-3210(N) (where N is an integer greater than zero), the I / O interfaces 3270, and the memory controller 3280. In at least one embodiment, in addition to or instead of the structure 3260, the CPU 3200 can also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfer across any number and type of directly or indirectly linked components that can be internal or external to the CPU 3200. In at least one embodiment, the I / O interface 3270 represents any number and type of I / O interfaces (such as PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to the I / O interface 3270. In at least one embodiment, the peripheral devices coupled to the I / O interface 3270 can include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other types of game controllers, a media recording device, an external storage device, a network interface card, etc.

[0285] In at least one embodiment, the memory controller 3280 facilitates data transfer between the CPU 3200 and the system memory 3290. In at least one embodiment, the core complex 3210 and the graphics complex 3240 share the system memory 3290. In at least one embodiment, the CPU 3200 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3280 and memory devices that may be dedicated to one component or shared among multiple components. In at least one embodiment, the CPU 3200 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which may be component-private or shared among any number of components (e.g., cores 3220 and core complex 3210).

[0286] Figure 33 An exemplary accelerator integration slice 3390 is shown in accordance with at least one embodiment. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines among a plurality of graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0287] The application virtual address space 3382 within the system memory 3314 stores process elements 3383. In one embodiment, the process elements 3383 are stored in response to a GPU call 3381 from an application 3380 executing on the processor 3307. The process elements 3383 contain the processing state of the corresponding application 3380. The work descriptor (WD) 3384 contained in the process element 3383 may be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 3384 is a pointer to a job request queue within the application virtual address space 3382.

[0288] The graphics acceleration module 3346 and / or the individual graphics processing engines may be shared by all or some of the processes in the system. In at least one embodiment, an infrastructure may be included for establishing the processing state and sending the WD 3384 to the graphics acceleration module 3346 to start a job in a virtualized environment.

[0289] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 3346 or an individual graphics processing engine. Since the graphics acceleration module 3346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and when the graphics acceleration module 3346 is allocated, the operating system initializes the accelerator integrated circuit for the owning partition.

[0290] In operation, the WD fetch unit 3391 in the accelerator integrated slice 3390 fetches the next WD 3384, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 3346. Data from the WD 3384 can be stored in the register 3345 and used by the memory management unit (MMU) 3339, the interrupt management circuit 3347, and / or the context management circuit 3348, as shown. At least one embodiment of the MMU 3339 includes a segment / page walk circuit for accessing the segment / page table 3386 within the OS virtual address space 3385. The interrupt management circuit 3347 can process interrupt events (INT) 3392 received from the graphics acceleration module 3346. When performing a graphics operation, the effective address 3393 generated by the graphics processing engine is translated to a physical address by the MMU 3339.

[0291] In one embodiment, the same register set 3345 is replicated for each graphics processing engine and / or graphics acceleration module 3346 and can be initialized by the hypervisor or the operating system. Each of these replicated registers can be included in the accelerator integrated slice 3390. Exemplary registers that can be initialized by the hypervisor are shown in Table 1.

[0292] Table 1 - Registers Initialized by the Hypervisor

[0293]

[0294]

[0295] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0296] Table 2 - Registers Initialized by the Operating System

[0297] 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Memory Segment Table Pointer 5 Authority Mask 6 Work Descriptor

[0298] In one embodiment, each WD 3384 is specific to a particular graphics acceleration module 3346 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to do work or work, or it can be a pointer to a memory location where the application has established a command queue for the work to be done.

[0299] Figure 34A-34B An exemplary graphics processor in accordance with at least one embodiment herein is shown. In at least one embodiment, any exemplary graphics processor may be fabricated using one or more IP cores. In addition to the illustration, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is for use within a SoC.

[0300] Figure 34A An exemplary graphics processor 3410 of a SoC integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. Figure 34B An additional exemplary graphics processor 3440 of a SoC integrated circuit in accordance with at least one embodiment is shown, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 34A the graphics processor 3410 is a low-power graphics processor core. In at least one embodiment, Figure 34B the graphics processor 3440 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 may be a variant of the graphics processor 510 of FIG. 5.

[0301] In at least one embodiment, the graphics processor 3410 includes a vertex processor 3405 and one or more fragment processors 3415A - 3415N (e.g., 3415A, 3415B, 3415C, 3415D to 3415N - 1, and 3415N). In at least one embodiment, the graphics processor 3410 may execute different shader programs via separate logic such that the vertex processor 3405 is optimized to execute operations for vertex shader programs, while the one or more fragment processors 3415A - 3415N perform fragment (e.g., pixel) shading operations for fragment or pixel or shader programs. In at least one embodiment, the vertex processor 3405 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 3415A - 3415N use the primitives and vertex data generated by the vertex processor 3405 to generate a frame buffer for display on a display device. In at least one embodiment, the fragment processors 3415A - 3415N are optimized to execute fragment shader programs as provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0302] In at least one embodiment, the graphics processor 3410 additionally includes one or more MMUs 3420A - 3420B, caches 3425A - 3425B, and circuit interconnections 3430A - 3430B. In at least one embodiment, the one or more MMUs 3420A - 3420B provide virtual - to - physical address mapping for the graphics processor 3410, including for the vertex processor 3405 and / or the fragment processors 3415A - 3415N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3425A - 3425B. In at least one embodiment, the one or more MMUs 3420A - 3420B may be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 505, image processors 515, and / or video processors 520 of FIG. 5, such that each processor 505 - 520 may participate in a shared or unified virtual memory system. In at least one embodiment, the one or more circuit interconnections 3430A - 3430B enable the graphics processor 3410 to connect to other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0303] In at least one embodiment, the graphics processor 3440 includes Figure 34AOne or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B of the graphics processor 3410. In at least one embodiment, the graphics processor 3440 includes one or more shader cores 3455A-3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, to 3455N-1 and 3455N), which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 3440 includes an inter-core task manager 3445, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3455A-3455N and a tiling unit 3458 to accelerate tiling operations for tile-based rendering, where the rendering operation of the scene is subdivided in image space, e.g., to take advantage of local spatial coherence within the scene or optimize the use of internal caches.

[0304] Figure 35A illustrates a graphics core 3500 according to at least one embodiment. In at least one embodiment, the graphics core 3500 can be included within Figure 24 the graphics processor 2410. In at least one embodiment, the graphics core 3500 can be Figure 34B the unified shader cores 3455A-3455N in. In at least one embodiment, the graphics core 3500 includes a shared instruction cache 3502, texture units 3518, and cache / shared memory 3520, which are shared by the execution resources within the graphics core 3500. In at least one embodiment, the graphics core 3500 can include multiple slices 3501A-3501N or partitions per core, and the graphics processor can include multiple instances of the graphics core 3500. The slices 3501A-3501N can include support logic, which includes local instruction caches 3504A-3504N, thread schedulers 3506A-3506N, thread dispatchers 3508A-3508N, and a set of registers 3510A-3510N. In at least one embodiment, the slices 3501A-3501N can include a set of additional functional units (AFUs) 3512A-3512N, floating-point units (FPUs) 3514A-3514N, integer arithmetic logic units (ALUs) 3516A-3516N, address calculation units (ACUs) 3513A-3513N, double-precision floating-point units (DPFPUs) 3515A-3515N, and matrix processing units (MPUs) 3517A-3517N.

[0305] In one embodiment, the FPU 3514A - 3514N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while the DPFPU 3515A - 3515N can perform double - precision (64 - bit) floating - point operations. In at least one embodiment, the ALU 3516A - 3516N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, the MPU 3517A - 3517N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, the MPU 3517A - 3517N can perform various matrix operations to accelerate CUDA programs, including enabling accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, the AFU 3512A - 3512N can perform additional logical operations not supported by the floating - point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0306] Figure 35B A general - purpose graphics processing unit (GPGPU) 3530 is shown in at least one embodiment. In at least one embodiment, the GPGPU 3530 is highly parallel and suitable for deployment on a multi - chip module. In at least one embodiment, the GPGPU 3530 can be configured such that highly parallel computing operations can be performed by a GPU array. In at least one embodiment, the GPGPU 3530 can be directly linked to other instances of the GPGPU 3530 to create a multi - GPU cluster to improve the execution time for CUDA programs. In at least one embodiment, the GPGPU 3530 includes a host interface 3532 to enable connection to a host processor. In at least one embodiment, the host interface 3532 is a PCIe interface. In at least one embodiment, the host interface 3532 can be a vendor - specific communication interface or communication fabric. In at least one embodiment, the GPGPU 3530 receives commands from the host processor and uses a global scheduler 3534 to dispatch execution threads associated with those commands to a set of compute clusters 3536A - 3536H. In at least one embodiment, the compute clusters 3536A - 3536H share a cache memory 3538. In at least one embodiment, the cache memory 3538 can be used as a high - level cache for the cache memories within the compute clusters 3536A - 3536H.

[0307] In at least one embodiment, the GPGPU 3530 includes memories 3544A - 3544B coupled to the compute clusters 3536A - 3536H via a set of memory controllers 3542A - 3542B. In at least one embodiment, the memories 3544A - 3544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0308] In at least one embodiment, each of the compute clusters 3536A - 3536H includes a set of graphics cores, such as Figure 35A the graphics core 3500, which may include various types of integer and floating - point logic units and may perform computational operations at various precisions, including computations suitable for CUDA programs. In at least one embodiment, at least one subset of the floating - point units in each of the compute clusters 3536A - 3536H may be configured to perform 16 - bit or 32 - bit floating - point operations, while a different subset of floating - point units may be configured to perform 64 - bit floating - point operations.

[0309] In at least one embodiment, multiple instances of the GPGPU 3530 may be configured to operate as compute clusters. In at least one embodiment, the compute clusters 3536A - 3536H may implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of the GPGPU 3530 communicate via the host interface 3532. In at least one embodiment, the GPGPU 3530 includes an I / O hub 3539 that couples the GPGPU 3530 to a GPU link 3540, enabling direct connection to other instances of the GPGPU 3530. In at least one embodiment, the GPU link 3540 is coupled to a dedicated GPU - to - GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 3530. In at least one embodiment, the GPU link 3540 is coupled to a high - speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 3530 are located in separate data - processing systems and communicate via network devices accessible via the host interface 3532. In at least one embodiment, the GPU link 3540 may be configured to be able to connect to a host processor, in addition to or in place of the host interface 3532. In at least one embodiment, the GPGPU 3530 may be configured to execute CUDA programs.

[0310] Figure 36AShows a parallel processor 3600 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 3600 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs).

[0311] In at least one embodiment, the parallel processor 3600 includes a parallel processing unit 3602. In at least one embodiment, the parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of the parallel processing unit 3602. In at least one embodiment, the I / O unit 3604 may be directly connected to other devices. In at least one embodiment, the I / O unit 3604 is connected to other devices by using a hub or switch interface (e.g., a memory hub 605). In at least one embodiment, the connection between the memory hub 605 and the I / O unit 3604 forms a communication link. In at least one embodiment, the I / O unit 3604 is connected to a host interface 3606 and a memory crossbar 3616, where the host interface 3606 receives commands for performing processing operations and the memory crossbar 3616 receives commands for performing memory operations.

[0312] In at least one embodiment, when the host interface 3606 receives a command buffer via the I / O unit 3604, the host interface 3606 may direct the work operations to execute those commands to the front end 3608. In at least one embodiment, the front end 3608 is coupled to a scheduler 3610 configured to allocate commands or other work items to a processing array 3612. In at least one embodiment, the scheduler 3610 ensures that the processing array 3612 is properly configured and in an active state before tasks are assigned to the processing array 3612 in the processing array 3612. In at least one embodiment, the scheduler 3610 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 3610 can be configured to perform complex scheduling and work allocation operations at both coarse-grained and fine-grained levels, enabling fast preemption and context switching of threads executing on the processing array 3612. In at least one embodiment, the host software may attest to the workload to be scheduled on the processing array 3612 via one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically allocated on the processing array 3612 by the scheduler 3610 logic within the microcontroller including the scheduler 3610.

[0313] In at least one embodiment, processing array 3612 may include up to "N" processing clusters (e.g., cluster 3614A, cluster 3614B through cluster 3614N). In at least one embodiment, each of the clusters 3614A - 3614N of processing array 3612 may execute a large number of concurrent threads. In at least one embodiment, scheduler 3610 may use various scheduling and / or work assignment algorithms to assign work to the clusters 3614A - 3614N of processing array 3612, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 3610, or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by processing array 3612. In at least one embodiment, different ones of the clusters 3614A - 3614N of processing array 3612 may be assigned to process different types of programs or to perform different types of computations.

[0314] In at least one embodiment, processing array 3612 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3612 is configured to perform general-purpose parallel computing operations. In at least one embodiment, processing array 3612 may include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physics operations, and performing data transformations.

[0315] In at least one embodiment, processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3612 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, processing array 3612 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 3602 may transfer data from system memory via I / O unit 3604 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 3622) during processing and then written back to system memory.

[0316] In at least one embodiment, when the parallel processing unit 3602 is used to perform graphics processing, the scheduler 3610 can be configured to divide the processing workload into tasks of approximately equal size to better distribute the graphics processing operations to the multiple clusters 3614A - 3614N of the processing array 3612. In at least one embodiment, portions of the processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 3614A - 3614N can be stored in a buffer to allow the transfer of intermediate data between the clusters 3614A - 3614N for further processing.

[0317] In at least one embodiment, the processing array 3612 can receive a processing task to be executed via the scheduler 3610, which receives commands defining the processing task from the front end 3608. In at least one embodiment, the processing task can include an index of the data to be processed, such as may include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 3610 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 3608. In at least one embodiment, the front end 3608 can be configured to ensure that the processing array 3612 is configured in a valid state before starting the workload specified by an incoming command buffer (e.g., batch - buffer, push - buffer, etc.).

[0318] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed via memory crossbar 3616, which can receive memory requests from processing array 3612 as well as I / O unit 3604. In at least one embodiment, memory crossbar 3616 can access parallel processor memory 3622 via memory interface 3618. In at least one embodiment, memory interface 3618 can include a plurality of partitioning units (e.g., partitioning unit 3620A, partitioning unit 3620B through partitioning unit 3620N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 3622. In at least one embodiment, the plurality of partitioning units 3620A-3620N are configured to be equal to the number of memory units such that first partitioning unit 3620A has a corresponding first memory unit 3624A, second partitioning unit 3620B has a corresponding memory unit 3624B, and Nth partitioning unit 3620N has a corresponding Nth memory unit 3624N. In at least one embodiment, the number of partitioning units 3620A-3620N may not be equal to the number of memory devices.

[0319] In at least one embodiment, memory units 3624A-3624N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A-3624N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 3624A-3624N, allowing partitioning units 3620A-3620N to write portions of each rendering target in parallel to effectively utilize the available bandwidth of parallel processor memory 3622. In at least one embodiment, a local instance of parallel processor memory 3622 can be excluded to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

[0320] In at least one embodiment, any one of clusters 3614A - 3614N of processing array 3612 can process data to be written into any of memory cells 3624A - 3624N within parallel processor memory 3622. In at least one embodiment, memory crossbar 3616 can be configured to transfer the output of each of clusters 3614A - 3614N to any of partition units 3620A - 3620N or to another cluster 3614A - 3614N, where the cluster 3614A - 3614N can perform additional processing operations on the output. In at least one embodiment, each of clusters 3614A - 3614N can communicate with memory interface 3618 via memory crossbar 3616 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 3616 has connections to memory interface 3618 to communicate with I / O unit 3604 and to a local instance of parallel processor memory 3622, enabling processing units within different processing clusters 3614A - 3614N to communicate with system memory or other memory that is not local to parallel processing unit 3602. In at least one embodiment, memory crossbar 3616 can use virtual channels to separate the traffic flow between clusters 3614A - 3614N and partition units 3620A - 3620N.

[0321] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single insertion card, or multiple insertion cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to operate with each other even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. In at least one embodiment, some instances of parallel processing unit 3602 can include floating - point units with higher precision relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 3602 or parallel processor 3600 can be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, gaming consoles, and / or embedded systems.

[0322] Figure 36B A processing cluster 3694 is shown in accordance with at least one embodiment. In at least one embodiment, processing cluster 3694 is included within a parallel processing unit. In at least one embodiment, processing cluster 3694 is Figure 36AAn instance of one of the processing clusters 3614A - 3614N. In at least one embodiment, the processing cluster 3694 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 3694.

[0323] In at least one embodiment, the operation of the processing cluster 3694 can be controlled by assigning processing tasks to the pipeline manager 3632 of the SIMT parallel processor. In at least one embodiment, the pipeline manager 3632 receives instructions from Figure 36A the scheduler 3610, and manages the execution of these instructions through the graphics multiprocessor 3634 and / or the texture unit 3636. In at least one embodiment, the graphics multiprocessor 3634 is an exemplary instance of the SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures can be included within the processing cluster 3694. In at least one embodiment, one or more instances of the graphics multiprocessor 3634 can be included within the processing cluster 3694. In at least one embodiment, the graphics multiprocessor 3634 can process data, and the data crossbar 3640 can be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 3632 can facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 3640.

[0324] In at least one embodiment, each graphics multiprocessor 3634 within the processing cluster 3694 can include the same set of functional execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the functional execution logic can be configured in a pipeline manner, where new instructions can be issued before the previous instructions are completed. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, boolean operations, shifts, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units can exist.

[0325] In at least one embodiment, the instructions transmitted to processing cluster 3694 constitute threads. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 3634. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 3634. In at least one embodiment, when the number of threads included in a thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 3634. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 3634, processing can be executed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 3634.

[0326] In at least one embodiment, graphics multiprocessor 3634 includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 3634 can forgo the internal cache and use the cache memory (e.g., L1 cache 3648) within processing cluster 3694. In at least one embodiment, each graphics multiprocessor 3634 can also access the L2 cache within a partition unit (e.g., Figure 36A partition units 3620A - 3620N) of the partition unit, which are shared among all processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3634 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 3602 can be used as global memory. In at least one embodiment, processing cluster 3694 includes multiple instances of graphics multiprocessor 3634, which can share common instructions and data that can be stored in L1 cache 3648.

[0327] In at least one embodiment, each processing cluster 3694 can include an MMU 3645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 3645 can reside in Figure 36Awithin the memory interface 3618. In at least one embodiment, the MMU 3645 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more information about tiles is discussed) and optionally to cache line indices. In at least one embodiment, the MMU 3645 may include a translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 3634 or the L1 cache 3648 or the processing cluster 3694. In at least one embodiment, the physical address is processed to allocate surface data access locality for efficient request interleaving among partition units. In at least one embodiment, the cache line index may be used to determine whether a request to a cache line is a hit or a miss.

[0328] In at least one embodiment, the processing cluster 3694 may be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 to perform texture mapping operations, e.g., which may involve determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from the L1 cache within the graphics multiprocessor 3634 as needed and texture data is fetched from the L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 3634 outputs the processed tasks to the data crossbar 3640 to provide the processed tasks to another processing cluster 3694 for further processing or to store the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 3616. In at least one embodiment, the raster operations unit (preROP) 3642 is configured to receive data from the graphics multiprocessor 3634 and direct the data to the ROP unit, which may be located together with the partition units (e.g., Figure 36A partition units 3620A - 3620N) described herein. In at least one embodiment, the PreROP 3642 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0329] Figure 36C shows a graphics multiprocessor 3696 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 3696 is Figure 36BThe graphics multiprocessor 3634. In at least one embodiment, the graphics multiprocessor 3696 is coupled to the pipeline manager 3632 of the processing cluster 3694. In at least one embodiment, the graphics multiprocessor 3696 has an execution pipeline that includes, but is not limited to, an instruction cache 3652, an instruction unit 3654, an address mapping unit 3656, a register file 3658, one or more GPGPU cores 3662, and one or more LSUs 3666. The GPGPU cores 3662 and LSUs 3666 are coupled to a cache memory 3672 and a shared memory 3670 via a memory and cache interconnect 3668.

[0330] In at least one embodiment, the instruction cache 3652 receives a stream of instructions to be executed from the pipeline manager 3632. In at least one embodiment, the instructions are cached in the instruction cache 3652 and dispatched for execution by the instruction unit 3654. In one embodiment, the instruction unit 3654 may dispatch instructions as a thread group (e.g., a warp), and assign each thread of the thread group to a different execution unit within the GPGPU core 3662. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 3656 can be used to convert an address in the unified address space into a different memory address that can be accessed by the LSU 3666.

[0331] In at least one embodiment, the register file 3658 provides a set of registers for the functional units of the graphics multiprocessor 3696. In at least one embodiment, the register file 3658 provides temporary storage for the operands of the data paths of the functional units (e.g., GPGPU cores 3662, LSUs 3666) connected to the graphics multiprocessor 3696. In at least one embodiment, the register file 3658 is partitioned among each functional unit such that a dedicated portion of the register file 3658 is assigned to each functional unit. In at least one embodiment, the register file 3658 is partitioned among different thread groups being executed by the graphics multiprocessor 3696.

[0332] In at least one embodiment, the GPGPU cores 3662 may each include an FPU and / or an ALU for executing instructions of the graphics multiprocessors 3696. The GPGPU cores 3662 may be architecturally similar or may have different architectures. In at least one embodiment, a first portion of the GPGPU cores 3662 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-3608 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 3696 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores 3662 may also include fixed or special-function logic.

[0333] In at least one embodiment, the GPGPU cores 3662 include SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU cores 3662 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU cores may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed by a single SIMD instruction. In at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel by a single SIMD8 logic unit.

[0334] In at least one embodiment, the memory and cache interconnect 3668 is an interconnect network that connects each functional unit of the graphics multiprocessor 3696 to the register file 3658 and the shared memory 3670. In at least one embodiment, the memory and cache interconnect 3668 is a crossbar interconnect that allows the LSU 3666 to perform load and store operations between the shared memory 3670 and the register file 3658. In at least one embodiment, the register file 3658 can operate at the same frequency as the GPGPU core 3662, resulting in very low latency for data transfer between the GPGPU core 3662 and the register file 3658. In at least one embodiment, the shared memory 3670 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 3696. In at least one embodiment, in at least one embodiment, the cache memory 3672 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 3636. In at least one embodiment, the shared memory 3670 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 3672, threads executing on the GPGPU core 3662 can also programmatically store data in the shared memory.

[0335] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0336] General computing

[0337] The following figures illustrate, but are not limited to, exemplary software configurations used to implement at least one embodiment in general computing.

[0338] Figure 37Shows the software stack of a programming platform according to at least one embodiment. In at least one embodiment, the programming platform is a platform for accelerating computing tasks using the hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler directives, and / or extensions to the programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL developed by the Khronos group TM ), SYCL, or Intel One API.

[0339] In at least one embodiment, the software stack 3700 of the programming platform provides an execution environment for the application 3701. In at least one embodiment, the application 3701 can include any computer software capable of being launched on the software stack 3700. In at least one embodiment, the application 3701 can include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0340] In at least one embodiment, the application 3701 and the software stack 3700 run on the hardware 3707. In at least one embodiment, the hardware 3707 can include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support the programming platform. In at least one embodiment, for example, when using CUDA, the software stack 3700 can be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, when using OpenCL, the software stack 3700 can be used with devices from different vendors. In at least one embodiment, the hardware 3707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 3707, which can include, but is not limited to, a CPU (but can also include computing devices) and its memory, the devices within the hardware 3707 can include, but are not limited to, GPUs, FPGAs, AI engines, or other computing devices (but can also include CPUs) and their memory.

[0341] In at least one embodiment, the software stack 3700 of the programming platform includes, but is not limited to, a plurality of libraries 3703, a runtime 3705, and a device kernel driver 3706. In at least one embodiment, each of the libraries 3703 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 3703 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 3703 include functions that are optimized for execution on one or more types of devices. In at least one embodiment, the libraries 3703 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the device. In at least one embodiment, the libraries 3803 are associated with corresponding APIs 3802, which may include one or more APIs that expose the functions implemented in the libraries 3803.

[0342] In at least one embodiment, the application 3701 is written as source code, which is compiled into executable code, as discussed in more detail below in connection with Figure 42 In at least one embodiment, the executable code of the application 3701 can run at least in part on the execution environment provided by the software stack 3700. In at least one embodiment, during the execution of the application 3701, code that needs to run on the device (as compared to the host) may be obtained. In such a case, in at least one embodiment, the runtime 3705 may be called to load and start the necessary code on the device. In at least one embodiment, the runtime 3705 may include any technically feasible runtime system capable of supporting the execution of the application 3701.

[0343] In at least one embodiment, the runtime 3705 is implemented as one or more runtime libraries associated with a corresponding API (which is shown as API 3704). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, etc. In at least one embodiment, the memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and transferring data between host memory and device memory. In at least one embodiment, the execution control functions may include, but are not limited to, functions for starting a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values in a buffer maintained by the runtime library for a given function to be executed on the device.

[0344] In at least one embodiment, the runtime library and the corresponding API 3704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a set of low-level functions for fine-grained control of the device, while another (or any number of) APIs can expose such a set of higher-level functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level API. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0345] In at least one embodiment, the device kernel driver 3706 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 3706 can provide APIs such as API 3704 and / or low-level functions on which other software depends. In at least one embodiment, the device kernel driver 3706 can be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3706 can compile parallel thread execution (“PTX”) IR code that is not hardware-specific into binary code for a specific target device (caching the compiled binary code), which is sometimes also referred to as “final” code. In at least one embodiment, doing so can allow the final code to run on the target device, which may not have existed when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline, without the need for the device kernel driver 3706 to compile the IR code at runtime.

[0346] Figure 38 Shown is a CUDA implementation of the Figure 37 software stack 3700 according to at least one embodiment. In at least one embodiment, the CUDA software stack 3800 on which an application 3801 can be launched includes a CUDA library 3803, a CUDA runtime 3805, a CUDA driver 3807, and a device kernel driver 3808. In at least one embodiment, the CUDA software stack 3800 executes on hardware 3809, which can include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0347] In at least one embodiment, the application 3801, the CUDA runtime 3805, and the device kernel driver 3808 can perform functions similar to those of the application 3701, the runtime 3705, and the device kernel driver 3706, respectively, as described above in connection with Figure 37A description thereof is provided. In at least one embodiment, the CUDA driver 3807 includes a library (libcuda.so) that implements the CUDA driver API 3806. In at least one embodiment, similar to the CUDA runtime API 3804 implemented by the CUDA runtime library (cudart), the CUDA driver API 3806 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, etc. In at least one embodiment, the CUDA driver API 3806 differs from the CUDA runtime API 3804 in that the CUDA runtime API 3804 simplifies device code management by providing implicit initialization, context (similar to a process) management, and module (similar to a dynamically loaded library) management. In contrast to the high-level CUDA runtime API 3804, in at least one embodiment, the CUDA driver API 3806 is a low-level API that provides more fine-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3806 may expose functions for context management that are not exposed by the CUDA runtime API 3804. In at least one embodiment, the CUDA driver API 3806 is also language-independent and, in addition to supporting the CUDA runtime API 3804, also supports, for example, OpenCL. Furthermore, in at least one embodiment, the development libraries including the CUDA runtime 3805 can be considered separate from the driver components, including the user-mode CUDA driver 3807 and the kernel-mode device driver 3808 (sometimes also referred to as the "display" driver).

[0348] In at least one embodiment, the CUDA library 3803 may include, but is not limited to, math libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (such as application 3801) can utilize. In at least one embodiment, the CUDA library 3803 may include math libraries, such as the cuBLAS library, which is an implementation of the basic linear algebra subprograms ("BLAS") for performing linear algebra operations; the cuFFT library for computing the fast Fourier transform ("FFT"), and the cuRAND library for generating random numbers, etc. In at least one embodiment, the CUDA library 3803 may include deep learning libraries, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0349] Figure 39 illustrates according to at least one embodiment of Figure 37ROCm implementation of the software stack 3700. In at least one embodiment, the ROCm software stack 3900 on which the application 3901 can be launched includes a language runtime 3903, a system runtime 3905, a thunk 3907, a ROCm kernel driver 3908, and a device kernel driver 3909. In at least one embodiment, the ROCm software stack 3900 executes on the hardware 3909, which may include a ROCm-enabled GPU developed by AMD Corporation of Santa Clara, California.

[0350] In at least one embodiment, the application 3901 can perform functions similar to those of the application 3701 discussed above in connection with Figure 37 In addition, in at least one embodiment, the language runtime 3903 and the system runtime 3905 can perform functions similar to those of the runtime 3705 discussed above in connection with Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 differ in that the system runtime 3905 is a language-independent runtime that implements the ROCr system runtime API 3904 and utilizes the heterogeneous system architecture (“HAS”) runtime API. In at least one embodiment, the HAS runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control of dispatching kernels through the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared with the system runtime 3905, the language runtime 3903 is an implementation of a language-specific runtime API 3902 layered on top of the ROCr system runtime API 3904. In at least one embodiment, the language runtime API may include, but is not limited to, the Portable Heterogeneous Computing Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. In particular, the HIP language is an extension of the C++ programming language and has a functionally similar version of the CUDA mechanism. And in at least one embodiment, the HIP language runtime API includes functions similar to those of the CUDA runtime API 3804 discussed above in connection with Figure 38 such as functions for memory management, execution control, device management, error handling, and synchronization.

[0351] In at least one embodiment, thunk (ROCt) 3907 is an interface that can be used to interact with the underlying ROCm driver 3908. In at least one embodiment, the ROCm driver 3908 is a ROCk driver, which is a combination of the AMDGPU driver and the HAS kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 37 The HAS kernel driver 3706 is a device kernel driver that allows different types of processors to share system resources more efficiently via hardware features.

[0352] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3900 above the language runtime 3903 and provide for integration with the above. Figure 38 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFT, and the like.

[0353] Figure 40 According to at least one embodiment, Figure 37 4001. In at least one embodiment, the OpenCL software stack 4000 on which the application 4001 can be launched includes an OpenCL framework 4005, an OpenCL runtime 4006, and a driver 4007. In at least one embodiment, the OpenCL software stack 4000 is executed on hardware 3809 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0354] In at least one embodiment, the application 4001, the OpenCL runtime 4006, the device kernel driver 4007 and the hardware 4008 can respectively execute the above combined Figure 37 The discussed application 3701, runtime 3705, device kernel driver 3706, and hardware 3707 have similar functionality. In at least one embodiment, the application 4001 also includes an OpenCL kernel 4002 having code to be executed on the device.

[0355] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4003 and runtime API 4005. In at least one embodiment, the runtime API 4005 uses a context to manage the execution of kernels on a device. In at least one embodiment, each identified device can be associated with its respective context, and the runtime API 4005 can use this context to manage the device's command queue, program objects, and kernel objects, shared memory objects, etc. In at least one embodiment, the platform API 4003 exposes functions that allow a device context to be used to select and initialize a device, submit work to the device via a command queue, and enable data transfer to and from the device, etc. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0356] In at least one embodiment, a compiler 4004 is also included in the OpenCL framework 4005. In at least one embodiment, source code can be compiled offline before executing an application or online during the execution of the application. Contrary to CUDA and ROCm, in at least one embodiment, an OpenCL application can be compiled online by the compiler 4004, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., standard portable intermediate representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, an OpenCL application can be compiled offline before executing such an application.

[0357] Figure 41 Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, the programming platform 4104 is configured to support various programming models 4103, middleware, and / or libraries 4102, and frameworks 4101 that an application 4100 can rely on. In at least one embodiment, the application 4100 can be an AI / ML application implemented using, for example, a deep learning framework (in at least one embodiment, MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and / or NVIDIA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computing on the underlying hardware.

[0358] In at least one embodiment, the programming platform 4104 can be one of the CUDA, ROCm, or OpenCL platforms described above in connection with Figure 38 , Figure 39 and Figure 40 respectively. In at least one embodiment, the programming platform 4104 supports multiple programming models 4103, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 4103 can expose the characteristics of the underlying hardware to improve performance. In at least one embodiment, the programming model 4103 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multi-Processing ("OpenMP"), Open Accelerator ("OpenACC"), and / or Vulcan Compute.

[0359] In at least one embodiment, the library and / or middleware 4102 provides an implementation of the abstraction of the programming model 4104. In at least one embodiment, such libraries include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, such middleware also includes software that provides services to application programs, in addition to those that can be obtained from the programming platform 4104. In at least one embodiment, the library and / or middleware 4102 can include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the library and / or middleware 4102 can include the NCCL and the ROCm Collective Communications Library ("RCCL") libraries, which provide communication routines for GPUs, the MIOpen library for deep learning acceleration, and / or the Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0360] In at least one embodiment, the application framework 4101 depends on the library and / or middleware 4102. In at least one embodiment, each application framework 4101 is a software framework for implementing the standard structure of application software. In at least one embodiment, frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning frameworks can be used to implement AI / ML applications.

[0361] Figure 42 Shows compiled code according to at least one embodiment to be used in Figure 37-40Execute on one of the programming platforms. In at least one embodiment, the compiler 4201 receives the source code 4200, which includes both host code and device code. In at least one embodiment, the compiler 4201 is configured to convert the source code 4200 into host-executable code 4202 for execution on the host and device-executable code 4203 for execution on the device. In at least one embodiment, the source code 4200 can be compiled offline before executing the application or online during the execution of the application.

[0362] In at least one embodiment, the source code 4200 can include code in any programming language supported by the compiler 4201, such as C++, C, Fortran, etc. In at least one embodiment, the source code 4200 can be included in a single-source file, which has a mixture of host code and device code and indicates the location of the device code therein. In at least one embodiment, the single-source file can be a.cu file including CUDA code or a.hip.cpp file including HIP code. Alternatively, in at least one embodiment, the source code 4200 can include multiple source code files instead of a single-source file, in which the host code and device code are separated.

[0363] In at least one embodiment, the compiler 4201 is configured to compile the source code 4200 into host-executable code 4202 for execution on the host and device-executable code 4203 for execution on the device. In at least one embodiment, the compiler 4201 performs operations including parsing the source code 4200 into an abstract syntax tree (AST), performing optimizations, and generating executable code. In at least one embodiment where the source code 4200 includes a single-source file, the compiler 4201 can separate the device code from the host code in such a single-source file, compile the device code and the host code into device-executable code 4203 and host-executable code 4202 respectively, and link the device-executable code 4203 and the host-executable code 4202 together in a single file, as discussed in more detail below regarding Figure 26 More detailed discussion.

[0364] In at least one embodiment, the host-executable code 4202 and the device-executable code 4203 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, the host-executable code 4202 can include native object code, while the device-executable code 4203 can include code in PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host-executable code 4202 and the device-executable code 4203 can include target binary code.

[0365] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is amenable to various modifications and alternative configurations, certain of its embodiments have been shown in the drawings and have been described in detail above. However, it is to be understood that the intention is not to limit the disclosure to the one or more specific forms disclosed, but on the contrary, the intention is to cover all modifications, alternative configurations, and equivalents falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0366] Unless otherwise stated or clearly contradicted by the context, the use of the terms "a," "an," "the," and similar referents in the context of describing the disclosed embodiments (especially in the context of the appended claims) should be construed to cover both the singular and the plural, rather than as defining a term. Unless otherwise stated, the terms "comprising," "having," "including," and "containing" should be construed as open-ended terms (i.e., "including but not limited to"). The term "connected" (when not otherwise modified, referring to a physical connection) should be construed to mean included in whole or in part, attached to, or joined together, even if there are some intervening elements. Unless otherwise indicated herein, references to numerical ranges in this document are merely intended to serve as a shorthand method for referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, unless otherwise indicated or clearly contradicted by the context, the use of the term "set" (e.g., "set of items") or "subset" should be construed to mean a non-empty set including one or more members. Further, unless otherwise indicated or clearly contradicted by the context, a "subset" of a corresponding set does not necessarily denote a proper subset of the corresponding set, but rather the subset and the corresponding set may be equal.

[0367] Unless otherwise expressly indicated or clearly contradicted by context, conjunctive phrases such as the phrase “at least one of A, B, and C” or “at least one of A, B and C” are understood in context to generally mean items, clauses, etc., which can be A or B or C, or any non - empty subset of the set A, B, and C. In at least one embodiment of a set having three members, the conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise stated or contradicted by context, the term “plurality” denotes a plural state (e.g., “a plurality of items” means multiple items). In at least one embodiment, the number of items in a plurality of items is at least two, but can be more if expressly indicated or indicated by context. Further, unless otherwise stated or clear from context, the phrase “based on” means “at least partially based on” rather than “based solely on”.

[0368] Unless otherwise indicated herein or clearly contradicted by context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions and are implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that execute jointly on one or more processors by hardware or a combination thereof. In at least one embodiment, the code is stored in the form of a computer program on a computer-readable storage medium, and in at least one embodiment, the computer program includes a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., propagating transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuits (e.g., buffers, caches, and queues). In at least one embodiment, the code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) on which executable instructions are stored, and when the executable instructions are executed by one or more processors of a computer system (i.e., as a result of being executed), the computer system performs the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media in the plurality of non-transitory computer-readable storage media lack all of the code, but the plurality of non-transitory computer-readable storage media together store all of the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors. In at least one embodiment, the non-transitory computer-readable storage medium stores instructions, and a main central processing unit (“CPU”) executes some instructions while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors, and different processors execute different subsets of the instructions.

[0369] Thus, in at least one embodiment, a computer system is configured to implement one or more services that perform, individually or jointly, the operations of the processes described herein, and such a computer system is configured with suitable hardware and / or software enabling the implementation of the operations. Additionally, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system that includes a plurality of devices operating in different ways such that the distributed computer system performs the operations described herein and such that a single device does not perform all of the operations.

[0370] The use of any and all at least one embodiment or exemplary language (e.g., "such as") provided herein is only intended to better illustrate the embodiments of the present disclosure and does not limit the scope of the disclosure, unless otherwise required. No language in the specification should be construed as indicating that any non-claimed element is essential for practicing the disclosure.

[0371] All references cited herein, including publications, patent applications, and patents, are incorporated herein by reference to the extent that each reference is specifically and individually indicated to be incorporated by reference and its entire content is set forth herein.

[0372] In the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms are not intended as synonyms for each other. Instead, in at least one of the embodiments, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

[0373] Unless otherwise expressly stated, it is understood that throughout the specification, terms such as "processing", "computing", "calculating", "determining", etc., refer to actions and / or processes of a computer or computing system or similar electronic computing device that process and / or transform data represented as a physical quantity (e.g., electronic) in the registers and / or memory of the computing system into other data similarly represented as a physical quantity in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0374] In a similar manner, the term "processor" may refer to any device or portion of a memory that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that may be stored in the registers and / or memory. As a non-limiting example in at least one of the embodiments, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, in at least one of the embodiments, a "software" process may include software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Similarly, each process may refer to multiple processes that execute instructions sequentially or in parallel continuously or intermittently. The terms "system" and "method" may be used interchangeably herein as long as the system can embody one or more methods and the method can be considered a system.

[0375] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data may be accomplished in a variety of ways, such as by receiving data as an argument to a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data may be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transferring, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transferring, sending, or presenting analog or digital data may be implemented by transmitting the data as an input or output argument to a function call, an application programming interface, or an interprocess communication mechanism.

[0376] Although the foregoing discussion describes one implementation in at least one embodiment of the described techniques, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. Additionally, although specific assignments of responsibilities are defined above for purposes of discussion, the various functions and responsibilities may be assigned and divided differently depending on circumstances.

[0377] Moreover, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims need not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A method, comprising: Adjusting a respective blade angle of each of a plurality of blades based at least in part on one or more acoustic values such that a fan switches between an axial operation mode and a centrifugal operation mode.

2. The method according to claim 1, further comprising: Determining that one or more temperature values of a chassis are below a threshold; And Causing the fan to switch from the centrifugal operation mode to the axial operation mode.

3. The method according to claim 1, further comprising: Determining that one or more temperature values of a chassis are above a threshold; And Causing the fan to switch from the axial operation mode to the centrifugal operation mode.

4. The method according to claim 1, further comprising: Causing a plurality of blades of the fan to rotate about a pivot axis perpendicular to a rotation axis of the fan.

5. The method according to claim 4, further comprising: Causing a shaft of a motor coupled to the plurality of blades to rotate about the pivot axis.

6. The method according to claim 4, further comprising: Causing a push rod to axially translate along the rotation axis of the fan.

7. The method according to claim 1, further comprising: Determining that the one or more acoustic values are below a threshold; And Causing the fan to switch from the centrifugal operation mode to the axial operation mode.

8. The method according to claim 1, further comprising: Determining that the one or more acoustic values are above a threshold; And Causing the fan to switch from the axial operation mode to the centrifugal operation mode.

9. The method according to claim 1, further comprising: Positioning one or more sensors within a body of a chassis to obtain the one or more temperature values of the chassis, and further based on the one or more temperature values to cause the fan to switch between the axial operation mode and the centrifugal operation mode.

10. The method according to claim 1, wherein, The causing the fan to switch between the axial operation mode and the centrifugal operation mode includes: causing a blade pitch control assembly to drive each of the plurality of blades to rotate about a corresponding pivot axis to adjust the respective blade angle.

11. A system, comprising: A fan including a plurality of blades that are rotatable about an axis of the fan, each of the plurality of blades being arranged at a respective blade angle; A blade pitch control assembly for driving each of the plurality of blades to rotate about a corresponding pivot axis to adjust the respective blade angle; And At least one processor for: Causing the fan to operate in an axial operation mode to direct air parallel to the axis of the fan; Determining that at least one acoustic value exceeds a threshold; And Causing the fan to operate in a centrifugal operation mode to direct air perpendicular to the axis of the fan.

12. The system according to claim 11, wherein the corresponding pivot axis is perpendicular to an axis of a corresponding one of the plurality of blades.

13. The system according to claim 11, wherein in response to the fan operating in the axial operation mode, the respective blade angle of each blade is an acute angle.

14. The system according to claim 11, wherein: In response to the fan operating in the centrifugal operating mode, the respective blade profiles of the plurality of blades are parallel to the axis of the fan.

15. The system according to claim 11, further comprising: one or more sensors located within a chassis including the fan, the one or more sensors being temperature sensors configured to determine the at least one temperature value.

16. A system comprising: a chassis; and a fan including a plurality of blades that are rotatable about an axis of the fan, each of the plurality of blades being arranged at a respective blade angle, the fan being located within the chassis for directing an airflow into the chassis, the respective blade angle of each blade being adjustable at least in part based on one or more acoustic values to change an operating mode of the fan from an axial operating mode to a centrifugal operating mode; a blade pitch control assembly for driving each of the plurality of blades to rotate about a corresponding pivot axis to adjust the respective blade angle.

17. The system according to claim 16, wherein: the blade pitch control assembly has a motor for driving each of the plurality of blades to rotate about a respective pivot axis.

18. The system according to claim 17, further comprising: at least one controller for sending a control signal to the blade pitch control assembly to change the operating mode of the fan.

19. The system according to claim 18, further comprising: one or more sensors that determine a temperature within the chassis, the one or more sensors sending a temperature value to the at least one controller.

20. The system according to claim 17, further comprising: a vent formed in the chassis that directs the airflow out of the chassis when the fan is in the centrifugal operating mode.

Images