The invention provides a method for repairing
retention time violation. The method comprises the following steps: acquiring a network
list and a
layout result of an FPGA (
Field Programmable Gate Array); the network
list comprises a connection relationship between the target sending unit and the target receiving unit, and the
layout result comprises respective
layout coordinates of the target sending unit and the target receiving unit; the target sending unit and the target receiving unit are driven by the same
time signal; based on the respective layout coordinates of the target sending unit and the target receiving unit, evaluating the path time
delay of the connection path by using a static
time sequence analysis tool; and when the path time
delay is smaller than a path time
delay threshold value, adding an unused
lookup table of at least one FPGA into the connection relation, and on the premise of not changing a layout result, determining respective layout coordinates of the at least one unused
lookup table based on the layout result so as to repair
retention time violation of the connection path. Therefore, the
retention time violation of the connection path can be quickly repaired by adding the unused
lookup table of the FPGA in the layout stage.