A gate driving circuit

Abstract

A gate driving circuit, characterized in that: the circuit includes a charge pump unit, a voltage dividing driving unit, a driving selection unit and a power transistor; wherein, the charge pump unit includes a first-stage charge pump and a second-stage charge pump, and the first-stage charge pump is cascaded with the second-stage charge pump; the voltage dividing driving unit is connected to the driving stage of the second-stage charge pump and is used to select to drive the second-stage charge pump based on the drain voltage of the power transistor and a reference voltage; the driving selection unit is respectively connected to the output ends of the first-stage charge pump and the second-stage charge pump and is used to select the output end of the first-stage charge pump or the second-stage charge pump as the gate driving voltage of the power transistor. The circuit of the present invention is simple, low in cost and accurate in effect.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more particularly, to a gate driving circuit. Background Art

[0002] In the prior art, a cascaded charge pump is usually used as a gate driving circuit to feedback a gate voltage with a larger voltage value to a power transistor when the input voltage is small, so as to realize the gate driving of the power transistor.

[0003] However, in this technical solution of the prior art, although the effective driving of the power transistor can be ensured when the input voltage is small, when the input voltage gradually rises to a higher state, the excitation effect of the charge pump will cause the gate voltage of the power transistor to be too high. When the gate voltage received by the power transistor is higher than its own breakdown voltage, the power transistor cannot work normally and is likely to affect the safety of the subsequent circuit.

[0004] On the other hand, the charge pump in the prior art needs to be driven under the combined action of a clock signal and an inverter. During the normal operation of the charge pump, the charge pump driving unit needs to continuously perform signal inversion based on the high and low levels of the clock signal, and control the capacitors C0 and C1 to be alternately in the charge and discharge states, consuming a large amount of power.

[0005] To solve this problem, there is an urgent need for a gate driving circuit. Summary of the Invention

[0006] To solve the deficiencies in the prior art, the object of the present invention is to provide a gate driving circuit, which controls the turning on and off of a secondary charge pump based on the magnitude of the input voltage Vin of a power transistor, and accordingly selects the output of a primary charge pump or a secondary charge pump as the gate voltage of the power transistor.

[0007] The present invention adopts the following technical solutions.

[0008] A gate driving circuit, wherein the circuit includes a charge pump unit, a voltage dividing and driving unit, a driving selection unit, and a power transistor; the charge pump unit includes a primary charge pump and a secondary charge pump, and the primary charge pump and the secondary charge pump are cascaded; the voltage dividing and driving unit is connected to the driving stage of the secondary charge pump and is used to select the driving of the secondary charge pump based on the drain voltage of the power transistor and a reference voltage; the driving selection unit is respectively connected to the output ends of the primary charge pump and the secondary charge pump and is used to select the output end of the primary charge pump or the secondary charge pump as the gate driving voltage of the power transistor.

[0009] Preferably, the voltage-dividing driving unit identifies the drain voltage Vin of the power transistor; when Vin is less than the driving threshold voltage of the secondary charge pump, the secondary charge pump is driven normally; when Vin is greater than the driving threshold voltage of the secondary charge pump, the secondary charge pump is in the static mode.

[0010] Preferably, the voltage-dividing driving unit includes voltage-dividing resistors R0, R1, an error amplifier EA, a NOR gate, and an inverter; among them, the voltage-dividing resistors R0 and R1 are connected in series and are connected between the power supply voltage Vdd and the ground level, and the divided voltage V0 of R0 and R1 is connected to the positive input terminal of the error amplifier EA; the negative input terminal of the error amplifier EA is connected to the reference voltage Vref, and the output terminal is connected to one input terminal of the NOR gate; the other input terminal of the NOR gate is connected to the clock signal CLK, and the output terminal is connected to the inverter; the output terminal of the inverter is connected to the driving stage of the secondary charge pump.

[0011] Preferably, when the value of the divided voltage V0 is such that, the error amplifier EA outputs a low level, and the voltage-dividing driving unit outputs the clock signal CLK; when the value of the divided voltage V0 is such that, the error amplifier EA outputs a high level, and the voltage-dividing driving unit shields the clock signal CLK.

[0012] Preferably, when the driving selection unit receives the output voltages of both the primary charge pump and the secondary charge pump at the same time, it selects the output voltage of the secondary charge pump as the gate voltage of the power transistor; when the driving selection unit only receives the output voltage of the primary charge pump and does not receive the output voltage of the secondary charge pump, it selects the output voltage of the primary charge pump as the gate voltage of the power transistor.

[0013] Preferably, the driving selection unit includes a first driving selection MOS transistor Mp4 and a second driving selection MOS transistor Mp5; among them, the gate of the first driving selection MOS transistor Mp4 and the drain of the second driving selection MOS transistor Mp5 are connected to the output signal of the secondary charge pump; the drain of the first driving selection MOS transistor Mp4 and the gate of the second driving selection MOS transistor Mp5 are connected to the output signal of the primary charge pump; the sources of the first driving selection MOS transistor Mp4 and the second driving selection MOS transistor Mp5 are connected to each other and are connected to the gate of the power transistor.

[0014] Preferably, the charge pump unit includes a current source, a primary charge pump, a first control unit, a secondary charge pump, and a second control unit; among them, one end of the current source is connected to the drain of the power transistor, and the other end is connected to the input terminal of the primary charge pump; the output terminal of the primary charge pump is connected to the driving stage of the secondary charge pump; the first control unit and the second control unit are respectively connected to the control terminals of the primary and secondary charge pumps.

[0015] Preferably, the first - stage charge pump and the second - stage charge pump are exactly the same, and the first control unit and the second control unit are exactly the same.

[0016] Preferably, the first - stage charge pump includes NMOS transistors Mn0 and Mn1, PMOS transistors Mp0 and Mp1, and capacitors C0 and C1. Among them, the sources of Mn0 and Mn1 are connected to each other as the input terminal of the first - stage charge pump, and the sources of Mp0 and Mp1 are connected as the output terminal of the first - stage charge pump. The gate of Mn0, the drain of Mn1, the gate of Mp0, the drain of Mp1, and one end of capacitor C1 are connected. The gate of Mn1, the drain of Mn0, the gate of Mp1, the drain of Mp0, and one end of capacitor C0 are connected.

[0017] Preferably, the first control unit includes inverters Inv0 and Inv1. Among them, the power supply terminals of inverters Inv0 and Inv1 are respectively connected to the drain of the power transistor, using the voltage Vin at the drain of the power transistor. The ground terminals of inverters Inv0 and Inv1 are grounded. The input terminal of inverter Inv0 receives the clock signal CLK, and the output terminal is connected to the other end of capacitor C0 and the input terminal of inverter Inv1. The output terminal of inverter Inv1 is connected to the other end of capacitor C1.

[0018] The beneficial effects of the present invention are as follows. Compared with the prior art, in a gate driving circuit of the present invention, it can control the turning on and off of the second - stage charge pump based on the magnitude of the input voltage Vin of the power transistor, and accordingly select the output of the first - stage charge pump or the second - stage charge pump as the gate voltage of the power transistor. The circuit of the present invention is simple, has low cost, and accurate effects.

[0019] The beneficial effects of the present invention also include:

[0020] 1. In the gate driving circuit of the present invention, it can select whether the first - stage charge pump works or both the first - stage and second - stage charge pumps work based on the magnitude of the input voltage of the power transistor. In this way, when the input voltage Vin of the power transistor is too large, the number of charge - pump stages is automatically reduced, thus ensuring the stability of the gate driving voltage.

[0021] 2. In the present invention, when Vin is relatively large, the voltage - dividing driving unit is directly adopted, the input of the second - stage charge pump is cancelled, and the second - stage charge pump is kept in a static state, thereby greatly reducing the power consumption of the system when Vin is relatively large. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic circuit structure diagram of a gate driving circuit in the prior art of the present invention;

[0023] Figure 2 It is a schematic circuit structure diagram of a gate driving circuit in the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present application will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and cannot be used to limit the protection scope of the present application.

[0025] Figure 1 It is a schematic circuit diagram of a gate driving circuit in the prior art of the present invention. As Figure 1 shown, the gate driving circuit in the prior art includes two cascaded charge pumps. Specifically, the drain voltage of the power transistor MnPWR is Vin. When this drain voltage is used as the input signal of the first-stage charge pump, the first-stage charge pump will output a voltage of 2*Vin. After this voltage is used as the input signal of the second-stage charge pump, the output is 3*Vin. It can be seen that the gate voltage of the power transistor is 3*Vin.

[0026] Based on the above circuit, although the input voltage Vin at the drain of the power transistor may be small, due to the effect of the charge pump, its gate voltage is large. Therefore, the on-resistance of the power transistor is effectively reduced, and the conduction of the power transistor MnPWR and the power supply for the subsequent circuit can be ensured.

[0027] On the other hand, in this process, the inverters Inv0, Inv1, Inv2, and Inv3 in the two-stage charge pump driving unit are constantly switched between high and low levels under the action of the clock signal CLK, and the capacitor is charged and discharged accordingly, which makes the chip power consumption very high.

[0028] To solve the above problems, in the present invention, a gate driving circuit is provided.

[0029] Figure 2 It is a schematic circuit diagram of a gate driving circuit in the present invention. As Figure 2 shown, a gate driving circuit includes a charge pump unit, a voltage dividing and driving unit, a driving selection unit, and a power transistor; wherein, the charge pump unit includes a first-stage charge pump and a second-stage charge pump, and the first-stage charge pump and the second-stage charge pump are cascaded; the voltage dividing and driving unit is connected to the driving stage of the second-stage charge pump and is used to select and drive the second-stage charge pump based on the drain voltage of the power transistor and the reference voltage; the driving selection unit is respectively connected to the output terminals of the first-stage charge pump and the second-stage charge pump and is used to select the output terminal of the first-stage charge pump or the second-stage charge pump as the gate driving voltage of the power transistor.

[0030] It can be understood that in order to prevent the second-stage charge pump from still being in the working state and consuming a large amount of power when the input voltage Vin is too large, the present invention provides a voltage dividing and driving unit to stop the working state of the second-stage charge pump when it detects that Vin is too large.

[0031] In addition, a selection unit is provided at the output ends of the first-stage and second-stage charge pumps to accurately select the end with the higher output voltage as the gate voltage of the power transistor MnPWR.

[0032] Preferably, the voltage-dividing driving unit identifies the drain voltage Vin of the power transistor; when Vin is less than the driving threshold voltage of the second-stage charge pump, the second-stage charge pump is normally driven; when Vin is greater than the driving threshold voltage of the second-stage charge pump, the second-stage charge pump is in the static mode.

[0033] In an embodiment of the present invention, the voltage-dividing driving unit includes an error amplifier EA, which can be used to compare the divided Vin with a preset reference voltage Vref to determine the magnitude of Vin.

[0034] Preferably, the voltage-dividing driving unit includes voltage-dividing resistors R0, R1, an error amplifier EA, a NOR gate, and an inverter; wherein, the voltage-dividing resistors R0 and R1 are connected in series and are connected between the power supply voltage Vdd and the ground level, and the divided voltage V0 of R0 and R1 is connected to the positive-phase input terminal of the error amplifier EA; the negative-phase input terminal of the error amplifier EA is connected to the reference voltage Vref, and the output terminal is connected to one input terminal of the NOR gate; the other input terminal of the NOR gate is connected to the clock signal CLK, and the output terminal is connected to the inverter; the output terminal of the inverter is connected to the driving stage of the second-stage charge pump.

[0035] It can be understood that after the divided voltage V0 enters the positive-phase input terminal of the error amplifier, it will be compared with the reference voltage Vref, and the error amplifier will determine whether its output is 1 or 0 according to their magnitudes. Through the output of the error amplifier, the NOR gate will determine whether to shield the clock signal CLK or invert the clock signal CLK and output it. After passing through an inverter, the signal received by the second-stage charge pump is either the clock signal or the static signal after the clock signal is shielded, that is, the state without input.

[0036] Preferably, when the value of the divided voltage V0 is, the error amplifier EA outputs a low level, and the driving unit outputs the clock signal CLK; when the value of the divided voltage V0 is, the error amplifier EA outputs a high level, and the driving unit shields the clock signal CLK.

[0037] It can be understood that in the present invention, the value of the divided voltage V0 is jointly determined by the two voltage-dividing resistors R0 and R1. Therefore, according to this formula, the driving threshold voltage value of the second-stage charge pump can be confirmed as V ref (R0 + R1) / R0. When Vin is greater than the driving threshold voltage, the clock signal will be shielded at this time. When Vin is less than the driving threshold voltage, the clock signal will be output.

[0038] Preferably, when the drive selection unit receives the output voltages of both the first - stage charge pump and the second - stage charge pump simultaneously, it selects the output voltage of the second - stage charge pump as the gate voltage of the power transistor; when the drive selection unit only receives the output voltage of the first - stage charge pump and does not receive the output voltage of the second - stage charge pump, it selects the output voltage of the first - stage charge pump as the gate voltage of the power transistor.

[0039] It can be understood that the drive selection unit can select different voltages according to the outputs of the first - stage charge pump and the second - stage charge pump.

[0040] Preferably, the drive selection unit includes a first drive - selection MOS transistor Mp4 and a second drive - selection MOS transistor Mp5; wherein, the gate of the first drive - selection MOS transistor Mp4 and the drain of the second drive - selection MOS transistor Mp5 are signal - connected to the output terminal of the second - stage charge pump; the drain of the first drive - selection MOS transistor Mp4 and the gate of the second drive - selection MOS transistor Mp5 are signal - connected to the output terminal of the first - stage charge pump; the sources of the first drive - selection MOS transistor Mp4 and the second drive - selection MOS transistor Mp5 are connected to each other and are connected to the gate of the power transistor.

[0041] It can be understood that in the present invention, the first drive - selection MOS transistor and the second drive - selection MOS transistor are cross - connected to realize the selection of the signal with the higher voltage among points A and B. Figure 2 The selection of the signal with the higher voltage among points A and B.

[0042] Preferably, the charge - pump unit includes a current source, a first - stage charge pump, a first control unit, a second - stage charge pump, and a second control unit; wherein, one end of the current source is connected to the drain of the power transistor, and the other end is connected to the input terminal of the first - stage charge pump; the output terminal of the first - stage charge pump is connected to the driving stage of the second - stage charge pump; the first control unit and the second control unit are respectively connected to the control terminals of the first - stage and second - stage charge pumps.

[0043] In an embodiment of the present invention, two - stage charge pumps can be selected as the drive for the gate voltage. In other embodiments, a cascade of more - stage charge pumps can also be used as the drive circuit for a higher - required gate voltage. Moreover, in the process of voltage selection, the method in the present invention can also be used to select several charge pumps.

[0044] The first and second control units described above are respectively signal - input circuits connected to the control terminals of the first - stage and second - stage charge pumps, that is, the other ends of the capacitors. According to the function of the inverter, the clock signal can be inverted and input into the charge pump in a synchronous - delay manner, thereby controlling the cyclic on - off of the MOS transistors in the charge pump and realizing the switching between two working states of the charge pump and doubling the voltage of the driving stage.

[0045] Preferably, the first - stage charge pump and the second - stage charge pump are exactly the same, and the first control unit and the second control unit are exactly the same.

[0046] It can be understood that in the present invention, two - stage or multi - stage charge pumps can be set to be exactly the same. In this way, it is convenient for calculation and parameter design, and the output of each stage is set to be the sum of the output of the previous stage and Vin.

[0047] Preferably, the first - stage charge pump includes NMOS transistors Mn0 and Mn1, PMOS transistors Mp0 and Mp1, and capacitors C0 and C1; wherein, the sources of Mn0 and Mn1 are connected to each other as the input terminal of the first - stage charge pump, and the sources of Mp0 and Mp1 are connected as the output terminal of the first - stage charge pump; the gate of Mn0, the drain of Mn1, the gate of Mp0, the drain of Mp1, and one end of capacitor C1 are connected; the gate of Mn1, the drain of Mn0, the gate of Mp1, the drain of Mp0, and one end of capacitor C0 are connected.

[0048] It can be understood that in the present invention, the charge pump can be set according to the prior - art solutions. Capacitors are respectively arranged at two driving ends of the charge pump, so as to further boost the voltage of the charge pump through alternating discharging.

[0049] Preferably, the first control unit includes inverters Inv0 and Inv1; wherein, the power supply terminals of inverters Inv0 and Inv1 are respectively connected to the drains of the power transistors, using the voltage Vin at the drains of the power transistors. The ground terminals of inverters Inv0 and Inv1 are grounded; the input terminal of inverter Inv0 receives the clock signal CLK, and the output terminal is connected to the other end of capacitor C0 and the input terminal of inverter Inv1; the output terminal of inverter Inv1 is connected to the other end of capacitor C1.

[0050] It can be understood that the charge pump in the present invention is driven based on an inverter and a clock signal.

[0051] The beneficial effect of the present invention is that, compared with the prior art, a gate driving circuit in the present invention can control the turning on and off of the second - stage charge pump based on the magnitude of the input voltage Vin of the power transistor, and accordingly select the output of the first - stage charge pump or the second - stage charge pump as the gate voltage of the power transistor. The circuit of the present invention is simple, low - cost, and accurate in effect.

[0052] The applicant of the present invention has made a detailed description and illustration of the embodiments of the present invention in combination with the accompanying drawings of the specification. However, those skilled in the art should understand that the above - mentioned embodiments are only the preferred implementation schemes of the present invention. The detailed description is only to help readers better understand the spirit of the present invention, rather than a limitation on the protection scope of the present invention. On the contrary, any improvement or modification made based on the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. A gate driving circuit, characterized in that: The circuit includes a charge pump unit, a voltage dividing driving unit, a driving selection unit and a power transistor; wherein, The charge pump unit includes a first-stage charge pump and a second-stage charge pump, and the first-stage charge pump and the second-stage charge pump are cascaded; The voltage dividing driving unit is connected to the driving stage of the second-stage charge pump, and is used to select to drive the second-stage charge pump based on the drain voltage of the power transistor and a reference voltage; The driving selection unit is respectively connected to the output terminals of the first-stage charge pump and the second-stage charge pump, and is used to select the output terminal of the first-stage charge pump or the second-stage charge pump as the gate driving voltage of the power transistor; When the driving selection unit receives the output voltages of both the first-stage charge pump and the second-stage charge pump at the same time, it selects the output voltage of the second-stage charge pump as the gate voltage of the power transistor; When the driving selection unit only receives the output voltage of the first-stage charge pump and does not receive the output voltage of the second-stage charge pump, it selects the output voltage of the first-stage charge pump as the gate voltage of the power transistor.

2. The gate driving circuit according to claim 1, characterized in that: The voltage dividing driving unit identifies the drain voltage Vin of the power transistor; When Vin is less than the driving threshold voltage of the second-stage charge pump, the second-stage charge pump is normally driven; When Vin is greater than the driving threshold voltage of the second-stage charge pump, the second-stage charge pump is in a static mode.

3. The gate driving circuit according to claim 2, characterized in that: The voltage dividing driving unit includes voltage dividing resistors R0, R1, an error amplifier EA, a NOR gate and an inverter; Wherein, the voltage dividing resistors R0 and R1 are connected in series and are connected between the power supply voltage Vdd and the ground level, and the divided voltage V0 of R0 and R1 is connected to the positive input terminal of the error amplifier EA; The negative input terminal of the error amplifier EA is connected to the reference voltage Vref, and the output terminal is connected to one input terminal of the NOR gate; The other input terminal of the NOR gate is connected to the clock signal CLK, and the output terminal is connected to the inverter; The output terminal of the inverter is connected to the driving stage of the second-stage charge pump.

4. The gate driving circuit according to claim 3, characterized in that: When the value of the divided voltage V0 is such that the error amplifier EA outputs a low level, the divided voltage driving unit outputs a clock signal CLK; When the value of the partial pressure V0 is such that the error amplifier EA outputs a high level, the partial pressure driving unit shields the clock signal CLK.

5. The gate driving circuit according to claim 1, characterized in that: The driving selection unit includes a first driving selection MOS transistor Mp4 and a second driving selection MOS transistor Mp5; wherein, The gate of the first driving selection MOS transistor Mp4 and the drain of the second driving selection MOS transistor Mp5 are connected to the output signal of the second-stage charge pump; The drain of the first driving selection MOS transistor Mp4 and the gate of the second driving selection MOS transistor Mp5 are connected to the output signal of the first-stage charge pump; The sources of the first driving selection MOS transistor Mp4 and the second driving selection MOS transistor Mp5 are connected to each other and are connected to the gate of the power transistor.

6. The gate driving circuit according to claim 1, characterized in that: The charge pump unit includes a current source, a first-stage charge pump, a first control unit, a second-stage charge pump, and a second control unit; wherein, One end of the current source is connected to the drain of the power transistor, and the other end is connected to the input terminal of the first-stage charge pump; The output terminal of the first-stage charge pump is connected to the driving stage of the second-stage charge pump; The first control unit and the second control unit are respectively connected to the control terminals of the first-stage and second-stage charge pumps.

7. The gate driving circuit according to claim 6, wherein: The first-stage charge pump and the second-stage charge pump are exactly the same, and the first control unit and the second control unit are exactly the same.

8. The gate driving circuit according to claim 7, wherein: The first-stage charge pump includes NMOS transistors Mn0 and Mn1, PMOS transistors Mp0 and Mp1, and capacitors C0 and C1; wherein, The sources of Mn0 and Mn1 are connected to each other as the input terminal of the first-stage charge pump, and the sources of Mp0 and Mp1 are connected as the output terminal of the first-stage charge pump; The gate of Mn0, the drain of Mn1, the gate of Mp0, the drain of Mp1, and one end of capacitor C1 are connected; The gate of Mn1, the drain of Mn0, the gate of Mp1, the drain of Mp0, and one end of capacitor C0 are connected.

9. The gate driving circuit according to claim 8, wherein: The first control unit includes inverters Inv0 and Inv1; wherein, The power supply terminals of the inverters Inv0 and Inv1 are respectively connected to the drain of the power transistor, using the voltage Vin at the drain of the power transistor, and the ground terminals of the inverters Inv0 and Inv1 are grounded; The input terminal of the inverter Inv0 receives the clock signal CLK, and the output terminal is connected to the other end of capacitor C0 and the input terminal of the inverter Inv1; The output terminal of the inverter Inv1 is connected to the other end of capacitor C1.

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