A standard cell layout optimization method, apparatus, system, and medium

Abstract

This application provides a method, apparatus, system, and medium for optimizing standard cell layouts. Based on the actual process flow and structural parameters of an initial standard cell layout, electrical simulations are performed. The simulation performance indicators of the initial standard cell layout are calculated based on the simulation results. When the simulation performance indicators match the preset performance indicators, a multinomial model of the layout dependency effect is established based on the fitting factor of the layout dependency effect model of the initial standard cell layout. The structural parameters of the initial standard cell layout are then corrected to obtain the corrected device structural parameters. A compact model is established, and a greedy algorithm is used to optimize the initial standard cell layout. By utilizing semiconductor process and device simulation tools to model based on the layout dependency effect, the cost of test fabrication is reduced. By generating a compact model and combining it with a greedy algorithm, optimized standard cell layouts are quickly generated, improving the efficiency of standard cell layout optimization, guiding the improvement of standard cell layout performance in the early stages of process development, and shortening the R&D cycle.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and in particular to a method, apparatus, system and medium for optimizing standard cell layout. Background Technology

[0002] Standard cell libraries are the core of digital circuit design. After logic synthesis, digital circuits integrate standard cell layouts using place-and-route algorithms, reducing the complexity of circuit layout design and manufacturing risks. To improve chip circuit performance, iterative optimization of standard cell libraries is a crucial aspect of PDK (Process Design Kit) development.

[0003] Among various standard cell optimization techniques, using the layout dependency effect for standard cell layout optimization can achieve optimal performance and minimal process fluctuations for standard cells.

[0004] As the size of integrated circuit devices continues to shrink, the fluctuations in device characteristics caused by changes in layout become more severe, resulting in deviations between actual device performance and simulation results. Improving layout-dependent effect modeling has become an indispensable part of integrated circuit design.

[0005] At 22nm and above, semiconductor device structures generally employ FinFETs (Fin Field-Effect Transistors). The three-dimensional effects of FinFET devices significantly increase the complexity of layout-dependent effect modeling. New processes also introduce new layout-dependent effects, resulting in LDE (Layout Dependent Effect) impacting device performance by approximately 30%. Layout-dependent modeling is an effective method for predicting the impact of layout on device performance. Traditional layout-dependent effect modeling processes require multiple iterations through LDE testing of layout design, mask fabrication testing, and more. At advanced process nodes, the cost of fabrication testing becomes even higher, and the development cycle becomes longer.

[0006] Therefore, how to improve the performance of standard cell layout as much as possible, reduce costs, and shorten the R&D cycle in the early stages of process development is a technical problem that needs to be solved in this field. Summary of the Invention

[0007] In view of this, a summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] The purpose of this application is to provide a standard cell layout optimization method, apparatus, system, and medium that can reduce test fabrication costs, improve standard cell layout optimization efficiency, guide early-stage process development to improve standard cell layout performance, and shorten the R&D cycle.

[0009] To achieve the above objectives, this application provides the following technical solution:

[0010] In a first aspect, embodiments of this application provide a standard cell layout optimization method, including:

[0011] Based on the actual process flow and structural parameters of the current device's initial standard cell layout, electrical simulation of the device is performed to obtain simulation results;

[0012] Calculate the simulation performance indicators of the initial standard cell layout of the current device based on the simulation results;

[0013] When the simulation performance index is consistent with the preset performance index, a multinomial model of the layout dependence effect is established based on the fitting factor of the layout dependence effect model of the initial standard cell layout of the current device.

[0014] The structural parameters of the initial standard cell layout of the current device are corrected according to the layout-dependent effect multinomial model to obtain the corrected device structural parameters;

[0015] A compact model of the current device is established based on the corrected device structure parameters;

[0016] Based on the compact model of the current device, a greedy algorithm is used to optimize the initial standard cell layout of the current device to obtain an optimized standard cell layout.

[0017] In one possible implementation, the step of optimizing the initial standard cell layout of the current device using a greedy algorithm to obtain an optimized standard cell layout includes:

[0018] Based on the layout dependency effect of the initial standard cell layout, the layout dependency factor of the layout dependency effect of the current device's initial standard cell layout is optimized using the greedy algorithm to obtain the optimized standard cell layout.

[0019] One possible implementation also includes:

[0020] Establish a test circuit to obtain the performance, power consumption, and area of ​​the optimized standard cell layout;

[0021] When the performance of the optimized standard cell layout is greater than or equal to a first preset value, the power consumption is less than or equal to a second preset value, and the area is less than or equal to a third preset value, the optimized standard cell layout is used as the final standard cell layout.

[0022] In one possible implementation, the current device includes a finned field-effect transistor device; the layout-dependent effect model fitting factors include fin width, fin spacing, and number of fins.

[0023] Secondly, embodiments of this application provide a standard cell layout optimization apparatus, comprising:

[0024] The simulation unit is used to perform electrical simulation of the device based on the actual process flow and structural parameters of the current device's initial standard cell layout, and to obtain simulation results;

[0025] A computing unit is used to calculate the simulation performance indicators of the initial standard cell layout of the current device based on the simulation results;

[0026] A unit is established to establish a layout dependency effect multinomial model based on the layout dependency effect model fitting factor of the current device's initial standard cell layout when the simulation performance index is consistent with the preset performance index.

[0027] The correction unit is used to correct the structural parameters of the initial standard cell layout of the current device according to the layout dependency effect multinomial model, so as to obtain the corrected device structural parameters.

[0028] A model unit is used to establish a compact model of the current device based on the corrected device structure parameters;

[0029] The optimization unit is used to optimize the initial standard cell layout of the current device using a greedy algorithm based on the compact model of the current device, so as to obtain an optimized standard cell layout.

[0030] In one possible implementation, the optimization unit is specifically used for:

[0031] Based on the layout dependency effect of the initial standard cell layout, the layout dependency factor of the layout dependency effect of the current device's initial standard cell layout is optimized using the greedy algorithm to obtain the optimized standard cell layout.

[0032] One possible implementation also includes:

[0033] Test unit, used to establish test circuitry to obtain the performance, power consumption, and area of ​​the optimized standard cell layout;

[0034] The comparison unit is used to select the optimized standard cell layout as the final standard cell layout when the performance of the optimized standard cell layout is greater than or equal to a first preset value, the power consumption is less than or equal to a second preset value, and the area is less than or equal to a third preset value.

[0035] In one possible implementation, the current device includes a finned field-effect transistor device; the layout-dependent effect model fitting factors include fin width, fin spacing, and number of fins.

[0036] Thirdly, embodiments of this application provide a standard cell layout optimization system, including:

[0037] Memory, used to store computer programs;

[0038] A processor, used to implement the steps of the standard cell layout optimization method as described above when executing the computer program.

[0039] Fourthly, embodiments of this application provide a computer-readable medium storing a computer program, which, when processed and executed, implements the steps of the standard cell layout optimization method described above.

[0040] Compared with the prior art, the embodiments of this application have the following beneficial effects:

[0041] This application provides a standard cell layout optimization method, apparatus, system, and medium. The method includes: performing device electrical simulation based on the actual process flow and structural parameters of the current device's initial standard cell layout to obtain simulation results; calculating the simulation performance index of the current device's initial standard cell layout based on the simulation results; when the simulation performance index is consistent with the preset performance index, establishing a layout dependency effect polynomial model based on the layout dependency effect model fitting factor of the current device's initial standard cell layout; correcting the structural parameters of the current device's initial standard cell layout based on the layout dependency effect polynomial model to obtain corrected device structural parameters; establishing a compact model of the current device based on the corrected device structural parameters; and optimizing the current device's initial standard cell layout using a greedy algorithm based on the current device's compact model to obtain an optimized standard cell layout. Therefore, this application utilizes semiconductor process simulation and device simulation tools to model based on layout dependency effects, reducing test mask fabrication costs. By generating a compact model and combining it with a greedy algorithm to quickly generate optimized standard cell layouts, it improves the efficiency of standard cell layout optimization, guides the early stages of process development to maximize the performance of standard cell layouts, and shortens the R&D cycle. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A flowchart of a standard cell layout optimization method provided in an embodiment of this application is shown;

[0044] Figure 2 This illustration shows a schematic diagram of the oxide diffusion length effect of a planar MOSFET according to an embodiment of this application;

[0045] Figure 3 This illustration shows a schematic diagram of a standard cell layout for the FinFET oxidation diffusion length effect provided in an embodiment of this application;

[0046] Figure 4 A schematic diagram of a LOD simulation result provided in an embodiment of this application is shown;

[0047] Figure 5 This illustration shows a schematic diagram of the simulation results of an NFIN fitting factor provided in an embodiment of this application;

[0048] Figure 6 A schematic diagram of an algorithm topology provided in an embodiment of this application is shown;

[0049] Figure 7 A schematic diagram of a standard cell layout optimization device provided in an embodiment of this application is shown. Detailed Implementation

[0050] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0052] As described in the background section, the applicant's research has revealed that standard cell libraries are the core of digital circuit design. After logic synthesis, digital circuits integrate standard cell layouts using placement and routing algorithms, reducing the complexity of circuit layout design and manufacturing risks. To improve chip circuit performance, iterative optimization of standard cell libraries is a crucial aspect of PDK (Process Design Kit) development.

[0053] Since standard cells are the core of digital logic circuits, improving the performance of standard cells is of great significance to the overall circuit performance. Layout optimization of standard cells is one of the important optimization tasks.

[0054] As device dimensions shrink, layout dependency becomes significantly more pronounced, making layout a crucial factor influencing device performance fluctuations. Therefore, incorporating layout dependency into the initial stages of standard cell layout has become essential.

[0055] Among various standard cell optimization techniques, using the layout dependency effect for standard cell layout optimization can achieve optimal performance and minimal process fluctuations for standard cells.

[0056] As the size of integrated circuit devices continues to shrink, the fluctuations in device characteristics caused by changes in layout become more severe, resulting in deviations between actual device performance and simulation results. Improving layout-dependent effect modeling has become an indispensable part of integrated circuit design.

[0057] At 22nm and above, semiconductor device structures generally employ FinFETs (Fin Field-Effect Transistors). The three-dimensional effects of FinFET devices significantly increase the complexity of layout-dependent effect modeling. New processes also introduce new layout-dependent effects, resulting in LDE (Layout Dependent Effect) impacting device performance by approximately 30%. Layout-dependent modeling is an effective method for predicting the impact of layout on device performance. Traditional layout-dependent effect modeling processes require multiple iterations through LDE testing of layout design, mask fabrication testing, and more. At advanced process nodes, the cost of fabrication testing becomes even higher, and the development cycle becomes longer.

[0058] Therefore, how to improve the performance of standard cell layout as much as possible, reduce costs, and shorten the R&D cycle in the early stages of process development is a technical problem that needs to be solved in this field.

[0059] To address the aforementioned technical challenges, Design Technology Co-optimization (DTCO) has become a new focus in the industry. Compared to traditional device optimization methods, DTCO emphasizes integrating process flow and circuit design, exploring device performance at the circuit level to achieve optimal optimization results. DTCO has been applied to FinFET device optimization, and for N / P-type FinFET devices, it has been shown that co-optimization can improve device performance by over 20%. To further enhance performance, DTCO schemes for standard cells will be a new research area. Digital circuit standard cells often consist of multiple devices, and the interaction between these devices is key to standard cell optimization. Considering layout dependency effects as the core is the starting point for implementing standard cell DTCO schemes.

[0060] This application provides a standard cell layout optimization method, apparatus, system, and medium. The method includes: performing device electrical simulation based on the actual process flow and structural parameters of the current device's initial standard cell layout to obtain simulation results; calculating the simulation performance index of the current device's initial standard cell layout based on the simulation results; when the simulation performance index is consistent with the preset performance index, establishing a layout dependency effect polynomial model based on the layout dependency effect model fitting factor of the current device's initial standard cell layout; correcting the structural parameters of the current device's initial standard cell layout based on the layout dependency effect polynomial model to obtain corrected device structural parameters; establishing a compact model of the current device based on the corrected device structural parameters; and optimizing the current device's initial standard cell layout using a greedy algorithm based on the current device's compact model to obtain an optimized standard cell layout. Therefore, this application utilizes semiconductor process simulation and device simulation tools to model based on layout dependency effects, reducing test mask fabrication costs. By generating a compact model and combining it with a greedy algorithm to quickly generate optimized standard cell layouts, it improves the efficiency of standard cell layout optimization, guides the early stages of process development to maximize the performance of standard cell layouts, and shortens the R&D cycle.

[0061] Exemplary methods

[0062] See Figure 1 The flowchart shown is a standard cell layout optimization method provided in an embodiment of this application, including:

[0063] S101: Based on the actual process flow and structural parameters of the current device's initial standard cell layout, perform device electrical simulation to obtain simulation results.

[0064] In the embodiments of this application, device electrical simulation can be performed based on the actual process flow and structural parameters of the current device initial standard cell layout to obtain simulation results.

[0065] Specifically, a 3D device model can be created for the current device to obtain the initial process flow and device structural parameters used for the current device modeling, that is, the actual process flow and structural parameters of the initial standard cell layout of the current device.

[0066] The above process flow and structural parameters can be configured as an executable file template to perform device electrical simulation and obtain simulation results.

[0067] For example, taking FinFET as an example, the Sprocess tool in the Sentaurus process simulation software can be used to perform three-dimensional device modeling of FinFET fin field-effect transistors, and obtain the process flow and structural parameters used for FinFET device modeling.

[0068] Specifically, a Sentaurus project can be established by initializing the FinFFT process flow and device structure parameters according to the actual process. A .cmd file that can be executed by the Sentaurus Sprocess is written, containing device parameter settings, process simulation flow, and settings for the four terminals of the device (Source, Drain, Gate, and Bulk). The simulation file Mould.cmd is then run under Sprocess to complete the device model establishment. The SDevice tool is used to read the device structure information for physical solution, and the simulation results A are viewed using the Inspect tool.

[0069] S102: Calculate the simulation performance indicators of the initial standard cell layout of the current device based on the simulation results;

[0070] S103: When the simulation performance index is consistent with the preset performance index, establish a layout dependency effect polynomial model based on the layout dependency effect model fitting factor of the current device initial standard cell layout.

[0071] S104: The structural parameters of the initial standard cell layout of the current device are corrected according to the layout-dependent effect multinomial model to obtain the corrected device structural parameters.

[0072] In this embodiment, the simulation performance index of the initial standard cell layout of the current device can be calculated based on the simulation results. When the simulation performance index is consistent with the preset performance index, a layout dependency effect polynomial model is established based on the fitting factor of the layout dependency effect model of the initial standard cell layout of the current device. The structural parameters of the initial standard cell layout of the current device are corrected according to the layout dependency effect polynomial model to obtain the corrected device structural parameters.

[0073] Based on the simulation results above, the performance of the relevant devices can be calculated. Taking FinFET as an example, the simulation performance indicators can include: threshold voltage Vth, subthreshold slope SS, leakage current Id, etc., to determine whether the performance indicators of the process node (22nm, 14nm, 10nm, etc.) are met.

[0074] If the simulation performance index A meets the preset performance index B, then the process flow and structural parameters are compiled and output as a template file Mould.cmd written in sprocess language; if the device characteristic A does not meet the performance index B, the process flow or structural parameters are readjusted and the above steps are repeated to achieve the preset performance index B of the process node.

[0075] When the simulation performance index A meets the preset performance index B, taking the oxidation diffusion length effect (LOD, Length of Diffusion) as a layout-dependent effect as an example, the oxidation diffusion length effect is caused by the stress generated by shallow trench isolation (STI) on the channel, which leads to changes in device performance. This effect still exists in FinFET devices.

[0076] See Figure 2 The diagram shown is a schematic diagram of the oxidation diffusion length effect of a planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) provided in an embodiment of this application.

[0077] The LOD effect layout dependence factors of planar MOSFET devices include: the distances SA and SB from the poly silicon channel to the STI, the poly width L, and the device width W.

[0078] Based on the layout characteristics of FinFET devices, list the possible model fitting factors. Figure 3 This is a schematic diagram of a standard cell layout for the FinFET oxidation diffusion length effect provided in an embodiment of this application.

[0079] FinFET refers to the layout-dependent effect model fitting factor of the initial standard cell layout of the current device, which may include: fin width (WFIN), fin spacing (PFIN), and fin number (NFIN). Different test schemes can be established based on the above FIN layout-dependent effect factor by controlling variables.

[0080] For example, as shown in Table 1, initial values ​​for SA / SB, L, and W can be set, and different test groups can be established using WFIN, PFIN, and NFIN as variables.

[0081]

[0082] Table 1

[0083] See Figure 4 The diagram shown is a schematic of a LOD simulation result provided in an embodiment of this application. Based on the test scheme established in Table 1, device models with different structural parameters are established, and simulation is performed through SProcess, with stress calculation enabled in the simulation. Figure 4 The horizontal axis represents SA (μm), and the vertical axis represents the transistor linear threshold voltage Vtlin (mV).

[0084] By simulating the electrical characteristic curves using SDevice, the influence of the fitted variables on device performance was analyzed and determined, and the fitted variables were selected as model fitting factors. In this special case of LOD, the number of fins (NFIN) was used as a new fitting factor for the new layout dependence effect of FINFET LOD.

[0085] Preliminary polynomial modeling of FinFET layout-dependent effects is performed based on simulation data. More specifically, the FinFET LOD model can be modified based on the BSIM4 (Berkeley Short-channel IGFET Model) model. The LOD model polynomial in BSIM4 includes mobility and threshold voltage formulas.

[0086] Taking the threshold voltage model as a special case, the BSIM4 LOD threshold voltage formula is:

[0087] ;

[0088] Where VTH is the BSIM4 LOD threshold voltage, VTH0 is the reference threshold voltage, and KVTH0 is the process fitting parameter. The scaling factors are the distances sa and sb from the Poly silicon channel to the STI. and This is a reference value for the distance from the Poly silicon channel to the STI used for model calibration.

[0089] ;

[0090] Where L is the channel length, W is the fin width, P is the fin spacing, and XL and XW are the lithographic offsets. LOD is the diffusion length, L draw For the effective channel length, NFIN will be taken into account as a new fitting factor, see [link to documentation]. Figure 4 As shown, the threshold voltage offset rate of SA / SB changes, and the threshold change exhibits a quadratic curve characteristic. The corrected threshold voltage model formula is:

[0091] ;

[0092] It includes quadratic polynomial forms.

[0093] For the scaling factor, a new fitting factor NFIN needs to be considered, such as... Figure 5 The diagram shown is a simulation result of an NFIN fitting factor provided in an embodiment of this application. The horizontal axis represents NFIN, and the vertical axis represents the Dev threshold voltage offset rate (%). The threshold voltage offset rate decreases as the number of NFINs increases, and the threshold voltage is negatively correlated with NFIN. The formula for the corrected threshold proportionality coefficient is as follows:

[0094] .

[0095] This allows us to obtain the corrected device structure parameters, i.e., the corrected threshold scaling factor.

[0096] S105: Establish a compact model of the current device based on the modified device structure parameters.

[0097] In the embodiments of this application, a compact model of the current device can be established based on the modified device structure parameters.

[0098] Specifically, a new layout test set can be established, using NFIN, SA / SB, L, and W as variables to generate a test layout structure. The test structure should include large-size devices, small-size devices, short-channel devices, and narrow-channel devices.

[0099] Based on the established test layout atlas, device modeling and simulation were performed using Sprocess and SDevice tools to calculate the linear drain current Id_line, saturation drain current Id_sat, linear threshold voltage Vt_line, and saturation threshold voltage Vt_sat.

[0100] For example, a compact model, SPICEModel, can be created using model building software combined with Sentaurus simulation data.

[0101] S106: Based on the compact model of the current device, a greedy algorithm is used to optimize the initial standard cell layout of the current device to obtain an optimized standard cell layout.

[0102] In this embodiment, the initial standard cell layout of the current device can be optimized using a greedy algorithm based on the compact model of the current device to obtain an optimized standard cell layout.

[0103] Specifically, based on the layout dependency effect of the initial standard cell layout, a greedy algorithm can be used to optimize the layout dependency factor of the current device's initial standard cell layout to obtain an optimized standard cell layout.

[0104] For example, the basic parameters for standard cell layout optimization can be determined using the dependency factors of layout-dependent effects as variable parameters. For instance, the dependency factor SA / SB distance in the diffusion effect length of LOD can be used as a variable. Specifically, assume there are n different layout-dependent effects LDE1, LDE2, LDE3..., and each LDE has j layout-dependent factors Ki1, Ki2, Ki3, Ki4..., Kij; the initial standard cell layout-dependent factor Kij is Vij.

[0105] The initial standard cell layout of the current device is optimized using a greedy algorithm. The core strategy of the greedy algorithm is to ensure that the performance and power consumption meet the design requirements, while minimizing the area.

[0106] Specifically, different map dependency effects are considered as optimization paths, and weights λi are assigned to different map dependency effects. For example... Figure 6 As shown, for layout optimization path selection, the device has i different optimization paths, and the next optimization path is determined according to the weight λi value.

[0107] After the current path optimization is completed, the remaining LDE optimization paths will be expanded again, and the above process will be executed. This iterative process continues until all layout dependencies are optimized, and the standard cell layout optimization ends.

[0108] Furthermore, in this embodiment of the application, in order to evaluate the effect of optimization, a test circuit can be established to obtain the performance, power consumption and area of ​​the optimized standard cell layout.

[0109] Specifically, the test circuit can be used to evaluate the PPA (Performance Power Area) each time an optimization path is switched to determine whether to end the current layout dependency optimization.

[0110] When the optimization is complete, if the performance of the optimized standard cell layout is greater than or equal to the first preset value, the power consumption is less than or equal to the second preset value, and the area is less than or equal to the third preset value, then the optimized standard cell layout can be used as the final standard cell layout.

[0111] If the optimized standard cell layout does not meet the above conditions, the device structure and parameters can be readjusted for re-optimization.

[0112] This application provides a standard cell layout optimization method, which includes: performing device electrical simulation based on the actual process flow and structural parameters of the current device's initial standard cell layout to obtain simulation results; calculating the simulation performance index of the current device's initial standard cell layout based on the simulation results; when the simulation performance index is consistent with the preset performance index, establishing a layout dependency effect polynomial model based on the layout dependency effect model fitting factor of the current device's initial standard cell layout; correcting the structural parameters of the current device's initial standard cell layout based on the layout dependency effect polynomial model to obtain corrected device structural parameters; establishing a compact model of the current device based on the corrected device structural parameters; and optimizing the current device's initial standard cell layout using a greedy algorithm based on the current device's compact model to obtain an optimized standard cell layout. Therefore, this application utilizes semiconductor process simulation and device simulation tools to model based on layout dependency effects, reducing test mask fabrication costs. By generating a compact model and combining it with a greedy algorithm to quickly generate optimized standard cell layouts, it improves the efficiency of standard cell layout optimization, guides the early stages of process development to maximize the performance of standard cell layouts, and shortens the R&D cycle.

[0113] Exemplary device

[0114] See Figure 7 The diagram shown is a schematic of a standard cell layout optimization device provided in an embodiment of this application, comprising:

[0115] Simulation unit 201 is used to perform electrical simulation of the device based on the actual process flow and structural parameters of the current device's initial standard cell layout, and to obtain simulation results;

[0116] The calculation unit 202 is used to calculate the simulation performance index of the initial standard cell layout of the current device based on the simulation results;

[0117] Establishment unit 203 is used to establish a layout dependency effect multinomial model based on the layout dependency effect model fitting factor of the current device initial standard cell layout when the simulation performance index is consistent with the preset performance index.

[0118] The correction unit 204 is used to correct the structural parameters of the initial standard cell layout of the current device according to the layout dependency effect multinomial model, so as to obtain the corrected device structural parameters.

[0119] Model unit 205 is used to establish a compact model of the current device based on the corrected device structure parameters;

[0120] The optimization unit 206 is used to optimize the initial standard cell layout of the current device using a greedy algorithm based on the compact model of the current device, so as to obtain an optimized standard cell layout.

[0121] In one possible implementation, the optimization unit is specifically used for:

[0122] Based on the layout dependency effect of the initial standard cell layout, the layout dependency factor of the layout dependency effect of the current device's initial standard cell layout is optimized using the greedy algorithm to obtain the optimized standard cell layout.

[0123] One possible implementation also includes:

[0124] Test unit, used to establish test circuitry to obtain the performance, power consumption, and area of ​​the optimized standard cell layout;

[0125] The comparison unit is used to select the optimized standard cell layout as the final standard cell layout when the performance of the optimized standard cell layout is greater than or equal to a first preset value, the power consumption is less than or equal to a second preset value, and the area is less than or equal to a third preset value.

[0126] In one possible implementation, the current device includes a finned field-effect transistor device; the layout-dependent effect model fitting factors include fin width, fin spacing, and number of fins.

[0127] This application provides a standard cell layout optimization device. The method applied to this device includes: performing electrical simulation of the device based on the actual process flow and structural parameters of the initial standard cell layout of the current device, and obtaining simulation results; calculating the simulation performance index of the initial standard cell layout of the current device based on the simulation results; when the simulation performance index is consistent with the preset performance index, establishing a layout dependency effect polynomial model based on the fitting factor of the layout dependency effect model of the initial standard cell layout of the current device; correcting the structural parameters of the initial standard cell layout of the current device based on the layout dependency effect polynomial model, and obtaining the corrected device structural parameters; establishing a compact model of the current device based on the corrected device structural parameters; and optimizing the initial standard cell layout of the current device using a greedy algorithm based on the compact model of the current device, obtaining an optimized standard cell layout. Thus, this application utilizes semiconductor process simulation and device simulation tools to model based on layout dependency effects, reducing the cost of test mask fabrication. By generating a compact model and combining it with a greedy algorithm to quickly generate optimized standard cell layouts, it improves the efficiency of standard cell layout optimization, guides the early stages of process development to maximize the performance of standard cell layouts, and shortens the R&D cycle.

[0128] Based on the above embodiments, this application provides a standard cell layout optimization system, including:

[0129] Memory, used to store computer programs;

[0130] A processor is used to implement the steps of the standard cell layout optimization method described above when executing the computer program.

[0131] Based on the above embodiments, this application also provides a computer-readable medium storing a computer program, which, when processed and executed, implements the steps of the standard cell layout optimization method described above.

[0132] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0133] The aforementioned computer-readable medium may be included in the aforementioned system, or it may exist independently and not assembled into the system.

[0134] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts.

[0135] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0136] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A standard cell layout optimization method, characterized in that, include: Based on the actual process flow and structural parameters of the current device's initial standard cell layout, electrical simulation of the device is performed to obtain simulation results; Calculate the simulation performance indicators of the initial standard cell layout of the current device based on the simulation results; When the simulation performance index is consistent with the preset performance index, a multinomial model of the layout dependence effect is established based on the fitting factor of the layout dependence effect model of the initial standard cell layout of the current device. The structural parameters of the initial standard cell layout of the current device are corrected according to the layout-dependent effect multinomial model to obtain the corrected device structural parameters; A compact model of the current device is established based on the corrected device structure parameters; Based on the compact model of the current device, a greedy algorithm is used to optimize the initial standard cell layout of the current device to obtain an optimized standard cell layout. The optimization of the initial standard cell layout of the current device using a greedy algorithm to obtain an optimized standard cell layout includes: Based on the layout dependency effect of the initial standard cell layout, the greedy algorithm is used to optimize the layout dependency factor of the layout dependency effect of the current device's initial standard cell layout to obtain the optimized standard cell layout. The layout dependency factor includes the distances SA and SB from the Poly silicon channel to the STI, the Poly width L, and the device width W.

2. The method according to claim 1, characterized in that, Also includes: Establish a test circuit to obtain the performance, power consumption, and area of ​​the optimized standard cell layout; When the performance of the optimized standard cell layout is greater than or equal to a first preset value, the power consumption is less than or equal to a second preset value, and the area is less than or equal to a third preset value, the optimized standard cell layout is used as the final standard cell layout.

3. The method according to any one of claims 1-2, characterized in that, The current device includes a finned field-effect transistor (FFET) device; the layout-dependent effect model fitting factors include fin width, fin spacing, and number of fins.

4. A standard cell layout optimization device, characterized in that, include: The simulation unit is used to perform electrical simulation of the device based on the actual process flow and structural parameters of the current device's initial standard cell layout, and to obtain simulation results; A computing unit is used to calculate the simulation performance indicators of the initial standard cell layout of the current device based on the simulation results; A unit is established to establish a layout dependency effect multinomial model based on the layout dependency effect model fitting factor of the current device's initial standard cell layout when the simulation performance index is consistent with the preset performance index. The correction unit is used to correct the structural parameters of the initial standard cell layout of the current device according to the layout dependency effect multinomial model, so as to obtain the corrected device structural parameters. A model unit is used to establish a compact model of the current device based on the corrected device structure parameters; The optimization unit is used to optimize the initial standard cell layout of the current device using a greedy algorithm based on the compact model of the current device, so as to obtain an optimized standard cell layout. The optimization unit is specifically used for: Based on the layout dependency effect of the initial standard cell layout, the greedy algorithm is used to optimize the layout dependency factor of the layout dependency effect of the current device's initial standard cell layout to obtain the optimized standard cell layout. The layout dependency factor includes the distances SA and SB from the Poly silicon channel to the STI, the Poly width L, and the device width W.

5. The apparatus according to claim 4, characterized in that, Also includes: The test unit is used to establish a test circuit to obtain the performance, power consumption, and area of ​​the optimized standard cell layout; The comparison unit is used to select the optimized standard cell layout as the final standard cell layout when the performance of the optimized standard cell layout is greater than or equal to a first preset value, the power consumption is less than or equal to a second preset value, and the area is less than or equal to a third preset value.

6. The apparatus according to any one of claims 4-5, characterized in that, The current device includes a finned field-effect transistor (FFET) device; the layout-dependent effect model fitting factors include fin width, fin spacing, and number of fins.

7. A standard cell layout optimization system, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the standard cell layout optimization method as described in any one of claims 1-3 when executing the computer program.

8. A computer-readable medium, characterized in that, The computer-readable medium stores a computer program that, when processed and executed, implements the steps of the standard cell layout optimization method as described in any one of claims 1-3.

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