A low-capacitance silicon-controlled rectifier

Abstract

The present invention provides a low-capacitance silicon-controlled rectifier, relating to the field of semiconductor technology, comprising: a substrate, an N-well region, a first P-well region, and a first P-type injection region formed above the substrate; a first N-type injection region and a second P-type injection region formed in the N-well region, a second N-type injection region and a third P-type injection region formed in the first P-well region, and a third N-type injection region formed at the junction of the N-well region and the first P-well region; the first N-type injection region and the second P-type injection region connected to an anode terminal, and the first P-type injection region and the second N-type injection region connected to a cathode terminal; and a control circuit respectively connected to the third P-type injection region, the cathode terminal, and the anode terminal, the control circuit being configured to control the on / off connection between the third P-type injection region and the cathode terminal. The beneficial effect is that lower capacitance can be achieved while maintaining the positive and negative current discharge paths unchanged and the leakage current close to each other.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low-capacitance silicon-controlled rectifier. Background Art

[0002] In recent years, the rapid development of integrated circuit manufacturing technology has led to a rapid upgrade of electronic products. To ensure the quality and reliability of electronic products, their chips and external interface circuits must have a certain level of ESD (electrostatic discharge) resistance, thus requiring an increasing number of protection devices. Thyristors, as a protection device with strong robustness per unit area and low parasitic capacitance, are widely used in various products.

[0003] The structure of traditional SCR (Silicon Controlled Rectifier) ​​is as follows Figure 1 As shown in Figure 1, two back-to-back transistors are connected in series, and there is an N+ between the N-well region NW and the P-well region PW to reduce the trigger voltage. This structure forms a P+ / NW / PW / N+ path between the anode and cathode to discharge forward ESD current; and a P+ / PW / NW / N+ path between the cathode and anode to discharge reverse ESD current. Its equivalent circuit is shown in Figure 1. Figure 2 As shown in the figure, when the anode-to-cathode pulse current gradually increases, the diode formed by N+ / PW will first undergo avalanche breakdown. Subsequently, the current in the diode gradually increases. When the voltage across resistors Rnw and Rpw reaches 0.7V, the PNP transistor P+ / NW / PW and the NPN transistor NW / PW / N+ will successively turn on, forming a positive feedback path in the diode, rapidly dissipating the forward ESD current. When the cathode-to-anode pulse current gradually increases, causing the voltage across NW and PW to reach 0.7V, the diode N+ / PW will turn on, forming a path in the diode, rapidly dissipating the reverse ESD current.

[0004] In addition, more and more electronic products have data interfaces above USB3.0 and HDMI1.4, and their transmission rates reach above GHz. Protective devices need to provide lower capacitance to ensure the integrity of the transmission signal, so capacitance has become one of the key parameters of protective devices. Figure 1 In the traditional structure shown in the figure, the parasitic capacitance of the device is mainly formed by the two junctions of NW / PW and NW / P substrate. The equivalent circuit of the capacitance is as follows: Figure 3As shown in the figure, in the design of such products, the contradiction between the positive correlation between current discharge capability and area and the negative correlation between capacitance and area persists, making it difficult to achieve both high discharge capability and low capacitance. Furthermore, the application environment of such products also places a high premium on device leakage at operating voltages, often requiring leakage in the nanoamp range. Therefore, how to further reduce capacitance while maintaining current discharge capability and leakage has become a pressing issue. Summary of the Invention

[0005] In view of the problems existing in the prior art, the present invention provides a low-capacitance silicon-controlled rectifier, comprising:

[0006] A substrate, with an N-well region, a first P-well region, and a first P-type implantation region formed on the substrate;

[0007] A first N-type implantation region and a second P-type implantation region are formed in the N-well region, a second N-type implantation region and a third P-type implantation region are formed in the first P-well region, and a third N-type implantation region is formed at the junction of the N-well region and the first P-well region;

[0008] The first N-type injection region and the second P-type injection region are connected to an anode terminal, and the first P-type injection region and the second N-type injection region are connected to a cathode terminal;

[0009] A control circuit is connected to the third P-type injection region, the cathode terminal and the anode terminal respectively, and is used to control the connection and disconnection of the third P-type injection region and the cathode terminal.

[0010] Preferably, the control circuit includes:

[0011] A voltage dividing branch, the voltage dividing branch being connected to the anode terminal and the cathode terminal respectively, and the voltage dividing branch comprising two voltage dividing components connected in series;

[0012] a first enhancement-mode transistor, wherein a transistor substrate of the first enhancement-mode transistor is connected to a source of the first enhancement-mode transistor and the cathode terminal, and a drain of the first enhancement-mode transistor is connected to the third P-type implantation region;

[0013] A protection resistor, one end of which is connected between the two voltage divider components, and the other end of which is connected to the gate of the first enhancement mode transistor.

[0014] Preferably, the resistance of the equivalent resistor of the voltage divider branch is at the MΩ level.

[0015] Preferably, the two voltage divider components are a first resistor and a second resistor, one end of the first resistor is connected to the anode terminal, the other end of the first resistor is respectively connected to one end of the second resistor and one end of the protective resistor, and the other end of the second resistor is connected to the cathode terminal.

[0016] Preferably, the two voltage-dividing components are respectively a third resistor and a second enhancement-mode transistor, one end of the third resistor is connected to the anode terminal, and the other end of the third resistor is respectively connected to the drain of the second enhancement-mode transistor and one end of the protection resistor;

[0017] The gate of the second enhancement mode transistor is connected to the source of the second enhancement mode transistor, and the source of the second enhancement mode transistor is connected to the transistor substrate of the second enhancement mode transistor and the cathode terminal respectively.

[0018] Preferably, the two voltage dividing components are respectively a third enhancement-mode transistor and a fourth enhancement-mode transistor, the drain of the third enhancement-mode transistor is connected to the anode terminal, the gate of the third enhancement-mode transistor is connected to the source of the third enhancement-mode transistor, and the source of the third enhancement-mode transistor is respectively connected to the transistor substrate of the third enhancement-mode transistor, the drain of the fourth enhancement-mode transistor, and one end of the protection resistor;

[0019] The gate of the fourth enhancement-mode transistor is connected to the source of the fourth enhancement-mode transistor, and the source of the fourth enhancement-mode transistor is respectively connected to the transistor substrate of the fourth enhancement-mode transistor and the cathode terminal.

[0020] Preferably, the first enhancement-mode transistor is an enhancement-mode NMOS transistor.

[0021] Preferably, a second P-type well region is also formed on the substrate, in which a fourth N-type injection region serving as the drain of the first enhancement-mode transistor, a fifth N-type injection region serving as the source of the first enhancement-mode transistor, and a fourth P-type injection region of the transistor substrate serving as the source of the first enhancement-mode transistor are formed, and the gate of the first enhancement-mode transistor is formed above between the fourth N-type injection region and the fifth N-type injection region of the second P-type well region.

[0022] Preferably, the second enhancement mode transistor is an enhancement mode NMOS transistor.

[0023] Preferably, the third enhancement-mode transistor and the fourth enhancement-mode transistor are both enhancement-mode NMOS transistors.

[0024] The above technical solution has the following advantages or beneficial effects:

[0025] 1) Ability to achieve lower capacitance while keeping the positive and negative current discharge paths unchanged and leakage currents close to each other;

[0026] 2) By adjusting the switching state of the control circuit based on different working environments, the low capacitance and low leakage of the low-capacitance silicon-controlled rectifier can be achieved in different working environments while maintaining the positive and negative current discharge capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of a traditional thyristor;

[0028] Figure 2 This is a schematic diagram of the equivalent circuit of a traditional thyristor;

[0029] Figure 3 This is a schematic diagram of the equivalent circuit of the capacitor of a traditional thyristor;

[0030] Figure 4 FIG1 is a structural diagram of a low-capacitance silicon-controlled rectifier in a preferred embodiment of the present invention;

[0031] Figure 5 FIG1 is a schematic diagram of an equivalent circuit of a low-capacitance silicon-controlled rectifier in a preferred embodiment of the present invention;

[0032] Figure 6 FIG1 is a schematic diagram of an equivalent circuit of a capacitor of a low-capacitance silicon-controlled rectifier in a preferred embodiment of the present invention;

[0033] Figure 7 FIG1 is a schematic diagram comparing the capacitance of a conventional circuit and an embodiment of the present invention under 1 MHz frequency test conditions in a preferred embodiment of the present invention;

[0034] Figure 8 FIG. 1 is a schematic diagram comparing the leakage stages of a conventional circuit and a circuit of the present invention under the same IV test conditions in a preferred embodiment of the present invention;

[0035] Figure 9 FIG1 is a schematic diagram of an equivalent circuit of a low-capacitance silicon-controlled rectifier according to an embodiment of the present invention;

[0036] Figure 10 FIG. 1 is a schematic diagram of an equivalent circuit of a low-capacitance silicon-controlled rectifier in another embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0038] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a low-capacitance silicon-controlled rectifier is provided. Figure 4 Shown, including:

[0039] A substrate Psub, with an N-well region NW, a first P-well region PW1 and a first P-type implantation region 201 formed on the substrate Psub;

[0040] A first N-type implant region 202 and a second P-type implant region 203 are formed in the N-well region NW, a second N-type implant region 204 and a third P-type implant region 205 are formed in the first P-well region PW1, and a third N-type implant region 213 is formed at the junction of the N-well region NW and the first P-well region PW1;

[0041] The first N-type implant region 202 and the second P-type implant region 203 are connected to an anode terminal Anode, and the first P-type implant region 201 and the second N-type implant region 204 are connected to a cathode terminal Cathode;

[0042] The control circuit 103 is connected to the third P-type injection region 205 , the cathode terminal Cathode and the anode terminal Anode respectively. The control circuit 103 is used to control the on-off of the third P-type injection region 205 and the cathode terminal Cathode.

[0043] Specifically, in this embodiment, the N-well region NW and the first P-well region PW1, including the first N-type injection region 202, the second P-type injection region 203, the second N-type injection region 204, the third P-type injection region 205 and the third N-type injection region 213, can be regarded as being formed by a NPN transistor and a PNP transistor connected in series. The overall equivalent circuit is as follows: Figure 5 shown.

[0044] like Figure 4 and Figure 5 As shown, a PNP transistor, an NPN transistor, a P-well resistor Rpw, and an N-well resistor Rnw form a first discharge path 101 of a low-capacitance silicon-controlled rectifier, which is used to discharge forward ESD current from the anode terminal Anode to the cathode terminal Cathode. The emitter of the PNP transistor is connected to the anode terminal Anode, the collector of the PNP transistor is connected to one end of the P-well resistor Rpw and the base of the NPN transistor, the other end of the P-well resistor is connected to the control circuit 103, the base of the PNP transistor is connected to the collector of the NON transistor and one end of the N-well resistor Rnw, the other end of the N-well resistor Rnw is connected to the anode terminal Anode, and the emitter of the NPN transistor is connected to the cathode terminal Cathode.

[0045] A first P-type implant region 201 connected to the cathode terminal Cathode and a first N-type implant region 202 connected to the anode terminal Anode form a second discharge path 102 of the low-capacitance silicon-controlled rectifier, which is used to discharge negative ESD current from the cathode terminal Cathode to the anode terminal Anode. Second discharge path 102 is a diode D, with the cathode of diode D connected to the anode terminal Anode and the anode of diode D connected to the cathode terminal Cathode.

[0046] The control circuit 103 achieves low capacitance and low leakage by controlling the disconnection and grounding states of the base region PW of the NPN transistor in the first discharge path 101 .

[0047] In a preferred embodiment of the present invention, Figure 4 and Figure 5 As shown, the control circuit 103 includes:

[0048] A voltage dividing branch, the voltage dividing branch is connected to the anode terminal Anode and the cathode terminal Cathode respectively, and the voltage dividing branch includes two voltage dividing components connected in series;

[0049] a first enhancement mode transistor NMOS1, wherein a transistor substrate of the first enhancement mode transistor NMOS1 is connected to a source and a cathode of the first enhancement mode transistor NMOS1, and a drain of the first enhancement mode transistor NMOS1 is connected to the third P-type implantation region 205;

[0050] A protection resistor R, one end of the protection resistor R is connected between the two voltage dividing components, and the other end of the protection resistor R is connected to the gate of the first enhancement mode transistor NMOS1.

[0051] Specifically, in this embodiment, the voltage divider branch is used to provide a suitable gate voltage to the first enhancement-mode transistor NMOS1, enabling switching. Because the voltage divider branch directly connects the anode terminal Anode and the cathode terminal Cathode, to limit leakage current in this voltage divider branch, in a preferred embodiment of the present invention, the equivalent resistance of the voltage divider branch is in the MΩ range. That is, the sum of the resistances of the two voltage divider components should reach the MΩ level.

[0052] The protection resistor R is a gate voltage protection resistor of the first enhancement mode transistor NMOS1, and is used to prevent the gate from being broken down and causing damage to the circuit when the circuit is working.

[0053] In a preferred embodiment of the present invention, the first enhancement mode transistor NMOS1 is an enhancement mode NMOS tube, such as Figure 4As shown, a second P-type well region PW2 is further formed on the substrate Psub. A fourth N-type implantation region 206 serving as the drain of the first enhancement-mode transistor NMOS1, a fifth N-type implantation region 207 serving as the source of the first enhancement-mode transistor NMOS1, and a fourth P-type implantation region 208 of the transistor substrate serving as the source of the first enhancement-mode transistor NMOS1 are formed in the second P-type well region PW2. The gate of the first enhancement-mode transistor NMOS1 is formed above the fourth N-type implantation region 206 and the fifth N-type implantation region 207 of the second P-type well region PW2.

[0054] The fourth N-type implant region 206, serving as the drain of the first enhancement-mode transistor NMOS1, is connected to the third P-type implant region 205 in the first discharge path 101 via a metal wire. The fifth N-type implant region 207, serving as the source of the first enhancement-mode transistor NMOS1, is connected to the cathode terminal Cathode. The fourth P-type implant region 208 extends from the NMOS substrate PW2 and connects to the fifth N-type implant region 207 to prevent the second P-well region PW2 from floating. Preferably, the threshold voltage Vth of the first enhancement-mode transistor NMOS1 is selected in accordance with the operating voltage of the circuit design, with a typical threshold voltage Vth range of 0.5V to 10V.

[0055] In this embodiment, the two voltage-dividing components may be resistors, or other components that can be used as resistors. When both voltage-dividing components are resistors, as shown in FIG. Figure 4 and Figure 5 As shown, in a preferred embodiment of the present invention, the two voltage dividing components are a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to the anode terminal Anode, the other end of the first resistor R1 is respectively connected to one end of the second resistor R2 and one end of the protection resistor R, and the other end of the second resistor R2 is connected to the cathode terminal Cathode.

[0056] Specifically, in this embodiment, the low-capacitance silicon-controlled rectifier of the present invention is connected in parallel across the protected device to protect it. The switching behavior of the control circuit 103 under varying operating conditions within the overall circuit achieves low capacitance and low leakage characteristics while maintaining both positive and negative ESD current dissipation capabilities. The following describes its operating mechanism using a common 3.3V differential data transmission line as an example.

[0057] During signal transmission, the entire circuit focuses on the capacitance value. At this time, the first enhancement mode transistor NMOS1 in the control circuit 103 is in the off state, so that the third P-type injection region 205 in the first discharge path 101 is equivalent to an open circuit. At this time, the equivalent capacitance circuit of the circuit is as follows: Figure 6 As shown. Figure 3 The equivalent capacitance circuit of the traditional circuit, Figure 6 203 / NW, NW / PW1NW / Psub, PW1 / 204 are equivalent to Figure 3 In the P+ / NW, NW / PWNW / Psub, PW / N+, it can be seen that the present invention reconnects the short-circuited PW / N+ capacitor in series to the overall circuit. According to the principle of capacitor series connection, the equivalent capacitance of the overall circuit of the present invention is reduced. Figure 7 This is a comparison of the capacitance of a conventional circuit and an embodiment of the present invention under the same conditions, at a frequency of 1 MHz. It can be seen that within the voltage range of signal transmission, the circuit design of the present invention reduces the capacitance by about 30% compared to the conventional circuit design.

[0058] Considering that the anode potential of the anode terminal Anode reaches the working voltage, the overall circuit is concerned about the leakage size at this time. The gate-source voltage of the first enhancement transistor NMOS1 is obtained by dividing the first resistor R1 and the second resistor R2. By selecting a suitable resistance ratio of the first resistor R1 and the second resistor R2, the threshold voltage Vth of the first enhancement transistor NMOS1 can be matched, so that when the anode potential reaches the working voltage, the first enhancement transistor NMOS1 changes from the off state to the on state. The purpose of the first enhancement transistor NMOS1 changing to the on state is to connect the first P-well region PW1 of the NPN transistor base region in the first discharge path 101 to the cathode terminal Cathode through the third P-type injection region 205, thereby avoiding the leakage caused by the floating of the NPN transistor base region being amplified by its own current amplification characteristics, thereby causing the overall circuit leakage problem to be too large. Figure 8 This is a comparison of the leakage stage of the traditional circuit and the circuit of the present invention under the same IV test conditions; at the same time, in order to highlight the role of the switching state conversion of the first enhancement mode transistor NMOS1 emphasized by the present invention, as a comparison, Figure 8 A set of leakage test data for the circuit that fails to turn on due to unreasonable design of NMOS threshold voltage is added. Comparing the leakage of each circuit under 3.3V voltage, the leakage of the traditional circuit is 40nA, while the leakage of the first enhancement transistor NMOS1 of the circuit of the present invention is 43nA when the NMOS is turned on, and the leakage of the first enhancement transistor NMOS1 of the circuit of the present invention is 144nA when the NMOS is not turned on; comparing the leakage of each circuit under 5V voltage, the leakage of the traditional circuit is 50nA, while the leakage of the first enhancement transistor NMOS1 of the circuit of the present invention is 50nA when the NMOS is turned on, and the leakage of the first enhancement transistor NMOS1 of the circuit of the present invention is 340nA when the NMOS is not turned on. It can be seen that the circuit of the present invention achieves a reasonable switching state conversion of the control circuit 103 by matching the NMOS threshold voltage Vth, which can completely avoid the problem of excessive leakage caused by the floating base region of the NPN transistor in the circuit, and achieve the same leakage level as the traditional circuit.

[0059] In summary, compared to conventional circuit designs, the low-capacitance silicon-controlled rectifier of the present invention can achieve lower capacitance while maintaining the positive and negative current discharge paths and leakage levels unchanged.

[0060] Considering the overall circuit leakage level, the sum of the resistance values ​​of the first resistor R1 and the second resistor R2 in the control circuit 103 should reach the MΩ level. A common method for achieving large resistance in semiconductor technology is to use long polysilicon resistors. However, achieving MΩ-level resistance through long polysilicon resistors consumes a large layout area. For applications that are particularly concerned about the size and cost of protective devices, a large layout area may reduce the practicality of the protective device. Therefore, as a preferred embodiment of the present invention, the voltage divider branch is optimized, and the optimized equivalent circuit is as follows: Figure 9 As shown, the two voltage dividing components are respectively a third resistor R3 and a second enhancement mode transistor NMOS2, one end of the third resistor R3 is connected to the anode terminal Anode, and the other end of the third resistor R3 is respectively connected to the drain of the second enhancement mode transistor NMOS2 and one end of the protection resistor R;

[0061] The gate of the second enhancement mode transistor NMOS2 is connected to the source of the second enhancement mode transistor NMOS2 , and the source of the second enhancement mode transistor NMOS2 is respectively connected to the transistor substrate and the cathode of the second enhancement mode transistor NMOS2 .

[0062] In this embodiment, Figure 4 and Figure 5 The second resistor R2 in the control circuit 103 is replaced by a second enhancement-mode transistor NMOS2, which is an enhancement-mode NMOS with a gate-source short circuit. Under common processes, the leakage of enhancement-mode NMOS is basically at the nA level. Figure 9 In the circuit design, due to the gate-source short circuit, the second enhancement mode transistor NMOS2 is always in the off state and acts as a MΩ resistor. Figure 9 The third resistor R3 is equivalent to Figure 4 and Figure 5 The first resistor R1 and the third resistor R3 in the embodiment are implemented as multiple resistance levels by using long polysilicon resistors of different lengths. Similarly, through the voltage divider relationship between the third resistor R3 and the second enhancement-mode transistor NMOS2, a suitable gate voltage is transmitted to the first enhancement-mode transistor NMOS1, thereby enabling it to achieve a reasonable switching state transition. Furthermore, the layout area of ​​the NMOS is much smaller than that of a MΩ-class polysilicon resistor. Therefore, the design of the control circuit 103 in this embodiment can significantly reduce the layout area consumed, improving the practicality of the overall circuit.

[0063] As a preferred embodiment of the present invention, Figure 10As shown, the two voltage dividing components are respectively a third enhancement mode transistor NMOS3 and a fourth enhancement mode transistor NMOS4, the drain of the third enhancement mode transistor NMOS3 is connected to the anode terminal, the gate of the third enhancement mode transistor NMOS3 is connected to the source of the third enhancement mode transistor NMOS3, and the source of the third enhancement mode transistor NMOS3 is respectively connected to the transistor substrate of the third enhancement mode transistor NMOS3, the drain of the fourth enhancement mode transistor NMOS4 and one end of the protection resistor R;

[0064] The gate of the fourth enhancement mode transistor NMOS4 is connected to the source of the fourth enhancement mode transistor NMOS4 , and the source of the fourth enhancement mode transistor NMOS4 is respectively connected to the transistor substrate and the cathode of the fourth enhancement mode transistor NMOS4 .

[0065] Specifically, in this embodiment, Figure 4 and Figure 5 The first resistor R1 and the second resistor R2 in the control circuit 103 are replaced by a third enhancement-mode transistor NMOS3 and a fourth enhancement-mode transistor NMOS4, respectively. Both the third and fourth enhancement-mode transistors NMOS3 and NMOS4 are enhancement-mode NMOS transistors with their gates shorted to the source. These third and fourth enhancement-mode transistors NMOS3 and NMOS4, which are always off, act as the required MΩ-level resistors. This circuit design replaces the larger polysilicon resistors with smaller NMOS transistors, further reducing the layout area.

[0066] In a preferred embodiment of the present invention, the second enhancement mode transistor is an enhancement mode NMOS transistor.

[0067] In a preferred embodiment of the present invention, the third enhancement-mode transistor and the fourth enhancement-mode transistor are both enhancement-mode NMOS transistors.

[0068] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A low-capacitance silicon-controlled rectifier, characterized in that: include: A substrate, with an N-well region, a first P-well region, and a first P-type implantation region formed on the substrate; A first N-type implantation region and a second P-type implantation region are formed in the N-well region, a second N-type implantation region and a third P-type implantation region are formed in the first P-well region, and a third N-type implantation region is formed at the junction of the N-well region and the first P-well region; The first N-type injection region and the second P-type injection region are connected to an anode terminal, and the first P-type injection region and the second N-type injection region are connected to a cathode terminal; a control circuit, connected to the third P-type injection region, the cathode terminal, and the anode terminal, respectively, and configured to control the connection and disconnection between the third P-type injection region and the cathode terminal; The control circuit comprises: A voltage dividing branch, the voltage dividing branch being connected to the anode terminal and the cathode terminal respectively, and the voltage dividing branch comprising two voltage dividing components connected in series; a first enhancement-mode transistor, wherein a transistor substrate of the first enhancement-mode transistor is connected to a source of the first enhancement-mode transistor and the cathode terminal, and a drain of the first enhancement-mode transistor is connected to the third P-type implantation region; A protection resistor, one end of which is connected between the two voltage divider components, and the other end of which is connected to the gate of the first enhancement mode transistor.

2. The low-capacitance silicon-controlled rectifier according to claim 1, characterized in that: The equivalent resistance of the voltage dividing branch is in the MΩ level.

3. The low-capacitance silicon-controlled rectifier according to claim 1, characterized in that: The two voltage divider components are a first resistor and a second resistor, one end of the first resistor is connected to the anode terminal, the other end of the first resistor is respectively connected to one end of the second resistor and one end of the protection resistor, and the other end of the second resistor is connected to the cathode terminal.

4. The low-capacitance silicon-controlled rectifier according to claim 1, characterized in that: The two voltage dividing components are respectively a third resistor and a second enhancement-mode transistor, one end of the third resistor is connected to the anode terminal, and the other end of the third resistor is respectively connected to the drain of the second enhancement-mode transistor and one end of the protection resistor; The gate of the second enhancement mode transistor is connected to the source of the second enhancement mode transistor, and the source of the second enhancement mode transistor is connected to the transistor substrate of the second enhancement mode transistor and the cathode terminal respectively.

5. The low-capacitance silicon-controlled rectifier according to claim 1, characterized in that: The two voltage dividing components are respectively a third enhancement-mode transistor and a fourth enhancement-mode transistor, the drain of the third enhancement-mode transistor is connected to the anode terminal, the gate of the third enhancement-mode transistor is connected to the source of the third enhancement-mode transistor, and the source of the third enhancement-mode transistor is respectively connected to the transistor substrate of the third enhancement-mode transistor, the drain of the fourth enhancement-mode transistor, and one end of the protection resistor; The gate of the fourth enhancement-mode transistor is connected to the source of the fourth enhancement-mode transistor, and the source of the fourth enhancement-mode transistor is respectively connected to the transistor substrate of the fourth enhancement-mode transistor and the cathode terminal.

6. The low-capacitance silicon-controlled rectifier according to claim 1, characterized in that: The first enhancement mode transistor is an enhancement mode NMOS transistor.

7. The low-capacitance silicon-controlled rectifier according to claim 6, characterized in that: A second P-type well region is also formed on the substrate, in which a fourth N-type injection region serving as the drain of the first enhancement-mode transistor, a fifth N-type injection region serving as the source of the first enhancement-mode transistor, and a fourth P-type injection region of the transistor substrate serving as the source of the first enhancement-mode transistor are formed. The gate of the first enhancement-mode transistor is formed above between the fourth N-type injection region and the fifth N-type injection region of the second P-type well region.

8. The low-capacitance silicon-controlled rectifier according to claim 4, characterized in that: The second enhancement mode transistor is an enhancement mode NMOS transistor.

9. The low-capacitance silicon-controlled rectifier according to claim 5, characterized in that: The third enhancement-mode transistor and the fourth enhancement-mode transistor are both enhancement-mode NMOS transistors.

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