Planar SiC MOSFET Device

Abstract

The present invention discloses a planar SiC MOSFET device, comprising: an anti-JFET region is formed on the surface of a drift region between two adjacent channel regions; two or more first ion implantation regions in the channel region are arranged such that the deeper the implantation peak position, the larger the implantation peak; the shallower the implantation peak position, the smaller the implantation peak; the implantation peak position and implantation dose of one or more second ion implantation regions in the anti-JFET region are arranged such that the size and position of the implantation peak of the second ion implantation region are both between the size and position of the shallowest and deepest implantation peaks in the channel region. The present invention can simultaneously meet the requirements of threshold voltage and reducing the short-channel effect of the device, and the anti-JFET region can not only meet the requirement of reducing the specific on-resistance of the device, but also prevent the increase of the electric field strength on the anti-JFET surface, thereby increasing the reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a planar SiC MOSFET device. Background Art

[0002] Compared with Si, SiC has very superior material properties, which are mainly manifested in that its bandgap width is 3.2 electron volts (eV), nearly three times higher than that of silicon which is 1.12. Its critical breakdown field strength is 10 times that of silicon. If the same breakdown voltage is to be achieved, the drift region length of SiC can be made 1 / 10 of that of silicon, and its doping concentration can also be increased by dozens of times. At the same time, due to the high bandgap width and low intrinsic carrier concentration, even at a junction temperature of 250 degrees or even 300 degrees, the number of intrinsic carriers in SiC devices is still lower than that of Si devices at room temperature (25 degrees). The high-temperature leakage current of SiC devices is greatly reduced. The main factor limiting its operating temperature is the package rather than the device itself.

[0003] Based on this, SiC MOSFETs have been increasingly widely used and have great market prospects.

[0004] As Figure 1 shown, it is a schematic cross-sectional structure diagram of an existing planar SiC MOSFET device; taking an N-type SiC MOSFET as an example for introduction, the existing planar SiC MOSFET device includes:

[0005] An N-type heavily doped SiC substrate 101, and the resistivity of the SiC substrate 101 is usually about 20 mΩ*cm. The substrate resistivity of the corresponding Si device can be made below 1 mΩ*cm. This is because too high a substrate doping concentration will increase the defects of the device. Therefore, the substrate resistance of the SiC substrate 101 is much higher than that of the Si device. In order to reduce the substrate resistance, it is usually desirable to make the thickness of the SiC substrate 101 as thin as possible. In addition, the thinner the substrate thickness, the lower the thermal resistance of the device;

[0006] An N-type doped buffer layer 102 formed of SiC material is formed on the SiC substrate 101. The doping concentration of the buffer layer 102 is very high, around 1e18 / cm 3 ; the buffer layer 102 is formed by epitaxial growth, so the defect density of the buffer layer 102 is better than that of the substrate. The thickness of the buffer layer 102 is usually around 1 μm.

[0007] An N-type doped SiC epitaxial layer 103 is formed on the surface of the Buffer layer 102. The doping concentration of the SiC epitaxial layer 103 determines the breakdown voltage of the device. The higher the breakdown voltage of the device, the thicker the SiC epitaxial layer 103 and the lower the doping concentration of the SiC epitaxial layer 103. For the current 1200V SiC MOSFET, the thickness of the SiC epitaxial layer 103 is usually between 8μm and 13μm, and the doping concentration of the SiC epitaxial layer 103 is usually between 5e15 / cm 3 ~2e16 / cm 3 . The SiC epitaxial layer 103 is usually a single layer at present, or it can also be a double epitaxy. For double epitaxy, the doping concentration near the surface is high, which reduces the JFET effect of the MOSFET.

[0008] A P-type doped channel region 104 is formed in the SiC epitaxial layer 103. The design of the channel region 104 is a difficulty of the SiC MOSFET. This is because the carrier mobility of the channel region 104 of the SiC MOSFET is very low, usually less than 1 / 10 of that of silicon devices; therefore, we hope to make the channel length Lc as short as possible. However, in order to ensure a certain threshold voltage, the doping concentration of the channel region 104, especially the surface doping concentration, cannot be too high.

[0009] In addition, the doping concentration of the drift region of the SiC MOSFET has also increased significantly. The drift region is composed of the SiC epitaxial layer 103 outside the channel region 104, which requires that both the doping concentration of the channel region 104 and the channel length Lc need to be increased, otherwise there will be a very serious short-channel effect.

[0010] The region between adjacent channel regions 104 usually exhibits a JFET effect, and the distance Wj between adjacent channel regions 104 is also a challenge. There will be a depletion between the channel region 104 and the N-type drift region, that is, the JFET effect, which will reduce the conductive region. If this distance Wj is too small, the JFET effect is too severe, and the specific on-resistance of the device will increase sharply. If the distance Wj is too large, the pitch of the device increases, the cell density decreases, and the specific on-resistance of the device also increases. In order to still have a relatively low specific on-resistance when the distance between channels is small, an anti-JFET implant is usually added. The anti-JFET implant forms an anti-JFET implant region between adjacent channel regions 104. However, this JFET implant region will increase the electric field strength of the gate oxide 107. For SiC MOSFETs, since the critical breakdown field strength of SiC is as high as over 3 MV / cm; the material of the gate oxide 107 is usually SiO2. In addition, due to the difference in the dielectric constants of the SiC material and SiO2 at the interface between the SiC epitaxial layer 103 and the gate oxide 107, the electric field strength in the SiO2 material of the gate oxide 107 will increase by more than 2 times. This easily reaches or exceeds the critical breakdown voltage of SiO2, resulting in device damage or degradation of long-term operating performance. Therefore, how to design the channel region 104 and the doping concentration of the anti-JFET region between adjacent channel regions 104 is a challenge and also a problem to be solved by the present invention. In summary, the present invention mainly solves how to design a reasonable doping concentration of the channel region 104 to reduce the short-channel effect of the device; and how to design the doping concentration of the anti-JFET region so that when the on-resistance of the device is relatively low, the surface breakdown field strength can still be relatively low.

[0011] An N-type heavily doped source region 106 and a P-type heavily doped body contact region 105 are formed in the surface region of the selected region of the channel region 104. The doping concentration of the body contact region 105 is high, which can reduce the base resistance of the parasitic triode of the device and prevent the device from experiencing snapback.

[0012] The source metal 110 composed of the front metal layer is connected to the bottom body contact region 105 and the source region 106 through a source region via hole. The source region via hole and the bottom body contact region 105 and the source region 106 achieve ohmic contact, and the channel region 104 is connected to the source region via hole and the source metal 110 through the body contact hole 105.

[0013] The gate oxide 107 is usually SiO2. The driving voltage of SiC MOSFETs usually needs to exceed 18V, and even reach 20V. For such a high driving voltage requirement, the gate oxide thickness is usually relatively thick. Currently, for SiC planar MOSFETs, the thickness of the gate oxide is usually That is, 50 nm.

[0014] The gate conductive material layer 108 is formed on the surface of the gate oxide 107, and the gate structure is formed by the superposition of the gate oxide 107 and the gate conductive material layer 108. The surface of the channel region 104 covered by the gate structure forms a conductive channel when the device is turned on. The gate conductive material layer 108 generally uses an N-type heavily doped polysilicon gate.

[0015] The interlayer film 109 realizes the isolation between the source metal 10 and the gate conductive material layer 108. The interlayer film 109 is also generally SiO2, and the thickness is generally between 0.4 μm and 2.0 μm. Summary of the Invention

[0016] The technical problem to be solved by the present invention is to provide a planar SiC MOSFET device, in which the doping of the channel region can not only meet the requirements of the threshold voltage, but also meet the requirements of reducing the short-channel effect of the device. At the same time, the anti-JFET region can not only meet the requirements of reducing the specific on-resistance of the device, but also prevent the increase of the electric field strength on the anti-JFET surface, thereby increasing the reliability of the device.

[0017] To solve the above technical problems, the planar SiC MOSFET device provided by the present invention includes:

[0018] A channel region formed in a selected region of a first-conductivity-type doped SiC epitaxial layer, and the surface of the channel region covered by the gate structure is used to form a conductive channel; the SiC epitaxial layer outside the channel region forms a drift region.

[0019] An anti-JFET region is formed on the surface of the drift region between two adjacent channel regions.

[0020] The gate structure also extends to the surface of the anti-JFET region.

[0021] The gate structure is formed by the superposition of a gate dielectric layer and a gate conductive material layer.

[0022] The channel region is formed by the superposition of two or more first ion implantation regions doped with a second conductivity type with different implantation peak positions.

[0023] The anti-JFET region is formed by the superposition of one or more second ion implantation regions doped with a first conductivity type with different implantation peak positions.

[0024] Each of the first ion implantation regions in the channel region is arranged as follows:

[0025] The deeper the implantation peak position, the larger the implantation peak; the shallower the implantation peak position, the smaller the implantation peak.

[0026] The threshold voltage of the planar SiC MOSFET device is adjusted by the first ion implantation region with the shallowest peak implantation position, and the short-channel effect is reduced by each of the first ion implantation regions below the second shallowest peak implantation position.

[0027] The peak implantation positions and implantation doses of the second ion implantation regions in the anti-JFET region are set as follows:

[0028] The peak implantation position of each second ion implantation region is deeper than the shallowest peak implantation position in the channel region to reduce the electric field strength at the interface between the gate dielectric layer and the SiC epitaxial layer.

[0029] The peak implantation position of each second ion implantation region is shallower than the deepest peak implantation position in the channel region to ensure the breakdown voltage of the device.

[0030] The peak implantation of each second ion implantation region is greater than the peak implantation of the first ion implantation region with the shallowest peak implantation position in the channel region, and the peak implantation of each second ion implantation region is less than the peak implantation of the first ion implantation region with the deepest peak implantation position in the channel region, so as to reduce the JFET effect and thus reduce the specific on-resistance of the device.

[0031] A further improvement is that the channel region is formed by superimposing two first ion implantation regions doped with the second conductivity type and having different peak implantation positions.

[0032] A further improvement is that the anti-JFET region is composed of a second ion implantation region doped with the first conductivity type.

[0033] A further improvement is that the anti-JFET region is formed by superimposing two second ion implantation regions doped with the first conductivity type and having different peak implantation positions, and the peak implantations of the two second ion implantation regions are the same or different.

[0034] A further improvement is that the channel region is formed by superimposing three first ion implantation regions doped with the second conductivity type and having different peak implantation positions.

[0035] A further improvement is that the anti-JFET region is composed of a second ion implantation region doped with the first conductivity type.

[0036] A further improvement is that the peak implantation position of the second ion implantation region in the anti-JFET region is located between the shallowest peak implantation position and the second shallowest peak implantation position of the channel region; or, the peak implantation position of the second ion implantation region in the anti-JFET region is located between the second shallowest peak implantation position and the deepest peak implantation position of the channel region.

[0037] A further improvement is that a source region heavily doped with a first conductivity type is also formed in the surface region of a selected region of the channel region, and the gate structure also extends onto the surface of the source region.

[0038] A further improvement is that a body contact region heavily doped with a second conductivity type is also formed in the surface region of a selected region of the channel region.

[0039] A further improvement is that the surfaces of the body contact region and the source region are connected to a source electrode composed of a front metal layer through source contact holes passing through an interlayer film.

[0040] A further improvement is that the planar SiC MOSFET device includes a plurality of device units;

[0041] Two adjacent device units form a primitive cell. In the primitive cell, the two device units share the anti-JFET region, the channel regions of the two device units are symmetrically arranged on both sides of the anti-JFET region, and the gate structures of the two device units are connected above the surface of the anti-JFET region to form an integral structure.

[0042] A further improvement is that the planar SiC MOSFET device includes a plurality of device units;

[0043] Two adjacent device units form a primitive cell. In the primitive cell, the two device units share the anti-JFET region, the channel regions of the two device units are symmetrically arranged on both sides of the anti-JFET region, and the gate structures of the two device units have a gap above the surface of the anti-JFET region to reduce the input capacitance.

[0044] A further improvement is that the planar SiC MOSFET device includes a plurality of device units, and one device unit forms a primitive cell;

[0045] Only one gate structure is provided at the top of each channel region and a conductive channel is formed;

[0046] The second side of the gate structure of each device unit extends from the second side of the channel region to the surface of the adjacent anti-JFET region and has a gap with the first side of the adjacent channel region;

[0047] The source region and the body contact region are formed between the first side of the gate structure of each device unit and the first side of the channel region.

[0048] A further improvement is that the SiC epitaxial layer is formed on the SiC substrate and a buffer layer doped with a first conductivity type is provided between the SiC epitaxial layer and the SiC substrate.

[0049] A further improvement is that the planar SiC MOSFET device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type; or, the planar SiC MOSFET device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.

[0050] A further improvement is that the P-type doping impurity includes aluminum and the N-type doping impurity includes nitrogen.

[0051] In the present invention, both the channel region and the anti-JFET region are composed of ion implantation regions. The present invention makes special settings for the ion implantation regions of the channel region and the anti-JFET region, mainly as follows:

[0052] The ion implantation region of the channel region is divided into multiple first ion implantation regions stacked on top of each other, so that the magnitude and position of the implantation peak of each first ion implantation region can be adjusted separately. In the present invention, the magnitude and position of the implantation peak of each first ion implantation region are set respectively according to the requirements of meeting the threshold voltage of the device and reducing the short-channel effect. Finally, the doping of the channel region can meet both the requirements of the threshold voltage and the requirements of reducing the short-channel effect of the device.

[0053] The magnitude and position of the implantation peak of the second ion implantation region of the anti-JFET region are set according to the magnitude and position of the implantation peak of each first ion implantation region of the channel region. Under the condition that the implantation peak position of the second ion implantation region of the anti-JFET region is located at the bottom of the implantation peak position of the shallowest first ion implantation region of the channel region, the electric field strength of the surface region of the anti-JFET region can be reduced, that is, the electric field strength at the interface between the gate dielectric layer and the SiC epitaxial layer can be reduced, thereby improving the reliability of the device; under the condition that the implantation peak position of the second ion implantation region of the anti-JFET region is located above the implantation peak position of the deepest first ion implantation region of the channel region, the breakdown voltage of the device can be guaranteed; the magnitude of the implantation peak of the second ion implantation region of the anti-JFET region and the setting of the implantation peak position can meet the requirements of the anti-JFET effect, reducing the specific on-resistance of the device.

[0054] In addition, in the field of semiconductor manufacturing, the implantation peak corresponding to the ion implantation process refers to the maximum doping concentration in the implantation region after ion implantation. The magnitude of the implantation peak is the maximum doping concentration itself in the implantation region, corresponding to the implantation dose of ion implantation; the position of the implantation peak is also the depth position corresponding to the maximum doping concentration in the implantation region, also simply referred to as the implantation peak position, corresponding to the implantation energy of ion implantation. Description of the Drawings

[0055] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:

[0056] Figure 1 is a schematic cross-sectional structure diagram of an existing planar SiC MOSFET device;

[0057] Figure 2 is a schematic cross-sectional structure diagram of the planar SiC MOSFET device according to the first embodiment of the present invention;

[0058] Figure 3A is the first doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention;

[0059] Figure 3B is at Figure 3A When the injection peak position of the anti-JFET region is shallower than the required value based on, it is the doping concentration distribution curve;

[0060] Figure 3C is at Figure 3A When the injection peak position of the anti-JFET region is deeper than the required value based on, it is the doping concentration distribution curve;

[0061] Figure 4 is the second doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention;

[0062] Figure 5 is the third doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention;

[0063] Figure 6 is the fourth doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention;

[0064] Figure 7 is a schematic cross-sectional structure diagram of the planar SiC MOSFET device according to the second embodiment of the present invention;

[0065] Figure 8 is a schematic cross-sectional structure diagram of the planar SiC MOSFET device according to the third embodiment of the present invention. Detailed implementation manners

[0066] The planar SiC MOSFET device according to the first embodiment of the present invention:

[0067] As Figure 2 shown, it is a schematic cross-sectional structure diagram of the planar SiC MOSFET device according to the first embodiment of the present invention; the planar SiC MOSFET device according to the first embodiment of the present invention includes:

[0068] The channel region 4 formed in the selected region of the SiC epitaxial layer 3 doped with the first conductivity type, the surface of the channel region 4 covered by the gate structure is used to form a conductive channel; the SiC epitaxial layer 3 outside the channel region 4 constitutes a drift region.

[0069] In the first embodiment of the present invention, the SiC epitaxial layer 3 is formed on the SiC substrate 1 and there is a buffer layer 2 doped with the first conductivity type between the SiC epitaxial layer 3 and the SiC substrate 1.

[0070] An anti-JFET region 3a is formed on the surface of the drift region between two adjacent channel regions 4. The anti-JFET region 3a is realized by increasing the doping of the first conductivity type in the SiC epitaxial layer 3 between the adjacent channel regions 4. Figure 2 In, the anti-JFET region is represented by a dotted line box 3a alone.

[0071] The gate structure also extends to the surface of the anti-JFET region 3a.

[0072] The gate structure is formed by stacking a gate dielectric layer 7 and a gate conductive material layer 8. The gate dielectric layer 7 is usually composed of a gate oxide such as silicon dioxide, and the gate conductive material layer 8 is usually composed of a polysilicon gate.

[0073] The channel region 4 is formed by stacking two or more first ion implantation regions doped with the second conductivity type and having different implantation peak positions.

[0074] The anti-JFET region 3a is formed by stacking one or more second ion implantation regions doped with the first conductivity type and having different implantation peak positions.

[0075] Each of the first ion implantation regions in the channel region 4 is arranged as follows:

[0076] The deeper the implantation peak position, the larger the implantation peak; the shallower the implantation peak position, the smaller the implantation peak.

[0077] The threshold voltage of the planar SiC MOSFET device is adjusted by the first ion implantation region with the shallowest implantation peak position, and the short-channel effect is reduced by each of the first ion implantation regions below the second shallowest implantation peak position.

[0078] The implantation peak position and implantation dose of each of the second ion implantation regions in the anti-JFET region 3a are arranged as follows:

[0079] The implantation peak position of each of the second ion implantation regions is deeper than the shallowest implantation peak position in the channel region 4 to reduce the electric field strength at the interface between the gate dielectric layer 7 and the SiC epitaxial layer 3.

[0080] The implantation peak position of each of the second ion implantation regions is shallower than the deepest implantation peak position in the channel region 4, so as to ensure the breakdown voltage of the device.

[0081] The implantation peak of each of the second ion implantation regions is greater than the implantation peak of the first ion implantation region with the shallowest implantation peak position in the channel region 4, and the implantation peak of each of the second ion implantation regions is less than the implantation peak of the first ion implantation region with the deepest implantation peak position in the channel region 4, so as to reduce the JFET effect and thus reduce the specific on-resistance of the device.

[0082] In some embodiments, the channel region 4 is formed by superimposing two first ion implantation regions doped with the second conductivity type and having different implantation peak positions. The anti-JFET region 3a is composed of a second ion implantation region doped with the first conductivity type. For this case, please refer to Figure 3A shown Figure 3A which is the first doping concentration distribution curve of the channel region and the anti-JFET region 3a of the planar SiC MOSFET device according to the first embodiment of the present invention; Figure 3A In it, curve 201 is Figure 2 the doping concentration distribution at the solid line AA in Figure 2 The longitudinal range of the solid line AA extends downward from the top surface of the channel region 4 to the SiC epitaxial layer 3 at the bottom of the channel region 4. Therefore, the doping distribution of the channel region 4 is included in curve 201; curve 202 is Figure 3A the doping concentration distribution at the dashed line BB in Figure 3A The longitudinal range of the dashed line BB extends downward from the top surface of the SiC epitaxial layer 3 between the channel regions 4. Therefore, the doping concentration distribution of the anti-JFET region 3a is included in curve 202.

[0083] The size of the shallower implantation peak in curve 201 is lower, which can realize the adjustment of the threshold voltage of the device; the size of the deeper implantation peak in curve 201 is larger, which can reduce the short-channel effect.

[0084] The position of the injection peak of curve 202 is located between the positions of the two injection peaks of curve 201. The advantage of this is that while obtaining a relatively low specific on-resistance, the device still has a high breakdown voltage, and it can also ensure that the maximum electric field strength at the interface between SiC and SiO2, that is, at the interface between the SiC epitaxial layer 3 and the gate dielectric layer 7, is reduced to an acceptable range, such as less than 2.0 MV / cm, or even below 1.5 MV / cm, when the device is approaching breakdown.

[0085] On the contrary, if the position of the injection peak of curve 202 is too shallow or too deep, corresponding problems will occur. Now, combined with Figure 3B and Figure 3C the following explanations are made:

[0086] As Figure 3B shown, it is the doping concentration distribution curve when the injection peak position in the anti-JFET region is shallower than the required value based on Figure 3A ; Figure 3B Curve 201a in Figure 3A is the same as curve 201 in Figure 2 ; Curve 202a is the doping concentration distribution at the dotted line BB in

[0087] As can be seen, the position of the injection peak of curve 202a is shallower than the position of the shallower injection peak in curve 201a; The disadvantage of this situation is that the injection peak of curve 202a is closer to the surface, that is, the SiC and SiO2 interface. After the doping concentration at the SiC and SiO2 interface increases, the maximum electric field strength will increase, which will affect the reliability of the device. Figure 3C shown, it is the doping concentration distribution curve when the injection peak position in the anti-JFET region is deeper than the required value based on Figure 3A ; Figure 3B Curve 201b in Figure 3A is the same as curve 201 in Figure 2 ; Curve 202b is the doping concentration distribution at the dotted line BB in

[0088] As can be seen, the position of the injection peak of curve 202b is deeper than the position of the deeper injection peak in curve 201b; The disadvantage of this situation is that the injection peak of curve 202b is farther from the surface, resulting in an increase in the doping concentration inside the drift region, which will affect the breakdown voltage of the device and the breakdown voltage will decrease. Figure 4 shown, it is the second doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention;Figure 4 The abscissa and ordinate sum of Figure 3A is the same as that of Figure 2 The doping concentration distribution along the solid line AA of Figure 2 is the same as that of curve 201c along the dotted line BB in Figure 3A Curve 201c is the same as curve 201 of . Curve 202c has two injection peaks. The positions of the two injection peaks of curve 202c are both between the positions of the two injection peaks of curve 201c, and the magnitudes of the two injection peaks of curve 202c are also between the magnitudes of the two injection peaks of curve 201c.

[0089] In some other embodiments, the channel region 4 is formed by superimposing three first ion implantation regions doped with a second conductivity type and having different injection peak positions. The anti-JFET region 3a is composed of a second ion implantation region doped with a first conductivity type. The injection peak position of the second ion implantation region of the anti-JFET region 3a is between the shallowest injection peak position and the second shallowest injection peak position of the channel region 4; alternatively, the injection peak position of the second ion implantation region of the anti-JFET region 3a is between the second shallowest injection peak position and the deepest injection peak position of the channel region 4.

[0090] As Figure 5 shown, it is the third doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention; Figure 5 The abscissa and ordinate sum of Figure 3A is the same as that of Figure 2 The doping concentration distribution along the solid line AA of Figure 2 is the same as that of curve 202d along the dotted line BB in . It can be seen that curve 201d has three injection peaks, and curve 202d has one injection peak. The position of the injection peak of curve 202d is between the positions of the two shallower injection peaks of curve 201d.

[0091] As Figure 6 shown, it is the fourth doping concentration distribution curve of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention; Figure 6 The abscissa and ordinate sum of Figure 3A is the same as that of Figure 2 The doping concentration distribution along the solid line AA of Figure 2The doping concentration distribution at the dashed line BB in []. It can be seen that the curve 201e has three injection peaks, while the curve 202e has one injection peak, and the position of the injection peak of the curve 202e is located between the positions of the two deeper injection peaks of the curve 201d.

[0092] Although only the fourth doping concentration distribution curve is specifically disclosed above, it is impossible to list all other doping concentration distributions in the specification. However, in fact, in the first embodiment of the present invention, the doping concentrations of the channel region 4 and the anti-JFET region 3a only need to ensure that the following conditions are met:

[0093] 1. The channel region 4 includes at least two injection peak concentrations, and the anti-JFET region 3a includes at least one injection peak concentration.

[0094] 2. The first injection peak concentration of the anti-JFET region 3a can be closer to the SiC body than the first injection peak concentration of the channel region 4.

[0095] 3. The last injection peak concentration of the anti-JFET region 3a is closer to the surface of the SiC than the last injection peak concentration of the channel region 4.

[0096] For more ion implantation conditions of the channel region 4 and the anti-JFET region 3a, a suitable injection peak concentration distribution can be obtained according to the above description and actual needs.

[0097] In the first embodiment of the present invention, a source region 6 doped with a heavily doped first conductive type is also formed in the surface region of the selected region of the channel region 4, and the gate structure also extends to the surface of the source region 6.

[0098] A body contact region 5 doped with a heavily doped second conductive type is also formed in the surface region of the selected region of the channel region 4.

[0099] The surfaces of the body contact region 5 and the source region 6 are connected to a source electrode 10 composed of a front metal layer through a source contact hole passing through the interlayer film 9.

[0100] In the first embodiment of the present invention, the planar SiC MOSFET device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. In other embodiments, it can also be: the planar SiC MOSFET device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0101] The P-type doping impurity includes aluminum (Alμminμm), and the N-type doping impurity includes nitrogen (Nitrogen).

[0102] Taking the N-type device as an example:

[0103] The channel region 4 and the anti-JFET region 3a are both formed by ion implantation. Usually, aluminum is implanted for the ion implantation of the channel region 4, and nitrogen is usually implanted for the ion implantation of the anti-JFET region 3a. To reduce the damage of ion implantation to the SiC device, the temperature of ion implantation can be increased, such as up to 500 degrees.

[0104] In some typical embodiments, the following specific parameters can be adopted:

[0105] The first one is: the length of the channel region 4 is 0.5 μm, and the width of the JFET region 3a is 1.5 μm; the implantation of the channel region 4 includes 2 times, and the implantation condition is 0-degree angle implantation. The first time is the implantation of aluminum with an implantation energy of 120 keV and an implantation dose of 6.0e12 cm -2 of aluminum, and the second time is the implantation of aluminum with an implantation energy of 600 keV and an implantation dose of 8.0e13 cm -2 of aluminum implantation. The implantation of the anti-JFET region 3a includes 1 time. The anti-JFET region 3a is implanted at a 0-degree angle. The implantation of the anti-JFET region 3a is the implantation of nitrogen with an implantation energy of 180 keV and an implantation dose of 2.0e12 cm -2 of nitrogen implantation, and the dose can also be increased to 3.0e12 cm -2 . This situation conforms to Figure 3A the first doping concentration distribution curve shown.

[0106] The second one is: the length of the channel region 4 is 0.5 μm, and the width of the JFET region 3a is 1.5 μm; the implantation of the channel region 4 includes 2 times, and the implantation condition is 0-degree angle implantation. The first time is the implantation of aluminum with an implantation energy of 120 keV and an implantation dose of 6.0e12 cm -2 of aluminum, and the second time is the implantation of aluminum with an implantation energy of 600 keV and an implantation dose of 8.0e13 cm -2 of aluminum implantation. The implantation of the anti-JFET region 3a includes 2 times, which is 0-degree angle implantation. The first time is the implantation of nitrogen with an implantation energy of 180 keV and an implantation dose of 2.0e12 cm -2 of nitrogen implantation, and the second time is the implantation of nitrogen with an implantation energy of 300 keV and an implantation dose of 2.0e12 cm -2 of nitrogen implantation. This situation conforms to Figure 4 the second doping concentration distribution curve shown.

[0107] The planar SiC MOSFET device includes a plurality of device units;

[0108] Two adjacent device units form a primitive cell,Figure 2 The structure of the primitive cell is shown. In the primitive cell, two of the device units share the anti-JFET region 3a. The channel regions 4 of the two device units are symmetrically arranged on both sides of the anti-JFET region 3a. The gate structures of the two device units are connected above the surface of the anti-JFET region 3a to form an integral structure.

[0109] In the first embodiment of the present invention, both the channel region 4 and the anti-JFET region 3a are composed of ion implantation regions. The present invention makes special settings for the ion implantation regions of the channel region 4 and the anti-JFET region 3a, mainly:

[0110] The ion implantation region of the channel region 4 is divided into multiple first ion implantation regions stacked on top of each other, so that the magnitude and position of the implantation peak of each first ion implantation region can be adjusted respectively. In the first embodiment of the present invention, the magnitude and position of the implantation peak of each first ion implantation region are set according to the requirements of meeting the threshold voltage of the device and reducing the short-channel effect. Finally, the doping of the channel region 4 can meet both the requirements of the threshold voltage and the requirements of reducing the short-channel effect of the device.

[0111] The magnitude and position of the implantation peak of the second ion implantation region of the anti-JFET region 3a are set according to the magnitude and position of the implantation peak of each first ion implantation region of the channel region 4. Under the condition that the implantation peak position of the second ion implantation region of the anti-JFET region 3a is located at the bottom of the implantation peak position of the shallowest first ion implantation region of the channel region 4, the electric field strength of the surface region of the anti-JFET region 3a can be reduced, that is, the electric field strength at the interface between the gate dielectric layer 7 and the SiC epitaxial layer 3 can be reduced, thereby improving the reliability of the device; under the condition that the implantation peak position of the second ion implantation region of the anti-JFET region 3a is located above the implantation peak position of the deepest first ion implantation region of the channel region 4, the breakdown voltage of the device can be guaranteed; the magnitude of the implantation peak of the second ion implantation region of the anti-JFET region 3a combined with the setting of the implantation peak position can meet the requirements of the anti-JFET effect, reducing the specific on-resistance of the device.

[0112] In addition, in the field of semiconductor manufacturing, the implantation peak corresponding to the ion implantation process refers to the maximum doping concentration in the implantation region after ion implantation. The magnitude of the implantation peak is the maximum doping concentration itself in the implantation region, corresponding to the implantation dose of ion implantation; the position of the implantation peak, that is, the depth position corresponding to the maximum doping concentration in the implantation region, is also simply referred to as the implantation peak position, corresponding to the implantation energy of ion implantation.

[0113] The planar SiC MOSFET device of the second embodiment of the present invention:

[0114] AsFigure 7 As shown, it is a schematic cross-sectional structure diagram of the planar SiC MOSFET device according to the second embodiment of the present invention; the difference between the planar SiC MOSFET device according to the second embodiment of the present invention and the planar SiC MOSFET device according to the first embodiment of the present invention is that the planar SiC MOSFET device according to the second embodiment of the present invention has the following distinguishing features:

[0115] The planar SiC MOSFET device includes a plurality of device units;

[0116] Two adjacent device units form a primitive cell, Figure 7 The structure of one primitive cell is shown in. In the primitive cell, the two device units share the anti-JFET region 3a, the channel regions 4 of the two device units are symmetrically arranged on both sides of the anti-JFET region 3a, and the gate structures of the two device units have a gap above the surface of the anti-JFET region 3a to reduce the input capacitance. Figure 7 In, the gate conductive material layers of two adjacent gate structures are separately marked with 8a and 8b. And Figure 2 Compared with, it can be seen that Figure 2 in the gate structure described in, the region between the channel regions 4 will be completely covered, that is, the overlapping region between the gate and the drain is increased, which will increase the gate-drain capacitance Cgd; in the corresponding device of the second embodiment of the present invention Figure 7 the covered area of the region between the gate structure and the channel region 4 is small, so Cgd will be reduced.

[0117] The planar SiC MOSFET device according to the third embodiment of the present invention:

[0118] As shown in Figure 8 it is a schematic cross-sectional structure diagram of the planar SiC MOSFET device according to the third embodiment of the present invention; the difference between the planar SiC MOSFET device according to the third embodiment of the present invention and the planar SiC MOSFET device according to the first embodiment of the present invention is that the planar SiC MOSFET device according to the third embodiment of the present invention has the following distinguishing features:

[0119] The planar SiC MOSFET device includes a plurality of device units, and one device unit forms a primitive cell; Figure 8 Two device units, that is, two primitive cells, are shown in.

[0120] Only one gate structure is provided at the top of each channel region 4 and a conductive channel is formed. Figure 8 The gate conductive material layer 8 of the gate structure is shown in.

[0121] The second side of the gate structure of each of the device units extends from the second side of the channel region 4 to the surface of the adjacent anti-JFET region 3a and is spaced from the first side of the adjacent channel region 4.

[0122] A source region 6 and a body contact region 5 are formed between the first side of the gate structure of each of the device units and the first side of the channel region 4.

[0123] Figure 2 In [description], since only one primitive cell is shown, in fact, each primitive cell is arranged repeatedly. Therefore, gate structures are formed on both sides of the channel region 4, and the middle region of the channel region 4 is the source region 6 and the body contact region 5. Since a channel is formed on the surface of the channel region 4 covered by the gate structure, channels are formed on both sides of the channel region 4, and there are two channels in total. Figure 2 Two channels are shown in the primitive cell in [description], and each of these two channels is composed of a channel in one of the channel regions 4.

[0124] and Figure 2 The structure shown in [description] is different. Figure 8 In one of the channel regions 4 in [description], only one gate structure is formed on one side. Since the conductive channel is only formed in the covered area of the gate structure, only one conductive channel is formed in the channel region 4. Figure 8 There is only one conductive channel in the primitive cell in [description].

[0125] Therefore, Figure 8 The structure shown in [description] can increase the primitive cell density, but it will reduce the channel density. The channel resistance of the device will increase, but the capacitance of the device will decrease due to the reduction of the channel density.

[0126] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A planar SiC MOSFET device, characterized in that, Comprising: A channel region formed in a selected region of a first-conductivity-type doped SiC epitaxial layer, and a surface of the channel region covered by a gate structure is used to form a conductive channel; The SiC epitaxial layer outside the channel region forms a drift region; An anti-JFET region is formed on a surface of the drift region between two adjacent channel regions; The gate structure also extends onto a surface of the anti-JFET region; The gate structure is formed by stacking a gate dielectric layer and a gate conductive material layer; The channel region is formed by stacking two or more first ion implantation regions doped with a second conductivity type and having different implantation peak positions; The anti-JFET region is formed by stacking one or more second ion implantation regions doped with a first conductivity type and having different implantation peak positions; Each of the first ion implantation regions in the channel region is arranged such that: The deeper the implantation peak position, the larger the implantation peak; the shallower the implantation peak position, the smaller the implantation peak; The threshold voltage of the planar SiC MOSFET device is adjusted by the first ion implantation region with the shallowest implantation peak position, and the short-channel effect is reduced by each of the first ion implantation regions below the second shallowest implantation peak position; The implantation peak position and implantation dose of each of the second ion implantation regions in the anti-JFET region are arranged such that: The implantation peak position of each of the second ion implantation regions is deeper than the shallowest implantation peak position in the channel region to reduce the electric field strength at an interface between the gate dielectric layer and the SiC epitaxial layer; The implantation peak position of each of the second ion implantation regions is shallower than the deepest implantation peak position in the channel region to ensure the breakdown voltage of the device; The implantation peak of each of the second ion implantation regions is greater than the implantation peak of the first ion implantation region with the shallowest implantation peak position in the channel region, and the implantation peak of each of the second ion implantation regions is less than the implantation peak of the first ion implantation region with the deepest implantation peak position in the channel region, so as to reduce the JFET effect and thus reduce the specific on-resistance of the device.

2. The planar SiC MOSFET device according to claim 1, characterized in that: The channel region is formed by stacking two first ion implantation regions doped with a second conductivity type and having different implantation peak positions.

3. The planar SiC MOSFET device according to claim 2, characterized in that: The anti-JFET region is composed of a second ion implantation region doped with a first conductivity type.

4. The planar SiC MOSFET device according to claim 2, characterized in that: The anti-JFET region is formed by stacking two second ion implantation regions doped with a first conductivity type and having different implantation peak positions, and the implantation peak sizes of the two second ion implantation regions are the same or different.

5. The planar SiC MOSFET device according to claim 1, characterized in that: The channel region is formed by stacking three first ion implantation regions doped with a second conductivity type and having different implantation peak positions.

6. The planar SiC MOSFET device according to claim 5, characterized in that: The anti-JFET region is composed of a second ion implantation region doped with a first conductivity type.

7. The planar SiC MOSFET device according to claim 6, characterized in that: The implantation peak position of the second ion implantation region in the anti-JFET region is located between the shallowest implantation peak position and the second shallowest implantation peak position of the channel region; or, the implantation peak position of the second ion implantation region in the anti-JFET region is located between the second shallowest implantation peak position and the deepest implantation peak position of the channel region.

8. The planar SiC MOSFET device according to claim 1, characterized in that: A source region heavily doped with a first conductivity type is further formed in a surface region of a selected region of the channel region, and the gate structure also extends onto a surface of the source region.

9. The planar SiC MOSFET device according to claim 8, characterized in that: A body contact region doped heavily with a second conductivity type is also formed in the surface region of a selected region of the channel region.

10. The planar SiC MOSFET device according to claim 9, characterized in that: The surfaces of the body contact region and the source region are connected to a source electrode composed of a front metal layer through source contact holes penetrating an interlayer film.

11. The planar SiC MOSFET device according to claim 10, characterized in that: The planar SiC MOSFET device includes a plurality of device cells; Two adjacent device cells form a primitive cell. In the primitive cell, the two device cells share the anti-JFET region, the channel regions of the two device cells are symmetrically arranged on both sides of the anti-JFET region, and the gate structures of the two device cells are connected above the surface of the anti-JFET region to form an integral structure.

12. The planar SiC MOSFET device according to claim 10, wherein: The planar SiC MOSFET device includes a plurality of device cells; Two adjacent device cells form a primitive cell. In the primitive cell, the two device cells share the anti-JFET region, the channel regions of the two device cells are symmetrically arranged on both sides of the anti-JFET region, and the gate structures of the two device cells have a gap above the surface of the anti-JFET region to reduce the input capacitance.

13. The planar SiC MOSFET device according to claim 10, wherein: The planar SiC MOSFET device includes a plurality of device cells, and one device cell forms a primitive cell; Only one gate structure is provided at the top of each channel region and a conductive channel is formed; The second side of the gate structure of each device cell extends from the second side of the channel region to the surface of an adjacent anti-JFET region and has a gap with the first side of the adjacent channel region; A source region and a body contact region are formed between the first side of the gate structure of each device cell and the first side of the channel region.

14. The planar SiC MOSFET device according to claim 1, wherein: The SiC epitaxial layer is formed on the SiC substrate, and a buffer layer doped with a first conductivity type is provided between the SiC epitaxial layer and the SiC substrate.

15. The planar SiC MOSFET device according to any one of claims 1-14, wherein: The planar SiC MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; alternatively, the planar SiC MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

16. The planar SiC MOSFET device according to claim 15, wherein: The P-type doping impurity includes aluminum, and the N-type doping impurity includes nitrogen.

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