Methods for fabricating semiconductor memory devices

Abstract

This disclosure provides a method for fabricating a semiconductor memory element. The method includes receiving a substrate having a cell region and a surrounding region; forming a first element line structure on a surface of the cell region; depositing a landing pad on a barrier layer and on the upper surface of the first element line structure; removing an upper corner of the landing pad to form an inclined surface, the inclined surface connecting the upper surface of the landing pad to a sidewall of the landing pad; etching the nitride layer and the spacer nitride layer of the first element line structure from the upper opening to form a concave surface; etching the spacer oxide layer from the concave surface to form an air gap; and depositing a silicon nitride layer to seal the air gap.

Description

[0001] This invention claims priority to U.S. Patent Applications No. 17 / 546,657 and No. 17 / 546,310 (i.e., priority date "December 9, 2021"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a method for fabricating a memory element. More particularly, it relates to a method for fabricating a memory element having a bit-line structure sandwiched between a pair of air gaps. Background Technology

[0003] Semiconductor components are widely used in the electronics industry. Semiconductor components can have relatively small size, multifunctionality, and relatively low manufacturing cost. Semiconductor components include semiconductor memory components for storing logic data, semiconductor logic components for processing logic data (e.g., random access memory (RAM) and read-only memory (ROM)), and hybrid semiconductor components that perform the functions of semiconductor memory components and semiconductor logic components.

[0004] In Dynamic Random Access Memory (DRAM) devices, there is a serious problem related to leakage current. Bonding between silicon oxide in an interlayer isolation layer and silicon near the interface between the semiconductor substrate and the interlayer isolation layer, or between a gate dielectric layer and silicon near the interface between the semiconductor substrate and the gate dielectric layer, results in an interface energy level. This interface energy level causes leakage current to flow from a diffusion layer to the semiconductor substrate. This leakage current degrades the performance characteristics of the DRAM.

[0005] Typically, a semiconductor memory element includes a cell region and a surrounding region. Figures 1 to 6 These are illustrative 3D perspective and cross-sectional views, providing a cell region of a semiconductor memory element 10 with multiple air gaps manufactured according to a conventional method of known technology. For example... Figure 1As shown, the semiconductor memory element 10 includes a bit line structure 101, which includes a bit line tungsten 101a and a bit line nitride 101b. The bit line structure 101 is disposed on a substrate of the semiconductor memory element 10 and protrudes from the substrate. The bit line structure 101 also includes sidewalls SW1 and SW2 and an upwardly inclined upper portion ATP1, wherein the upwardly inclined upper portion ATP1 is connected to the sidewall SW2 of the bit line structure 101. The semiconductor memory element 10 also includes a landing pad 103 disposed on the upwardly inclined upper portion ATP1 and the sidewalls SW1 and SW2 of the bit line structure 101, wherein the landing pad 103 has an inclined surface IS1 corresponding to the upwardly inclined upper portion ATP1 of the bit line structure 101. The bit line structure 101 is sandwiched between a pair of spacers 105a and 105b. After performing an etching step using a chemical etchant (e.g., HF (hydrogen fluoride) vapor), a pair of air gaps AG1 and AG2 are formed within spacers 105b and 105a, respectively (see reference). Figure 2 Interstitial oxide 107 determines the stability of the HF vapor etching process.

[0006] As used in this text, the term "open area" refers to the area on top of a laminated structure formed after slight etching. Please refer to [link / reference]. Figure 2 and Figure 3 A smaller opening region 109 in the interstitial oxide 107 results in a longer HF vapor etching time and an insufficient gap depth H1. The longer HF vapor etching time leads to nitride loss from the interstitials 105a and 105b in the cell region and the bit line nitride 101b, as well as significant nitride loss from the nitride film in the surrounding region.

[0007] Please refer to Figure 1 and Figure 4 A large interstitial oxide opening region 111 requires a longer dry etching time for the tungsten used in the landing pad 103, resulting in a larger etching depth DP1. A significant nitride loss in the nitride film of the cell region and the surrounding region leads to a sealing nitride morphology in both regions.

[0008] Please refer to Figure 1 , Figure 5 and Figure 6A larger height H2 of the interstitial oxide 107 results in a larger opening region in the interstitial oxide 107 and a reduction in HF vapor etching time. However, the larger height H2 of the interstitial oxide 107 also causes multiple air gaps to form at a higher position, which leads to a shorter distance between a capacitor and an air gap, and affects the process window of the capacitor because a dry etching step is required to etch through multiple said air gaps. Therefore, the metal nitride used in the capacitor is deposited in multiple said air gaps, resulting in a leakage current between multiple said bit lines. In addition, a larger air gap depth causes a larger loss of nitride, resulting in a sealed nitride morphology in both the cell region and the surrounding region. Therefore, these problems require an additional patterning process to form separate cells and surrounding regions.

[0009] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0010] One embodiment of this disclosure provides a method for fabricating a semiconductor memory element. The method includes receiving a substrate having a cell region and a surrounding region; forming a first bit line structure on a surface of the cell region, wherein the first bit line structure sequentially includes a bit line contact point, a tungsten layer, and a nitride layer. The bit line contact point is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact point, and the nitride layer is disposed on the tungsten layer. The first bit line structure has an upper surface and two sidewalls, the upper surface being away from the substrate, and the two sidewalls connecting the upper surface to the substrate. The first bit line structure is sandwiched between a pair of spacers. Between, each spacer includes a spacer oxide layer sandwiched between two spacer nitride layers, wherein a barrier layer conformally covers a plurality of said sidewalls adjacent to the first element line structure and a plurality of said spacers in the unit region; a landing pad is deposited on the barrier layer and on the upper surface of the first element line structure; an upper corner of the landing pad is removed to form an inclined surface, the inclined surface connecting an upper surface of the landing pad to a sidewall of the landing pad, wherein an upper opening of the spacer is formed in the inclined surface; hydrogen fluoride vapor is used to generate (NH4)2SiF 6(s) The nitride layer of the first element line structure and the interstitial nitride layer are etched from the upper opening to form a concave surface; hydrogen fluoride vapor is used to control (NH4)2SiF 6(s)The vaporization rate is determined by etching the interstitial oxide layer from the concave surface to form an air gap; and a silicon nitride layer is deposited to seal the air gap.

[0011] Another embodiment of this disclosure provides a method for fabricating a semiconductor memory element. The method includes receiving a silicon substrate having a cell region and a surrounding region; forming a first bit line structure on a surface of the cell region, wherein the first bit line structure sequentially includes a bit line contact point, a tungsten layer, and a nitride layer. The bit line contact point is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact point, and the nitride layer is disposed on the tungsten layer. The first bit line structure includes an upper surface and two sidewalls. The upper surface is located away from the substrate, and the two sidewalls connect the upper surface to the substrate. The first bit line structure is sandwiched between a pair of spacers. Between, each intermezoid includes an intermezoid oxide layer sandwiched between two intermezoid nitride layers, wherein a barrier layer conformally covers a plurality of said sidewalls adjacent to the first element line structure and a plurality of said intermezoids in the unit region; an atomic layer deposition (ALD) is performed to deposit a landing pad on the barrier layer and on the upper surface of the first element line structure; a directional etching is performed to remove an upper corner of the landing pad to form a concave surface having an upper opening of the intermezoid formed in the concave surface; hydrogen fluoride vapor is used to generate (NH4)2SiF 6(s) An anisotropic dry etching process is performed to etch the nitride layer and the interstitial nitride layer of the first element line structure from the opening to form a concave surface; hydrogen fluoride vapor is used to control the (NH4)2SiF 6(s) The vaporization rate is determined by etching the interstitial oxide layer from the concave surface to form an air gap; and a silicon nitride layer is deposited to seal the air gap.

[0012] Another embodiment of this disclosure provides a semiconductor memory device. The semiconductor memory device includes a substrate having a cell region and a surrounding region; a first bit line structure disposed on a surface of the cell region and protruding from the surface of the cell region, wherein the first bit line structure sequentially includes a bit line contact point, a tungsten layer, and a nitride layer. The bit line contact point is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact point, and the nitride layer is disposed on the tungsten layer. The first bit line structure has a sidewall and an upwardly inclined upper portion. The sidewall of the first bit line structure... The upwardly inclined upper portion of the bit line structure is connected to the surface of the cell region, and the upwardly inclined upper portion has a concave surface facing the nitride layer of the first bit line, wherein the first bit line structure is sandwiched between a pair of air gaps; a barrier layer conformally covers a plurality of sidewalls adjacent to the first bit line structure and a plurality of air gaps of the cell region; and a landing pad is disposed on the upwardly inclined upper portion and the plurality of sidewalls of the first bit line structure, wherein the landing pad has an inclined surface corresponding to the upwardly inclined upper portion of the first bit line structure.

[0013] Because of the design of the preparation method disclosed herein, (NH4)2SiF 6(s) Deposited on one upper opening of an interstitial spacer. This chemical begins to decompose and surround the nitride layer of the first elemental wire structure and the interstitial nitride layer to increase the etching rate. (NH4)2SiF is controlled by the subsequent etching step of the interstitial oxide layer. 6(s) The vaporization rate allows for the acquisition of a desired profile for the gas gap. Therefore, the fabrication method of this disclosure solves problems encountered in the prior art, such as difficulties related to the size of an opening region of a spacer oxide, HF vapor etching time, leakage current, and other related issues. Furthermore, the fabrication method of this disclosure eliminates the need for an additional patterning process to form individual cells and surrounding regions.

[0014] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0015] The disclosure of the present invention can be more fully understood by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0016] Figure 1 This is a cross-sectional schematic diagram illustrating a portion of a semiconductor memory element prepared using known techniques prior to the fabrication of an air gap.

[0017] Figure 2 This is a cross-sectional schematic diagram illustrating a portion of a semiconductor memory element prepared using known techniques after an air gap has been fabricated.

[0018] Figure 3 This is a 3D schematic diagram illustrating a semiconductor memory element of known technology, which has a relatively small interstitial oxide open region.

[0019] Figure 4 This is a 3D schematic diagram illustrating a semiconductor memory element of known technology, which has a relatively large spacer oxide open region.

[0020] Figure 5 This is a cross-sectional schematic diagram illustrating a portion of a semiconductor memory element of the prior art, which includes a spacer oxide having a relatively large height before an air gap is fabricated.

[0021] Figure 6 This is a cross-sectional schematic diagram illustrating a portion of a semiconductor memory element of the prior art, which includes a spacer oxide having a relatively large height after an air gap is fabricated.

[0022] Figure 7 This is a representative flowchart illustrating a method for fabricating a semiconductor memory element according to an embodiment of the present disclosure.

[0023] Figure 8 This is a three-dimensional schematic diagram illustrating an embodiment of the present disclosure in execution. Figure 7 A portion of the semiconductor memory element following step S101.

[0024] Figure 9 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7 A portion of the semiconductor memory element following step S103.

[0025] Figure 10 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7 A portion of the semiconductor memory element following step S105.

[0026] Figure 11 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7A portion of the semiconductor memory element following step S107.

[0027] Figure 12 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7 A portion of the semiconductor memory element during the intermediate stage of step S103.

[0028] Figure 13 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7 A portion of the semiconductor memory element following step S109.

[0029] Figure 14 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7 A portion of the semiconductor memory element following step S111.

[0030] Figure 15 This is a cross-sectional schematic diagram illustrating an embodiment of the present disclosure in performance. Figure 7 A portion of the semiconductor memory element following step S113.

[0031] Figure 16 This is an SEM image, illustrating an embodiment of this disclosure during execution. Figure 7 A portion of the semiconductor memory element following step S113.

[0032] The attached figures are labeled as follows:

[0033] 10: Semiconductor memory devices

[0034] 101: Bitline Structure

[0035] 101a: Bit line tungsten

[0036] 101b: nitride of the site line

[0037] 103: Landing mat

[0038] 105a: Spacer

[0039] 105b: Spacer

[0040] 107: Interstitial oxides

[0041] 109: Opening area

[0042] 111: Interstitial oxide opening region

[0043] 700: Preparation method

[0044] 800: Semiconductor memory element

[0045] 801: Base

[0046] 801a: Cell Area

[0047] 801b: Surrounding Area

[0048] 803: First element line structure

[0049] 803a: Bit line contact point

[0050] 803b: Tungsten layer

[0051] 803c: Nitride layer

[0052] 805: Spacer

[0053] 807: Spacer

[0054] 809: Interstitial oxide layer

[0055] 811: Interstitial Nitride Layer

[0056] 813: Interstitial nitride layer

[0057] 815: Barrier Layer

[0058] 817: Landing mat

[0059] 819: Concave surface

[0060] 821: Silicon nitride layer

[0061] AG1: Air gap

[0062] AG2: Air gap

[0063] AG3: Air gap

[0064] AG4: Air gap

[0065] ATP1: Upward tilt of the upper part

[0066] DP1: Etching Depth

[0067] H1: Depth

[0068] H2: Depth

[0069] IS1: Inclined surface

[0070] IS2: Inclined surface

[0071] O1: Open at the top

[0072] S1: Surface

[0073] S101: Steps

[0074] S103: Steps

[0075] S105: Steps

[0076] S107: Steps

[0077] S109: Steps

[0078] S111: Steps

[0079] S113: Steps

[0080] SW1: Sidewall

[0081] SW2: Sidewall

[0082] SW3: Sidewall

[0083] SW4: Sidewall

[0084] SW5: Sidewall

[0085] TC1: Top corner

[0086] TS1: Top surface

[0087] TS2: Top surface Detailed Implementation

[0088] The details shown herein are merely illustrative examples, intended only to illustrate preferred embodiments of the invention, and presented for the purpose of providing what is considered the most useful and easily understood description of the principles and concepts of various embodiments. In this regard, no attempt is made to show the structural details of the invention in greater detail, rather than to provide a necessary basic understanding of the invention, and the description, taken in conjunction with the accompanying drawings and / or examples, should make it clear to those skilled in the art how various forms of the invention can be embodied in practice. Therefore, before describing the disclosed processes and elements, it should be understood that the aspects described herein are not limited to specific embodiments, devices, or configurations, and thus variations are naturally possible. It should also be understood that the terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting unless specifically defined herein.

[0089] Embodiments or examples of the present disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0090] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0091] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include multiple forms unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, the multiple terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0092] The grouping of alternative elements or embodiments of the invention disclosed herein should not be construed as limiting. Each part of a group may be mentioned and claimed individually or in combination with other parts of the group or other elements found herein. For convenience and / or patentability reasons, it is contemplated that one or more parts of a group may be included in or removed from a group.

[0093] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0094] As used herein, the terms “patterning” and “patterned” are used to describe a step of forming a predetermined pattern on a surface. This patterning step includes various steps and processes and varies according to different embodiments. In some embodiments, a patterning process is employed to pattern an existing thin film or layer. The patterning process includes forming a mask on the existing thin film or layer and removing the unmasked thin film or layer by an etching or other removal process. The mask may be a photoresist or a hard mask. In some embodiments, a patterning process is employed to directly form a patterned layer on a surface. The patterning process includes forming a photoresist film on the surface, performing a photolithography process, and performing a development process. The remaining photoresist film is retained and integrated into the semiconductor device.

[0095] This disclosure will be described in detail with reference to the accompanying drawings, which have component numbers. It should be understood that the drawings are greatly simplified and are not drawn to scale. Furthermore, the dimensions of the drawings have been exaggerated to provide a clear illustration and understanding of the invention.

[0096] Figures 1 to 6 It is a 3D and cross-sectional schematic diagram illustrating a cell region of a semiconductor memory element 10 having multiple air gaps manufactured using known techniques. Figure 7 This is a representative flowchart illustrating a method 700 for fabricating a semiconductor memory element 800 according to an embodiment of the present disclosure. Figures 8 to 16 These are cross-sectional schematic diagrams and SEM images illustrating a portion of a semiconductor memory element during an intermediate stage of performing a fabrication method or after performing multiple steps, according to some embodiments of this disclosure.

[0097] Please refer to Figure 8In step S101, a substrate 801 is provided, having a unit region 801a and a surrounding region 801b. In this disclosure, the term "substrate" refers to and includes a base material or structure on which materials are formed. It should be understood that a substrate may include a single material, multiple layers of different materials, one or more layers with different material regions or different structures therein, or other similar configurations. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, substrate 801 may be a semiconductor substrate, a base semiconductor substrate on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. Substrate 801 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, substrate 801 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductors may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductors may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductors may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP. In some embodiments, substrate 801 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate, a silicon-on-insulator (SOI) substrate, or the like. In some embodiments, substrate 801 is a multilayer structure, including a polycrystalline silicon layer and a metal layer sequentially stacked on substrate 801. In some embodiments, substrate 801 includes a metal layer.

[0098] Please refer to Figure 9In step S103, a first bit line structure 803 is formed on a surface S1 of the cell region 801a. The first bit line structure 803 sequentially includes a bit line contact point 803a, a tungsten layer 803b, and a nitride layer 803c. The bit line contact point 803a is disposed on the surface S1 of the cell region 801a, the tungsten layer 803b is disposed on the bit line contact point 803a, and the nitride layer 803c is disposed on the tungsten layer 803b. The first bit line structure 803 has an upper surface TS1 and two sidewalls SW3 and SW4. Surface TS1 faces away from substrate 801. Sidewalls SW3 and SW4 connect the upper surface TS1 of the first element structure 803 to substrate 801. The first element structure 803 is sandwiched between a pair of spacers 805 and 807, wherein each spacer 805 or 807 includes a spacer oxide layer 809 sandwiched between two spacer nitride layers 811 and 813. A barrier layer 815 conformally covers the plurality of sidewalls SW3 and SW4 adjacent to the first element structure 803 and the plurality of spacers 805 and 807 of unit region 801a. In some embodiments, the first element structure 803 is a columnar body with a circular top. In some embodiments, the first element structure 803 includes a sidewall, an upwardly inclined upper portion, an upper portion, and a downwardly inclined portion. In some embodiments, the upwardly inclined upper portion, the upper portion, and the downwardly inclined portion together form the circular top.

[0099] In some embodiments, the semiconductor structure 800 further includes an adhesive layer (not shown) disposed on a substrate 801 between adjacent pairs of bit line structures 803. The purpose of this adhesive layer is to increase the adhesion between a landing pad 817 (which will be formed in a later processing step) and the barrier layer 815 to prevent the landing pad 817 from peeling off.

[0100] In step S103, the barrier layer 815 may, for example, comprise silicon oxide, silicon oxynitride, silicon nitride, or the like. It should be understood that, in this disclosure, silicon oxynitride represents a substance comprising silicon, nitrogen, and oxygen, wherein the oxygen content is greater than the nitrogen content. Silicon nitride represents a substance comprising silicon, oxygen, and nitrogen, wherein the nitrogen content is greater than the oxygen content. Optionally, a cleaning process using a reducing agent may be performed to remove multiple defects from the substrate 801. The reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

[0101] Please refer to Figure 10In step S105, a landing pad 817 is deposited on the barrier layer 815 and on the upper surface TS1 of the first elemental wire structure 803. In step S105, a process such as atomic layer deposition (ALD), atomic layer epitaxy (ALE), atomic layer chemical vapor deposition (ALCVD), spin coating, sputtering, or a similar process can be used to coat the landing pad 817 over the barrier layer 815 and on the upper surface TS1 of the first elemental wire structure. According to a preferred embodiment of this disclosure, ALD is used to perform the deposition of the landing pad 817 over the barrier layer 815 and on the upper surface TS1 of the first elemental wire structure 803. Alternatively, a planarization process such as chemical mechanical polishing can be performed after step S105.

[0102] Please refer to Figure 11 In step S107, an upper corner TC1 of the landing pad 817 is removed to form an inclined surface IS2, which connects an upper surface TS2 to a sidewall SW5 of the landing pad 817. An upper opening O1 of the spacer 805 or 807 is formed in the inclined surface IS2. In some embodiments of this disclosure, the inclined surface IS2 is a convex surface. In step S107, an etching process, such as an anisotropic dry etching process or a reactive ion etching (RIE) process, may be performed to remove the upper corner TC1 of the landing pad 817, and the inclined surface IS2 is a convex surface. In some embodiments of this disclosure, a directional etching process is performed to remove the upper corner TC1 of the landing pad 817. Figure 11 The upper corner TC1 of the landing pad 817. In some embodiments, multiple etching steps are performed to achieve a desired configuration or a combination of configurations of the inclined surface IS2 of the landing pad 817. In some embodiments, a specific angle dry etching is performed to remove the upper corner TC1 of the landing pad 817.

[0103] Please refer to Figure 12 and Figure 13 In step S109, an etching process is performed using hydrogen fluoride vapor on the nitride layer 803c of the first element structure 803 and the interstitial nitride layers 811 or 813 from the upper opening O1 to form a concave surface 819. The subsequent reaction occurs at the beginning of step S109 to produce (NH4)2SiF. 6(s) :

[0104] 1. SiO 2(s) +4HF (g) →SiF 4(g) +2H 2(g)

[0105] 2. SiF 4(g) +2HF (g) +2NH 3(g)→(NH4)2SiF 6(s)

[0106] 3.(NH4)2SiF 6(s) →SiF 4(g) +2HF (g) +2NH 3(g)

[0107] like Figure 12 As shown, at the end of reaction 2, (NH4)2SiF 6(s) This chemical substance is generated at the upper opening O1 of the spacer 805 or 807. It begins to decompose or surround the nitride layer 803c of the first element line structure 803 and the spacer nitride layer 811 or 813 to improve the etch rate. For example... Figure 13 As shown, after performing step S109, a concave surface 819 is formed.

[0108] Please refer to Figure 14 In step S111, an etching process is performed on the interstitial nitride layer 809 from the concave surface 819 using hydrogen fluoride vapor. The etching process performed in step S111 is, for example, an anisotropic dry etching process or a reactive ion etching (RIE) process. This is achieved by controlling the (NH4)2SiF in step S111. 6(s) The vaporization rate is the desired profile of an air gap AG3. In this disclosure, the term air gap is used to refer to a chamber that may be filled with air, have a gas different from air, or in particular an inert gas, such as argon, or may be a vacuum.

[0109] Please refer to Figure 15 In step S113, a silicon nitride layer 821 is deposited on the semiconductor memory element 800 to seal the air gap AG4. A process such as ALD, ALE, ALCVD, spin coating, sputtering, or similar techniques can be used to apply the silicon nitride layer 821 to the semiconductor memory element 800 to seal the air gap AG3. According to a preferred embodiment of this disclosure, the step of depositing the silicon nitride layer 821 on the semiconductor memory element 800 is performed using ALD. Alternatively, a planarization process, such as chemical mechanical polishing, can be performed after step S113.

[0110] Figure 16 This is an SEM image, illustrating an embodiment of this disclosure during execution. Figure 7 A portion of the semiconductor memory element following step S113. A concave surface is formed on the nitride layer of the first element line structure and the spacer nitride layer.

[0111] Because of the design of the preparation method disclosed herein, (NH4)2SiF6(s) It forms on an upper opening of an interstitial spacer. This chemical substance begins to decompose and surround the nitride layer of the first elemental wire structure and the interstitial nitride layer to increase the etching rate. The (NH4)2SiF is controlled by the subsequent etching step of the interstitial oxide layer. 6(s) The vaporization rate allows for the acquisition of a desired profile for the gas gap. Therefore, the fabrication method of this disclosure solves problems encountered in the prior art, such as difficulties related to the size of an opening region of a spacer oxide, HF vapor etching time, leakage current, and other related issues. Furthermore, the fabrication method of this disclosure eliminates the need for an additional patterning process to form individual cells and surrounding regions.

[0112] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0113] Furthermore, the scope of this invention is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this document that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this invention.

Claims

1. A method for fabricating a semiconductor memory element, comprising: Receive a substrate having a cell region and a surrounding region; A first element line structure is formed on a surface of the cell region, wherein the first element line structure sequentially includes a bit line contact point, a tungsten layer and a nitride layer. The bit line contact point is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact point, and the nitride layer is disposed on the tungsten layer. The first element line structure has an upper surface and two sidewalls. The upper surface is away from the substrate, and the two sidewalls connect the upper surface to the substrate. The first element line structure is sandwiched between a pair of spacers, wherein each spacer includes a spacer oxide layer sandwiched between two spacer nitride layers. A barrier layer conformally covers a plurality of the sidewalls adjacent to the first element line structure and a plurality of the spacers in the cell region. A landing pad is deposited on the barrier layer and on the upper surface of the first elemental structure; Remove one upper corner of the landing pad to form an inclined surface that connects one upper surface of the landing pad to one side wall of the landing pad, wherein an upper opening of the gap is formed in the inclined surface; The nitride layer of the first element line structure and the interstitial nitride layer are etched from the upper opening to form a concave surface; The spacer oxide layer is etched from the concave surface to form an air gap; as well as A silicon nitride layer is deposited to seal the air gap.

2. The method for fabricating a semiconductor memory element as described in claim 1, wherein the substrate is a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, a ceramic substrate, a quartz substrate, a glass substrate, or an insulator-coated silicon substrate.

3. The method for fabricating a semiconductor memory element as described in claim 1, wherein the substrate is a multilayer structure having a polysilicon layer and a metal layer sequentially stacked on the substrate.

4. The method for fabricating a semiconductor memory element as described in claim 1, wherein the substrate comprises a metal layer.

5. The method for fabricating a semiconductor memory element as claimed in claim 1, prior to the step of depositing a landing pad on the barrier layer and on the upper surface of the first element line structure, further includes performing a cleaning process using a reducing agent, wherein the reducing agent is selected from the group consisting of titanium tetrachloride, tantalum tetrachloride, or combinations thereof.

6. The method for fabricating a semiconductor memory element as claimed in claim 1, wherein the step of depositing a landing pad on the barrier layer and on the upper surface of the first element line structure is performed using atomic layer deposition.

7. The method for fabricating a semiconductor memory element as claimed in claim 1, further comprising performing a planarization process after depositing a landing pad on the barrier layer and on the upper surface of the first element line structure.

8. The method for fabricating a semiconductor memory element as claimed in claim 1, wherein a spacer etching is performed to remove the upper corner of the landing pad, and the inclined surface is a convex surface.

9. The method for fabricating a semiconductor memory element as claimed in claim 1, wherein the step of using a hydrogen fluoride vapor to etch the nitride layer and the spacer nitride layer of the first element line structure from the upper opening is performed using an anisotropic dry etching process.

10. The method for fabricating a semiconductor memory element as claimed in claim 1, wherein the step of etching the nitride layer of the first element line structure and the spacer nitride layer from the upper opening to form a concave surface is to use hydrogen fluoride vapor to generate (NH4)2SiF 6(s) The step of etching the interstitial oxide layer from the concave surface to form an air gap is performed using hydrogen fluoride vapor by controlling (NH4)2SiF. 6(s) The vaporization rate is implemented.

11. The method for fabricating a semiconductor memory element as claimed in claim 1, wherein the step of depositing a silicon nitride layer to seal the air gap is performed using atomic layer deposition.

12. The method of fabricating a semiconductor memory element as claimed in claim 1, wherein a directional etching is performed to remove the upper corner of the landing pad, and the inclined surface is a concave surface.

13. The method of fabricating a semiconductor memory element as claimed in claim 1, wherein a dry etching at a specific angle is performed to remove the upper corner of the landing pad.

14. A method for fabricating a semiconductor memory element, comprising: Receive a silicon substrate having a cell region and a surrounding region; A first element line structure is formed on a surface of the cell region, wherein the first element line structure sequentially includes a bit line contact point, a tungsten layer and a nitride layer. The bit line contact point is disposed on the surface of the cell region, the tungsten layer is disposed on the bit line contact point, and the nitride layer is disposed on the tungsten layer. The first element line structure includes an upper surface and two sidewalls. The upper surface is away from the substrate, and the two sidewalls connect the upper surface to the substrate. The first element line structure is sandwiched between a pair of spacers, wherein each spacer includes a spacer oxide layer sandwiched between two spacer nitride layers. A barrier layer conformally covers a plurality of the sidewalls adjacent to the first element line structure and a plurality of the spacers of the cell region. Perform an atomic layer deposition to deposit a landing pad on the barrier layer and on the upper surface of the first elemental structure; Perform a directional etching to remove an upper corner of the landing pad to form a concave surface having an upper opening of the spacer formed in the concave surface; An anisotropic dry etching process is performed to etch the nitride layer and the interstitial nitride layer of the first element line structure from the opening in order to form a concave surface; The spacer oxide layer is etched from the concave surface to form an air gap; as well as A silicon nitride layer is deposited to seal the air gap.

15. The method for fabricating a semiconductor memory element as claimed in claim 14, wherein the silicon substrate is a multilayer structure having a polysilicon layer and a metal layer sequentially stacked on the substrate.

16. The method of fabricating a semiconductor memory element as claimed in claim 14, prior to performing an atomic layer deposition to deposit a landing pad on the barrier layer and on the upper surface of the first element line structure, further comprising performing a cleaning process using a reducing agent, wherein the reducing agent is selected from the group consisting of titanium tetrachloride, tantalum tetrachloride, or combinations thereof.

17. The method for fabricating a semiconductor memory element as claimed in claim 14, wherein the step of etching the nitride layer and the spacer nitride layer of the first element line structure from the upper opening to form a concave surface is performed using hydrogen fluoride vapor to generate (NH4)2SiF. 6(s) The step of etching the interstitial oxide layer from the concave surface to form an air gap is performed using hydrogen fluoride vapor by controlling (NH4)2SiF. 6(s) The vaporization rate is implemented.

18. The method of fabricating a semiconductor memory element as claimed in claim 14, further comprising performing a planarization process after performing an atomic layer deposition to deposit a landing pad on the barrier layer and on the upper surface of the first element line structure.

19. The method for fabricating a semiconductor memory element as claimed in claim 14, wherein the step of depositing a silicon nitride layer to seal the air gap is performed using atomic layer deposition.

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