Flash memory device, method for manufacturing the same, and electronic device

Abstract

The present application provides a flash memory device, a manufacturing method thereof, and an electronic device. The flash memory device includes a semiconductor substrate and a plurality of memory cells; an isolation region and a memory array region are formed on the semiconductor substrate; the plurality of memory cells are formed in the memory array region, and each memory cell is connected to a source line and a bit line; between two adjacent isolation regions, the memory cells in the same row are connected to the same source line to form a string; within each string, no blocking layer is provided in the orthographic projection region of the source line; each string is connected to n bit lines, where n > 32 and n = k * 16, and k is an integer greater than or equal to 3. Based on this, the present application can reduce the resistance Rs of the memory array region, reduce the voltage drop in the memory array region and the impact on Low VCC in the read operation stage, and can also reduce the area occupied by the isolation region, which is beneficial to reducing the area of the memory array region.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and particularly to a flash memory device, a manufacturing method thereof, and an electronic device. Background Art

[0002] In a flash memory device, the SAB (Salicide block) layer is a relatively thin alloy of metal and polysilicon. The SAB layer generally covers the control transistors and storage transistors of the MOS devices in the flash memory device, as well as each wire connected to these structural components. For example, the source line SL (on which the source line voltage VSL is applied) connected to the source of the control transistor, and the bit line BL (on which the bit line voltage VBL is applied) connected to the drain of the storage transistor. The main function of the SAB layer is to prevent the formation of silicide on the surface of the structural components it covers, and it is at least used to reduce the resistance value of the covered structural components. Of course, it can also prevent the covered area from being broken down by charges. However, the SAB layer will cause a relatively large resistance value in the storage array area, resulting in a relatively large voltage drop in the storage array area during the read operation stage, thus having a greater impact on the Low VCC (low power supply voltage or low supply voltage) during the read operation stage. That is to say, if the Low VCC is relatively low, after the voltage drop, the middle part of each storage array area cannot receive the required voltage, and thus the data cannot be read. Summary of the Invention

[0003] In view of this, the present application provides a flash memory device, a manufacturing method thereof, and an electronic device, which can improve the problem that the SAB layer in the flash memory device increases the resistance value Rs of the storage array area and the resulting relatively large voltage drop in the storage array area, which affects the Low VCC during the read operation stage.

[0004] A flash memory device provided by the present application includes:

[0005] A semiconductor substrate, on which an isolation region and a storage array region are formed;

[0006] A plurality of memory cells, formed in the storage array region, each memory cell being connected to a source line and a bit line; between two adjacent isolation regions, the memory cells in the same row are connected to the same source line to form a string; within each string, there is no blocking layer in the orthographic projection region of the source line; each string is connected to n bit lines, where n>32 and n = k * 16, and k is an integer greater than or equal to 3.

[0007] Optionally, k = 8, then n = 128.

[0008] Optionally, the flash memory device further includes a blocking layer, such as the SAB layer; this blocking layer is formed in the isolation region and covers a preset region except the source line.

[0009] Optionally, the isolation region and the memory array region are alternately arranged in sequence along a first direction; the memory array region formed on the semiconductor substrate is arranged in an array, and the isolation regions between two adjacent columns of the memory array region are arranged in sequence along a second direction; wherein, the first direction and the second direction are perpendicular to each other.

[0010] Optionally, the isolation region is provided with a connection portion, the source lines of two adjacent columns of the memory array region extend to the isolation region and are connected to the connection portion, and the connection portion is used for receiving a source line voltage.

[0011] Optionally, the flash memory device further includes a dielectric layer covering the source line, and the dielectric layer is provided with a contact hole; the connection portion is disposed on the dielectric layer, and the connection portion extends into the contact hole and is connected to the source line.

[0012] Optionally, the flash memory device further includes a dielectric layer covering the source line, and the dielectric layer is provided with a contact hole; the connection portion is disposed below the dielectric layer and is on the same layer as the source line, and the orthographic projection of the contact hole falls within the orthographic projection of the connection portion.

[0013] Optionally, the connection portions between two adjacent columns of the memory array region are aligned along the second direction.

[0014] The present application also provides a method for manufacturing a flash memory device for manufacturing the flash memory device as described in any one of the above, and the method includes:

[0015] Providing a semiconductor substrate, and forming an isolation region and a memory array region on the semiconductor substrate;

[0016] Forming a plurality of memory cells in the memory array region, each memory cell being connected to a source line and a bit line; between two adjacent isolation regions, the memory cells in the same row are connected to the same source line to form a string; within each string, there is no blocking layer in the orthographic projection region of the source line; each string is connected to n bit lines, where n>32 and n = k*16, and k is an integer greater than or equal to 3.

[0017] The present application also provides an electronic device, including an electronic component and the flash memory device as described in any one of the above, and the flash memory device is connected to the electronic component.

[0018] As described above, there is no blocking layer formed in the orthographic projection region of the source line of the present application, so as to reduce the resistance Rs of the storage array region, reduce the voltage drop (including the maximum voltage drop) of the storage array region and the impact on LowVCC in the read operation stage; moreover, each string is connected to more than 32 bit lines, that is, within a string, one source line is connected to the storage units connected by more than 32 bit lines. Compared with the existing situation where one source line in a string is connected to the storage units connected by 32 bit lines, the number of isolation regions can be reduced, and the area occupied by the isolation regions is relatively small, which is conducive to reducing the area of the storage array region and conducive to the miniaturization of the flash memory device; even if silicide is generated on the surface of the source line without a blocking layer, resulting in an increase in resistance, the relatively small-sized storage array region allows for the design of a source line with a shorter length, which is conducive to controlling the resistance of the source line within a relatively small range and ultimately will not cause a large increase in the resistance of the entire storage array region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. is a partial layout diagram of a flash memory device provided by an embodiment of the present application;

[0020] Figure 2 FIG. is a cross-sectional schematic diagram of an isolation region of a flash memory device provided by an embodiment of the present application;

[0021] Figure 3 FIG. is a schematic flow chart of a manufacturing method of a flash memory device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In order to solve the above problems existing in the prior art, the present application provides a flash memory device, a manufacturing method thereof, and an electronic device. These several protection subjects are based on the same concept, and the principles of solving problems are basically the same or similar. The implementation manners of each protection subject can be referred to each other, and the repeated parts will not be elaborated.

[0023] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly described below in combination with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only a part of the embodiments of the present application, rather than all embodiments. Without conflict, the following various embodiments and their technical features can be combined with each other, and they also belong to the technical solution of the present application.

[0024] In the description of the embodiments of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for facilitating the description of the technical solutions of the corresponding embodiments, rather than indicating or implying that the device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as a limitation to the present application.

[0025] Please refer to Figure 1 and Figure 2 , a flash memory device provided by an embodiment of the present application includes:

[0026] A semiconductor substrate 1, on which a plurality of isolation regions 1a and a plurality of memory array regions (CellArray) 1b are formed. A single isolation region 1a is located between adjacent memory array regions 1b, and a corresponding isolation structure is provided in the isolation region 1a. The numbers of the isolation regions 1a and the memory array regions 1b shown in the figure are only for exemplary display. In addition, the arrangement manners of these isolation regions 1a and memory array regions 1b, as well as the isolation structure, can be determined adaptively according to the type of the flash memory device, and the present application does not limit them. Taking a floating gate type flash memory device as an example, these memory array regions 1b can be arranged in an array. Then, along the first direction x, the isolation regions 1a and the memory array regions 1b are arranged alternately in sequence; between two adjacent columns of memory array regions 1b, the isolation regions 1a are arranged in sequence along the second direction y.

[0027] Wherein, the first direction x and the second direction y are perpendicular to each other. The first direction x can be regarded as the width direction of the flash memory device and is parallel to the horizontal direction when in the Figure 1 shown placement orientation. The second direction y can be regarded as the height direction of the flash memory device and is parallel to the vertical direction when in the Figure 1 shown placement orientation. And the thickness direction of the flash memory device can be called the third direction z. The first direction x, the second direction y, and the third direction z are perpendicular to each other pairwise and can be regarded as the three coordinate axis directions of a three-dimensional rectangular coordinate system respectively.

[0028] The material of the semiconductor substrate 1 includes but is not limited to at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, other III / V compound semiconductors.

[0029] The semiconductor substrate 1 can be a single-layer structure made of at least one of the above semiconductor materials, such as a single-crystalline silicon semiconductor substrate, or a multi-layer structure, such as a structure using at least one of the technologies of SOI (Silicon on Insulator), SSOI (Stacked Silicon on Insulator), S-SiGeOI (Stacked Germanium Silicon on Insulator), SiGeOI (Germanium Silicon on Insulator), and GeOI (Germanium on Insulator).

[0030] Other necessary structural components can also be formed in the semiconductor substrate 1, such as the gate, source, or drain of a MOS transistor, or a metal interconnect structure electrically connected to the MOS transistor. These structural components can be arranged in the isolation region 1a and the memory array region 1b according to the requirements of the actual scenario.

[0031] Multiple memory cells 2 are formed in the corresponding memory array region 1b. The structures of these memory cells 2 are the same or similar. A single memory cell 2 is connected to a source line SL and a bit line BL. Between two adjacent isolation regions 1a, the memory cells 2 in the same row are connected to the same source line SL to form a string 1c. In each string 1c, no blocking layer is provided in the orthographic projection region of the source line SL; each string 1c is connected to n bit lines BL, where n>32 and n = k*16, and k is an integer greater than or equal to 3. It can be regarded that the source line SL connects multiple memory cells 2 to "strap" to form a string 1c. Figure 1 The area shown by the dotted line in the figure is a string 1c. Optionally, a single source line SL can be connected to multiple strings 1c on both sides of it, so as to reduce the number of source lines SL and reasonably arrange the isolation region 1a and the memory array region 1b of the memory cells 2.

[0032] Moreover, in the orthographic projection (i.e., the orthographic projection along the third direction z) region of the source line SL in each string 1c, no blocking layer is formed in the memory cells 2 of the flash memory device.

[0033] In the existing flash memory device, since an SAB layer is provided above the source line SL to act as a blocking layer, the resistance Rs of the memory array region 1b is relatively large. And this application is equivalent to removing the blocking layer such as the SAB layer in the orthographic projection region of the source line SL, so that the resistance Rs of the memory array region 1b can be reduced, the voltage drop of the memory cells 2 can be reduced, and the influence on Low VCC in the read operation stage can be reduced.

[0034] Taking an existing floating - gate flash memory device as an example, each source line SL is connected to 32 bit lines BL to form a string. The SAB layer will cause a relatively large resistance Rs of about 600 ohm for each memory array region 1b. The driving current applied to each source line SL is about 20 μA. During the read operation stage, the maximum voltage drop (IR drop) is located in the middle part of the string. Then the maximum voltage drop is 600 ohm * 16 * 20 μA = 0.192 V. It can be seen that the maximum voltage drop is relatively large, which will affect the Low VCC during the read operation stage.

[0035] In this application, the blocking layer in the orthographic projection region of the source line SL is removed. The resistance Rs of each memory array region 1b can be reduced to about 30 ohm. Similarly, the driving current applied to each source line SL is about 20 μA. During the read operation stage, the maximum voltage drop is located in the middle part of each string along the first direction x. Then the maximum voltage drop of this application is 30 ohm * (n / 2) * 20 μA.

[0036] This application preferably sets k = 8, then n = 128, that is, each source line SL of each string 1c is connected to 128 bit lines BL. After research and testing, at this time, the resistance Rs of the memory array region 1b, the voltage drop, and the impact on the Low VCC during the read operation stage are relatively balanced, and the read performance of the flash memory device is better. Herein, the maximum voltage drop of this application is (30 ohm * 64 * 20 μA) = 0.0384 μA, which is much smaller than the maximum voltage drop of 0.192 V of the same - type flash memory device, and of course, the impact on the Low VCC during the read operation stage is also smaller.

[0037] It should be understood that the maximum value of n cannot cause the maximum voltage drop of this application to be equal to that of the existing same - type flash memory device. Still taking the above example, the maximum value of n cannot be 640, that is, 3 ≤ k < 40.

[0038] In this application, each string 1c is connected to more than 32 bit lines, that is, within a string 1c, one source line SL is connected to the memory cells 2 connected by more than 32 bit lines BL. Compared with the memory cells 2 connected by one source line SL to 32 bit lines BL within the current string, the number of isolation regions 1a can be reduced. The area occupied by the isolation regions 1a is relatively small, which is conducive to reducing the area of the memory array region 1b and is conducive to the miniaturization of the flash memory device.

[0039] Still taking the existing floating - gate flash memory device as an example, each string includes 32 bit lines BL. Structures for applying the source line voltage VSL are provided in the isolation regions on both sides of these bit lines BL, and the total width occupied is equivalent to 2 bit lines BL. Then the area occupied by each isolation region is 2 / 34 = 5.88%.

[0040] Each string 1c of the present application is provided with more than 32 bit lines BL. Taking 128 bit lines BL as an example, the area occupied by each isolation region 1a is 2 / 130 = 1.54%. It can be seen that the present application can reduce the area occupied by the isolation region 1a by (5.88% - 1.54%) = 4.34%.

[0041] In addition, even if a blocking layer such as a traditional SAB layer is not provided, silicide will be generated on the surface of the source line SL of the present application, resulting in an increase in resistance. However, for smaller-sized memory cells 2, a shorter source line SL can be designed, so that the resistance of the source line SL can also be controlled within a smaller range, and ultimately it will not cause a large increase in the resistance of the entire memory array region 1b. That is to say, even if the blocking layer in the region corresponding to the source line SL is removed, the present application will not cause the resistance to become large.

[0042] Furthermore, the source line SL is connected to the memory cells 2 connected by a large number of bit lines BL, and the stability of the electron flow direction on the source line SL is high, and the charges on the floating gate of MOS devices such as memory tubes are not likely to escape. It can be seen that even if the blocking layer in the region corresponding to the source line SL is removed, the impact on the anti-electron escape effect in the region of the source line SL is small, and the impact on the data retention effect is small.

[0043] The flash memory device of the present application can also be provided with a blocking layer. For example, please refer to Figure 1 and Figure 2 , the blocking layer 3 is formed in the isolation region 1a and covers a preset region except the source line SL. It should be noted that Figure 2 is only for exemplary display, only showing the local structural components related to the source line SL in the isolation region 1a, as well as the gate G of the MOS transistor, etc. The setting of other necessary structural components can refer to the prior art.

[0044] The blocking layer 3 can be an SAB layer, and its function can be the same as that of the existing SAB layer, which will not be elaborated here. That is to say, the present application can only remove the SAB layer in the orthographic projection region of the source line SL and retain the other original SAB layers, thereby reducing the impact of removing the SAB layer to a small extent.

[0045] The material of the blocking layer 3 includes but is not limited to oxides (such as silicon oxide) and / or nitrides.

[0046] The preset area includes, but is not limited to, the position where the isolation structure is located within the isolation area 1a. Since the specific type of the flash memory device is not limited in this application, the specific type of the isolation structure and the electronic components it includes can be determined adaptively according to the actual scenario. For example, it includes, but is not limited to, the control transistor, storage transistor, etc. of the MOS device. Different from the prior art, the blocking layer 3 of this application can also cover the portions of the respective traces connected to these electronic components that extend into the isolation area 1a. For example Figure 2 as shown, it can cover the portion SL-1 of the source line SL that extends into the isolation area 1a.

[0047] In scenarios such as Figure 1 and Figure 2 as shown, the isolation area 1a can be provided with a connection portion 11. The source lines SL of adjacent two columns of memory cells 2 extend into the isolation area 1a and are connected to the connection portion 11. The connection portion 11 can be equivalent to a PAD (connection point or connection block) in the circuit and is used to access the source line voltage VSL.

[0048] The connection portion 11 can be provided on a different layer from the source line SL. As Figure 2 shown, the flash memory device further includes a dielectric layer 4 covering the source line SL. The portion of the source line SL that extends into the isolation area 1a is called the extension portion SL-1, and the dielectric layer 4 also covers the extension portion SL-1; the dielectric layer 4 is provided with a contact hole. Along the third direction z, the orthographic projection of the contact hole falls within the orthographic projection of the extension portion SL-1 of the source line SL. Hereby, the contact hole can expose a part of the extension portion SL-1; the connection portion 11 is provided on the dielectric layer 4 and the connection portion 11 extends into the contact hole to connect with the extension portion SL-1 of the source line SL in this way.

[0049] The connection portion 11 can also be provided on the same layer as the source line SL, so that the connection portion 11 and the source line SL can be formed through one process, simplifying the process. The connection portion 11 is provided below the dielectric layer 4 and on the same layer as the source line SL. Along the third direction z, the orthographic projection of the contact hole falls within the orthographic projection of the connection portion 11. Hereby, the contact hole can expose a part of the connection portion 11, and the connection portion 11 can extend into the contact hole to connect with the structural member applying the source line voltage VSL; or, the structural member applying the source line voltage VSL can extend into the contact hole to connect with the connection portion 11.

[0050] Please continue to refer to Figure 1 , between adjacent two columns of memory array areas 1b, these connection portions 11 can be aligned along the second direction y. That is, the connection portions 11 in the second direction y are located on the same straight line, and adjacent two columns of memory array areas 1b and the structural members inside them can be mirror-symmetrically arranged along this straight line, which is beneficial for preparation.

[0051] It should be understood that the flash memory device provided in the embodiments of the present application is a complete flash memory device and also has the necessary structures of known flash memory devices. Here, only the structural components related to the source line SL and the bit line BL in the flash memory device are described, and other components will not be elaborated.

[0052] The embodiments of the present application also provide a method for manufacturing a flash memory device, which is used to manufacture the flash memory device in any of the above embodiments. As Figure 3 shown, the method includes the following steps S1 and S2.

[0053] S1: Provide a semiconductor substrate, and form isolation regions and a memory array region on the semiconductor substrate.

[0054] S2: Form a plurality of memory cells in the memory array region, each memory cell being connected to a source line and a bit line; between two adjacent isolation regions, the memory cells in the same row are connected to the same source line to form a string; within each string, there is no barrier layer in the orthographic projection region of the source line; each string is connected to n bit lines, where n>32 and n = k*16, and k is an integer greater than or equal to 3.

[0055] Next, in combination with Figure 1 and Figure 2 the method for manufacturing the flash memory device will be described in detail.

[0056] First, provide a semiconductor substrate 1, and form an isolation structure in the semiconductor substrate 1, so as to define an isolation region 1a and a memory array region 1b separated by the isolation structure through the isolation structure, and then form each memory cell 2 on the memory array region 1b.

[0057] The manufacturing process of the memory cell 2 can be determined according to the specific type. For ease of understanding, in the present application, the memory cell 2 is described by taking the example that it includes a selection transistor and a storage transistor connected in series. Both the selection transistor and the storage transistor include a gate electrode and source and drain electrodes located on both sides of the gate electrode. The gate electrode of the selection transistor serves as a selection gate, and the gate electrode of the storage transistor serves as a floating gate. The manufacturing process of the selection transistor and the storage transistor is, for example: first form a gate oxide layer and a polysilicon layer on the semiconductor substrate 1, then perform mask etching to form a selection gate and a floating gate, then form spacer walls 5 on the sidewalls of the selection gate and the floating gate, and finally perform ion implantation to form source and drain electrodes on both sides of the selection gate and the floating gate, where the drain electrode of the storage transistor serves as the bit line BL, the source electrode of the selection transistor serves as the source line SL, and the drain electrode of the selection transistor and the source electrode of the storage transistor can be connected, that is, share one end point.

[0058] Then, form a barrier material layer in the isolation region 1a. In the present application, within each string 1c, no barrier material layer is formed in the orthographic projection region of the source line SL.

[0059] The barrier material layer includes, but is not limited to, oxides or nitrides. This application can be formed by methods such as CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), etc.

[0060] Next, the barrier material layer is etched to form the barrier layer 3. The formation process of the barrier layer 3 is, for example: forming a patterned photoresist layer and / or mask layer on the barrier material layer, the patterned photoresist layer and / or mask layer having an image of the barrier layer, and then using the patterned photoresist layer and / or mask layer as a mask, through corresponding dry or wet etching processes, removing the unnecessary barrier material layer and retaining the required barrier material layer, so as to form the barrier layer 3 in the isolation region 1a. And within each string 1c, no barrier layer 3 is formed in the orthographic projection region of the source line SL, thereby reducing the resistance Rs of the storage array region 1b, reducing the voltage drop in the storage array region 1b, and the impact on Low VCC during the read operation phase.

[0061] Further, a dielectric layer 4 is formed on the semiconductor substrate 1.

[0062] The dielectric layer 4 can be made of various suitable low-K dielectric materials, such as PSG (Phosphorus Doped Silicon Glass), BPSG (Boron Phosphorus Silicon Glass), etc., which have better fluidity, can achieve better filling between gaps, and the upper surface of the easily formed dielectric layer 4 is relatively flat.

[0063] Then, contact holes are formed in the dielectric layer 4, and a conductive material, such as the same conductive material as the connection part 11, is filled in the contact holes to form plugs. The positions of the contact holes correspond to the positions of other electronic components such as the source line SL and the gate G respectively, and then the connection part 11 is formed through deposition and etching processes. Finally, a dielectric layer can be formed on the connection part 11, and other structural components are formed on this dielectric layer. The manufacturing methods of these structural components can refer to the prior art.

[0064] Finally, along the first direction x, the source lines SL of each storage cell 2 are led out through their respective contact holes and are electrically connected correspondingly through the connection part 11 in the isolation region 1a; each bit line BL is led out through its respective contact hole and connects the storage cells 2 corresponding in the second direction y. Within one string 1c of this application, one source line SL is connected to the storage cells 2 connected by more than 32 bit lines BL. Compared with the situation where one source line SL in the current string is only connected to the storage cells 2 connected by 32 bit lines BL, this application can reduce the number of isolation regions 1a, making the area occupied by the isolation regions 1a smaller, which is beneficial to reducing the area of the storage array region 1b and beneficial to the miniaturization of the flash memory device.

[0065] An embodiment of the present application further provides an electronic device, including an electronic component and the flash memory device of any of the above embodiments, where the electronic component is connected to the flash memory device. Therefore, the electronic device has the beneficial effects that can be produced by the flash memory device of the corresponding embodiment.

[0066] The electronic device can be any electronic product or device such as a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or can also be any intermediate product including the flash memory device.

[0067] The above are only some embodiments of the present application, and do not limit the patent scope of the present application accordingly. For those of ordinary skill in the art, any equivalent structural transformation made by using the content of this specification and the drawings shall similarly be included in the patent protection scope of the present application.

[0068] Although terms such as "first" and "second" are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. Additionally, the singular forms "a", "an", and "the" are also intended to include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination. An exception to this definition only occurs when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

Claims

1. A flash memory device, characterized in that, Comprising: A semiconductor substrate, on which an isolation region and a memory array region are provided; A plurality of memory cells, formed in the memory array region, each memory cell being connected to a source line and a bit line; between two adjacent isolation regions, the memory cells in the same row are connected to the same source line to form a string; within each string, no blocking layer is provided in the orthographic projection region of the source line; each string is connected to n bit lines, where 640 > n > 32 and n = k * 16, k is an integer and 3 ≤ k < 40.

2. The flash memory device according to claim 1, characterized in that, The flash memory device further includes a blocking layer, formed in the isolation region and covering a preset region except the source line.

3. The flash memory device according to claim 1 or 2, wherein, The k = 8.

4. The flash memory device according to claim 1, wherein The isolation region and the memory array region are arranged alternately in a first direction; The memory array region formed on the semiconductor substrate is arranged in an array, and the isolation regions between two adjacent columns of the memory array region are arranged in sequence in a second direction; Wherein, the first direction and the second direction are perpendicular to each other.

5. The flash memory device according to claim 4, wherein The isolation region is provided with a connection part, the source lines of two adjacent columns of the memory array region extend to the isolation region and are connected to the connection part, and the connection part is used to receive a source line voltage.

6. The flash memory device according to claim 5, characterized in that, The flash memory device further includes a dielectric layer covering the source line, and the dielectric layer is provided with contact holes; the connection part is arranged on the dielectric layer and extends into the contact holes to be connected to the source line.

7. The flash memory device according to claim 5, wherein The flash memory device further includes a dielectric layer covering the source line, and the dielectric layer is provided with contact holes; the connection part is arranged below the dielectric layer and on the same layer as the source line, and the orthographic projection of the contact hole falls within the orthographic projection of the connection part.

8. The flash memory device according to any one of claims 5 to 7, characterized in that, The connection parts between two adjacent columns of the memory array region are aligned in the second direction.

9. A manufacturing method of a flash memory device, characterized in that, A method for manufacturing the flash memory device as described in any one of claims 1 to 8 above, the method comprising: Providing a semiconductor substrate, and forming an isolation region and a memory array region on the semiconductor substrate; Forming a plurality of memory cells in the memory array region, each memory cell being connected to a source line and a bit line; between two adjacent isolation regions, the memory cells in the same row are connected to the same source line to form a string; within each string, no blocking layer is provided in the orthographic projection region of the source line; each string is connected to n bit lines, where 640 > n > 32 and n = k * 16, k is an integer and 3 ≤ k < 40.

10. An electronic device, characterized in that, Including an electronic component and the flash memory device as described in any one of claims 1 to 8 above, the flash memory device being connected to the electronic component.

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