Drive circuit for switching element and switching circuit

Abstract

In a drive circuit of a switching element, loss caused by a negative bias voltage is reduced, a surge voltage is prevented from damaging the switching element, and the switching element is prevented from being erroneously triggered by switching noise. A drive circuit for driving a switching element, characterized by comprising: a control section having a first terminal connected to a gate terminal of the switching element and a second terminal connected to a source terminal of the switching element, and outputting a control signal from the first terminal to the gate terminal; a first capacitor and a first resistor connected in parallel; and a second capacitor and a second resistor connected in parallel, the first capacitor and the first resistor being connected in series to a first connection line connecting the gate terminal and the first terminal on the gate terminal side of the first connection line, and the second capacitor and the second resistor being connected in series to the first connection line on the first terminal side of the first connection line.

Description

Technical Field

[0001] This invention relates to a drive circuit for a switching element and a switching circuit having the same. Background Technology

[0002] For a long time, techniques have been proposed to use JFETs (Jet FETs) made of SiC (silicon carbide) as switching elements in power converters. In the drive circuit of such switching elements, to prevent malfunctions, a capacitor with a capacitance larger than the stray capacitance generated between the drain and gate is placed between the gate and source of the switching element. Furthermore, to prevent malfunctions, techniques have been proposed to use accelerating capacitors (CgD) to achieve negative bias (see, for example, Patent Document 1). Similarly, techniques have also been proposed to use Zener diodes to achieve negative bias (see, for example, Patent Document 2).

[0003] In conventional drive circuits for switching elements, the use of negative bias leads to a situation where reverse conduction losses caused by the internal diodes of the switching element increase proportionally to the negative bias voltage. Furthermore, since reverse conduction losses are also frequency-dependent, the increase in reverse conduction losses remains a problem even with higher switching frequencies.

[0004] When a bridge arm comprising the switching element described in Patent Document 1 is connected in series to form a half-bridge, in addition to the increased reverse conduction loss mentioned above, further problems arise during the dead time period when both switching elements are off. Specifically, because an RC circuit including an accelerating capacitor CgD is provided at the gate, the gate surge increases when the gate is turned off. If a voltage exceeding the rated voltage Vrat is applied as the gate voltage due to such a gate surge, the switching element may be damaged. Furthermore, when one switching element is turned off, the gate voltage decays towards 0V according to the RC time constant. Therefore, if switching noise caused by the switching of the other switching element occurs, the gate voltage will increase, potentially leading to false triggering. Increasing the negative bias to prevent false triggering will cause the gate voltage to exceed the rated voltage Vrat.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2013-99133

[0008] Patent Document 2: Japanese Patent Application Publication No. 2014-93586 Summary of the Invention

[0009] The technical problem that the invention aims to solve

[0010] The present invention was made in view of the problems mentioned above, and its object is to provide a technique that can reduce losses caused by negative bias voltage, suppress surge voltage damage to switching elements, and suppress false triggering of switching elements caused by switching noise in the drive circuit of switching elements.

[0011] Solutions for solving technical problems

[0012] The present invention is used to solve the above-mentioned technical problems.

[0013] It is a driving circuit for driving switching elements, characterized by having:

[0014] The control unit has a first terminal connected to the gate terminal of the switching element via a first connection line and a second terminal connected to the source terminal of the switching element via a second connection line, and outputs a control signal from the first terminal to the gate terminal;

[0015] A first capacitor and a first resistor connected in parallel; and

[0016] The second capacitor and the second resistor are connected in parallel.

[0017] The first capacitor and the first resistor are connected in series to the first connection line on the gate terminal side of the first connection line.

[0018] The second capacitor and the second resistor are connected in series to the first connection line at the first terminal side of the first connection line.

[0019] According to the present invention, by discharging the charge accumulated in the input capacitance of the switching element through a first capacitor and a second capacitor connected in series with the first connection line, the switching element is switched to an off state. At this time, because the gate-source voltage of the switching element can be turned off at a higher voltage, the gate-source surge voltage can be reduced, damage to the switching element can be suppressed, and reverse conduction losses caused by negative bias can be suppressed. Furthermore, because the input capacitance of the switching element, the first capacitor, and the second capacitor are charged and discharged through a first resistor connected in parallel to the first capacitor and a second resistor connected in parallel to the second capacitor, the gate-source voltage at the time of switching noise is kept low, thus preventing false triggering of the switching element. The gate-source voltage of the switching element is maintained at a higher voltage. Therefore, reverse conduction losses caused by negative bias can be reduced.

[0020] Furthermore, in this invention,

[0021] Alternatively, a mirror clamping circuit can be set between the midpoint of the first capacitor and first resistor of the first connecting line and the midpoint of the second capacitor and second resistor and the second connecting line.

[0022] Therefore, since the impedance of the mirror current can be reduced by using a mirror clamping circuit, the switching noise that occurs under the gate-source voltage of the switching element can be reduced.

[0023] Alternatively, in this invention, it can also be set as follows:

[0024] The first diode and the third resistor, which are connected in series, are connected in parallel to the second capacitor and the second resistor.

[0025] The cathode terminal of the first diode is connected to the first terminal.

[0026] Therefore, since the gate-source voltage can be adjusted to decrease when the switching element is turned off by the first diode and the third resistor, the gate-source voltage can be kept at a high value and the reverse conduction loss can be reduced.

[0027] Alternatively, in this invention, it can also be set as follows:

[0028] A second diode and a fourth resistor, connected in series, are connected between the first capacitor and the first resistor on the first connection line and the gate terminal, and between the second connection line and the second connection line.

[0029] The cathode terminal of the second diode is connected to the first connecting line.

[0030] Accordingly, since the gate-source voltage can be adjusted to increase during the period when the negative bias changes toward 0V by setting the second diode and the fourth resistor, the reverse conduction loss of the switching element during this period can be reduced.

[0031] Alternatively, in this invention, it can also be set as follows:

[0032] Connect the fifth resistor in series to the first terminal side of the second capacitor.

[0033] The second capacitor and the fifth resistor are connected in parallel to the second resistor.

[0034] The third diode and the sixth resistor, which are connected in series, are connected in parallel to the fifth resistor.

[0035] The cathode terminal of the third diode is connected to the first terminal.

[0036] Therefore, by setting the fifth resistor, the sixth resistor, and the third diode, the switching speed of the switching element can be adjusted.

[0037] Furthermore, in this invention,

[0038] A clamping circuit may also be provided to keep the voltage at the gate terminal of the source terminal of the switching element below a predetermined voltage value.

[0039] Therefore, even when a voltage greater than the predetermined voltage value is applied between the gate terminal and the source terminal of the switching element, excessive gate surges can be suppressed because the clamping circuit keeps the voltage below the predetermined voltage value.

[0040] Alternatively, in this invention, it can also be set as follows:

[0041] Connect the fourth diode between the midpoint of the first capacitor and first resistor and the second capacitor and second resistor in the first connection line and the second connection line.

[0042] The cathode terminal of the fourth diode is connected to the first connection line.

[0043] Accordingly, since the impedance is reduced by connecting a fourth diode in the forward direction (forward direction) so that the current flows from the second connection line to the first connection line, the noise can be bypassed and the switching noise can be reduced even when the switching noise occurs in the switching element.

[0044] Furthermore, the present invention can also be configured as follows:

[0045] A switching circuit comprising the switching element being driven by the driving circuit of the switching element.

[0046] Accordingly, by constructing a switching circuit that includes a switching element driven by a driving circuit of the switching element of the present invention, it is possible to reduce the surge voltage of the gate-source voltage of the switching element, suppress damage to the switching element, and suppress reverse conduction losses caused by negative bias. Furthermore, it is possible to prevent false triggering of the switching element when switching noise occurs from other switching elements.

[0047] Alternatively, in this invention, it can also be set as follows:

[0048] This includes a half-bridge circuit composed of the aforementioned switching elements.

[0049] Accordingly, in a switching circuit including a half-bridge circuit, it is possible to reduce the surge voltage between the gate and source of the switching element, suppress damage to the switching element, and suppress reverse conduction losses caused by negative bias. Furthermore, it is possible to prevent false triggering of the switching element due to switching noise from other switching elements.

[0050] Alternatively, in this invention, it can also be set as follows:

[0051] It includes a full-bridge circuit composed of the aforementioned switching elements.

[0052] Accordingly, in a switching circuit including a full-bridge circuit, it is possible to reduce the surge voltage between the gate and source of the switching element, suppress damage to the switching element, and suppress reverse conduction losses caused by negative bias. Furthermore, it is possible to suppress false triggering of the switching element when switching noise occurs from other switching elements.

[0053] Invention Effects

[0054] According to the present invention, it is possible to provide a technique in the drive circuit of a switching element that can reduce losses caused by negative bias voltage, suppress surge voltage damage to the switching element, and suppress false triggering of the switching element caused by switching noise. Attached Figure Description

[0055] Figure 1 A diagram illustrating a switching circuit incorporating the gate drive circuit according to an embodiment of the present invention.

[0056] Figure 2 A circuit diagram illustrating the configuration of a synchronous rectification boost chopper circuit according to an embodiment of the present invention is provided.

[0057] Figure 3 A circuit diagram illustrating the configuration of the gate drive circuit according to Embodiment 1 of the present invention is provided.

[0058] Figure 4 This is an operation sequence diagram of the gate drive circuit according to Embodiment 1 of the present invention.

[0059] Figure 5 A diagram illustrating the current path transfer in the gate drive circuit according to Embodiment 1 of the present invention.

[0060] Figure 6 A sequence diagram illustrating the details of the operation of the gate drive circuit according to Embodiment 1 of the present invention.

[0061] Figure 7 A diagram showing a circuit model corresponding to the gate drive circuit according to Embodiment 1 of the present invention.

[0062] Figure 8 A graph illustrating the simulation results of the gate drive circuit according to Embodiment 1 of the present invention.

[0063] Figure 9 A diagram illustrating the configuration of the full-bridge circuit according to Embodiment 1 of the present invention.

[0064] Figure 10 A diagram illustrating the path of current in the full-bridge circuit according to Embodiment 1 of the present invention.

[0065] Figure 11 A graph illustrating the gate-source voltage in the full-bridge circuit according to Embodiment 1 of the present invention is provided.

[0066] Figure 12 A circuit diagram illustrating the configuration of the gate drive circuit according to Embodiment 2 of the present invention is provided.

[0067] Figure 13 This is an operation sequence diagram of the gate driving circuit according to Embodiment 2 of the present invention.

[0068] Figure 14 A diagram illustrating the current path transfer in the gate drive circuit according to Embodiment 2 of the present invention.

[0069] Figure 15 A sequence diagram illustrating the details of the operation of the gate drive circuit according to Embodiment 2 of the present invention.

[0070] Figure 16 A diagram showing a circuit model corresponding to the gate drive circuit of Embodiment 2 of the present invention.

[0071] Figure 17 A graph illustrating the simulation results of the gate drive circuit according to Embodiment 2 of the present invention.

[0072] Figure 18 A circuit diagram illustrating the configuration of the gate drive circuit according to Embodiment 3 of the present invention is provided.

[0073] Figure 19 This is an operation sequence diagram of the gate drive circuit according to Embodiment 3 of the present invention.

[0074] Figure 20 A diagram showing a circuit model corresponding to the gate drive circuit of Embodiment 3 of the present invention.

[0075] Figure 21 A graph illustrating the simulation results of the gate drive circuit according to Embodiment 3 of the present invention.

[0076] Figure 22 A circuit diagram illustrating the configuration of the gate drive circuit according to Embodiment 4 of the present invention is provided.

[0077] Figure 23 This is an operation sequence diagram of the gate drive circuit according to Embodiment 4 of the present invention.

[0078] Figure 24 A diagram showing the circuit model corresponding to the gate drive circuit of Embodiment 4 of the present invention.

[0079] Figure 25 A graph illustrating the simulation results of the gate drive circuit according to Embodiment 4 of the present invention.

[0080] Figure 26A circuit diagram illustrating the configuration of the gate drive circuit according to Embodiment 5 of the present invention is provided.

[0081] Figure 27 This is an operation sequence diagram of the gate drive circuit according to Embodiment 5 of the present invention.

[0082] Figure 28 A circuit diagram illustrating the configuration of the gate drive circuit according to Embodiment 6 of the present invention is provided.

[0083] Figure 29 A diagram illustrating the configuration of the gate drive circuit according to Embodiment 7 of the present invention.

[0084] Figure 30 A circuit diagram illustrating the configuration of a conventional gate drive circuit.

[0085] Figure 31 This is a sequence diagram of the operation of a conventional gate drive circuit. Detailed Implementation

[0086] [Application Example]

[0087] The application examples of the present invention will now be described with reference to the accompanying drawings.

[0088] The gate drive circuit involved in this invention is, for example, such as Figure 2 The gate drive circuits GD1 and GD2 shown can be applied to the switching elements Q1 and Q2 of the synchronous rectification boost chopper circuit 100, which are respectively used as half-bridge circuits.

[0089] First, refer to Figure 30 The gate drive circuit 300, which can also be applied to the conventional gate drive circuits GD1 and GD2 in the synchronous rectification type boost chopper circuit 100, will be described.

[0090] In the gate drive circuit 300, a gate resistor 302 is disposed on the gate side of the JFET (Junction Field Effect Transistor) 301 and is connected to the gate power supply 304 via a switch 303. Furthermore, a second gate resistor 305 is connected in series between the gate resistor 302 and the switch 303, and a capacitor 306 is connected in parallel with the second gate resistor 305.

[0091] In the gate drive circuit 300, when the JFET is turned on, switch 303b is turned off and switch 303a is turned on. Therefore, gate current is injected from the gate power supply 304 into the JFET 301 through the parallel circuit of the second gate resistor 305 and capacitor 306, and gate resistor 302. Conversely, when the JFET is turned off, switch 303a is turned off and switch 303b is turned on. Therefore, the gate and source of the JFET 301 are short-circuited through gate resistor 302 and the parallel circuit of the second gate resistor 305 and capacitor 306.

[0092] exist Figure 31 The diagram illustrates the operating sequence when this gate drive circuit 300 is used as the gate drive circuits GD1 and GD2 of a synchronous rectification type boost chopper circuit 100. Here, vds_Q1 and vgs_Q1 represent the drain-source voltage and gate-source voltage of switching element Q1, respectively. vds_Q2 and vgs_Q2 represent the drain-source voltage and gate-source voltage of switching element Q2, respectively. In1 and In2 represent the input signals of gate drive circuits GD1 and GD2, respectively.

[0093] When using such a gate drive circuit 300, in Figure 31 Regarding vgs_Q1, as seen in mode IVpr, the gate surge Sr0_Q1 increases when turned off. Similarly, regarding vgs_Q2, as seen in mode IIpr, the gate surge Sr0_Q2 increases when turned off. If a voltage exceeding the gate voltage rating Vrat is applied due to these gate surges, the JFET301, which serves as a switching element, may be damaged. Furthermore, in modes IIpr and IVpr, during the dead time period when both switching elements Q1 and Q2 are off, reverse conduction losses increase. Additionally, when turned off, the gate voltage decays towards 0V according to the RC time constant, increasing switching noise, such as Nz0_Q1, and posing a risk of false triggering (maloperation). On the other hand, if the negative bias is increased to prevent false triggering, as mentioned above, the gate surge causes the gate voltage rating Vrat to exceed the gate voltage rating.

[0094] In contrast, in the gate drive circuit 1, which is an application example of the present invention, by maintaining a high gate voltage when the gate is turned off, reverse conduction losses are reduced while suppressing damage to the switching element caused by turn-off surges. Furthermore, in the gate drive circuit 1, false triggering is suppressed by maintaining a low gate voltage when switching noise occurs.

[0095] The specific configuration of the gate drive circuit 1 is as follows: Figure 3 As shown in the image.

[0096] Switches S1 and S2 are connected in series to a DC power supply (gate power supply) Vs. The negative side of the gate power supply Vs is connected to ground (GND). Switches S1 and S2 open and close according to the input signal Vsig. The output terminal Vout is connected to the gate terminal of the switching element Q via connection line 11, and the GND side terminal of switch S2 is connected to the source terminal of the switching element Q via connection line 12. Between the gate terminal of the switching element Q and the output terminal Vout, starting from the gate terminal side, a capacitor Cs and a resistor Rs are connected in series and in parallel, as are a capacitor Cp and a resistor Rp. A negative bias voltage relative to the gate voltage of the switching element Q can be generated through capacitors Cs and Cp.

[0097] Figure 4 The operation sequence of a synchronous rectification boost chopper circuit 100, equipped with the gate drive circuits according to Embodiment 1, serving as gate drive circuits GD1 and GD2, is shown. Here, vds_Q1 and vgs_Q1 represent the drain-source voltage and gate-source voltage of switching element Q1, respectively. vds_Q2 and vgs_Q2 represent the drain-source voltage and gate-source voltage of switching element Q2, respectively. In1 and In2 represent the input signals of gate drive circuits GD1 and GD2, respectively.

[0098] By connecting a capacitor Cp and a resistor Rp in parallel on the switch S1 and switch S2 sides relative to such a capacitor Cs and resistor Rs, it is possible to maintain a high gate voltage (gate-source voltage) when the gate of the switching element Q is turned off. Thus, as... Figure 4 As shown, it can reduce surge voltage and suppress damage to switching element Q caused by surge voltage exceeding the rated voltage Vrat. Furthermore, it can keep the gate voltage low when switching noise occurs due to the switching of the other bridge arm's switching element. Thus, as... Figure 4 As shown, because the gate voltage does not exceed Vth, it can suppress false triggering of the switching element Q.

[0099] [Example 1]

[0100] The gate driving circuits according to embodiments of the present invention will now be described in more detail with reference to the accompanying drawings.

[0101] The gate drive circuit involved in this embodiment is a circuit connected to the gate side of the switching element. For example, a JFET can be used as the switching element involved in this embodiment, and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with an added resistor between the gate and source can also be used.

[0102] Figure 1 A switching circuit including a switching element having the gate drive circuit involved in this embodiment is shown. Figure 1 (A) is a half-bridge circuit 100 obtained by connecting the pins of two bridge arms, including switching elements Q1 and Q2, in series with the input power supply Vin. Switching elements Q1 and Q2 are driven by gate drive circuits GD1 and GD2, respectively. In the full-bridge circuit 200, the output terminal Vo is led out from the midpoint of the two bridge arms included in each pin. Figure 1 (B) is a full-bridge circuit 200 obtained by connecting two bridge arms, including switching elements Q1 and Q2, connected in series, and two bridge arms, including switching elements Q3 and Q4, connected in parallel to the input power supply. Switching elements Q1, Q2, Q3, and Q4 are gate-driven by gate drive circuits GD1, GD2, GD3, and GD4, respectively. In the full-bridge circuit 200, the output terminal Vo is led out from the midpoint of the two bridge arms included in each pin.

[0103] exist Figure 2 The diagram shows a synchronous rectification boost chopper circuit 100 as an example of a half-bridge circuit. The synchronous rectification boost chopper circuit 100 includes pins connected in series with bridge arms comprising switching elements Q1 and Q2, respectively. A gate drive circuit GD1, which drives the gate of switching element Q1 according to an input signal In1, is connected to the gate terminal and source terminal of switching element Q1. Similarly, a gate drive circuit GD2, which drives the gate of switching element Q2 according to an input signal In2, is connected to the gate terminal and source terminal of switching element Q2.

[0104] Furthermore, the input power supply 101 is connected in parallel to the switching element Q2 at the midpoint between the source terminal of switching element Q1 and the drain terminal of switching element Q2, and at the source terminal side of switching element Q2. The input power supply 101 is connected such that the midpoint between the source terminal of switching element Q1 and the drain terminal of switching element Q2 is the positive terminal, and the source terminal side of switching element Q2 is the negative terminal. Additionally, to ensure that the positive terminal of the input power supply 101 is positive, a polarized electrolytic capacitor 102 is connected in parallel to the input power supply 101. Furthermore, an inductor 103 is connected in series between the positive terminal of the polarized electrolytic capacitor 102 and the midpoint between the source terminal of switching element Q1 and the drain terminal of switching element Q2.

[0105] Load 104 is connected in parallel to the drain terminal of switching element Q1 and the source terminal of switching element Q2 in the pin configuration. Additionally, to ensure the drain terminal of switching element Q1 is positive, a polarized electrolytic capacitor is connected in parallel to load 104.

[0106] Figure 3 To Figure 1 The circuit diagram shown illustrates the detailed configuration of the gate drive circuit GD1 of the synchronous rectification boost chopper circuit 100. Gate drive circuit GD1 and gate drive circuit GD2 have the same configuration. In the description of the common configuration of both gate drive circuits GD1 and GD2, "1" and "2" are omitted.

[0107] Switches S1 and S2 are connected in series to the gate power supply Vs. The negative side of the gate power supply Vs is connected to ground (GND). Switches S1 and S2 are turned on and off according to the input signal Vsig. The output terminal Vout, which is the midpoint between switches S1 and S2, is connected to the gate terminal of the switching element Q via connecting line 11, and the GND side terminal Vgnd of switch S2 is connected to the source terminal of the switching element Q via connecting line 12. The gate driver 10 is configured to include switches S1 and S2, the output terminal Vout, and the GND side terminal Vgnd. By turning switches S1 and S2 on and off, a control signal for the gate terminal of the switching element Q is output from the output terminal Vout of the gate driver 10. Switches S1 and S2 can be, for example, known switching elements such as MOSFETs. The gate driver 10 corresponds to the control unit of the present invention. Connecting lines 11 and 12 correspond to the first connecting line and the second connecting line of the present invention, respectively. In addition, the output terminal Vout and the GND side terminal Vgnd correspond to the first terminal and the second terminal of the present invention, respectively.

[0108] Two capacitors, each connected in parallel with a resistor, are connected in series between the output terminal Vout of connection line 12 and the gate terminal of switching element Q. A capacitor Cs and a resistor Rs connected in parallel are disposed on the gate terminal side of switching element Q. Additionally, a capacitor Cp and a resistor Rp connected in parallel are disposed on the midpoint side of switches S1 and S2. When switching element Q is switched, capacitors Cs and Cp function as accelerating capacitors for the instantaneous charging and discharging of the charge in switching element Q. Furthermore, resistors Rs and Rp function as limiting resistors for the flow of small currents when switching element Q is turned on. A negative bias voltage for the gate voltage of switching element Q can be generated through capacitors Cs and Cp. Here, capacitor Cs and resistor Rs correspond to the first capacitor and first resistor of the present invention, respectively. Furthermore, capacitor Cp and resistor Rp correspond to the second capacitor and second resistor of the present invention, respectively.

[0109] Figure 4The diagram illustrates the operation sequence of a synchronous rectification boost chopper circuit 100, equipped with the gate drive circuits of Embodiment 1, serving as gate drive circuits GD1 and GD2. Here, vds_Q1 and vgs_Q1 represent the drain-source voltage and gate-source voltage of switching element Q1, respectively. vds_Q2 and vgs_Q2 represent the drain-source voltage and gate-source voltage of switching element Q2, respectively. In1 and In2 represent the input signals of gate drive circuits GD1 and GD2, respectively.

[0110] By connecting a capacitor Cp and a resistor Rp in parallel on the switch S1 and switch S2 sides relative to such a capacitor Cs and resistor Rs, the gate voltage (gate-source voltage) when the gate of the switching element Q is turned off can be maintained at a high level. This reduces surge voltage and suppresses damage to the switching element Q due to surge voltage exceeding the rated voltage Vrat. Figure 4 In, for example, for the vgs_Q1 mode IV S The waveform below, for VGS_Q2 mode II S As shown in the waveform below, even if surges Sr1_Q1 and Sr1_Q2 occur, the gate-source voltage when the gate is turned off will not exceed the rated voltage Vrat. Furthermore, the gate voltage can be kept low when switching noise occurs due to the switching element of the other bridge arm. Therefore, it is possible to suppress false triggering of the switching element Q due to the gate voltage exceeding Vth. Figure 4 In, for example, for vgs_Q1 mode I S The waveform below, for VGS_Q2 mode III S As shown in the waveform below, since the gate-source voltage does not exceed Vth when switching noise occurs Nz1_Q1 and Nz1_Q2, false triggering is suppressed.

[0111] Next, the operating principle of the gate drive circuit 1 involved in Embodiment 1 will be described in detail. Figure 5 Figures (A) to (E) illustrate the transfer of current paths in the gate drive circuit. Figure 6 A graph showing the changes in gate-source voltage vgs, voltage vcp of capacitor Cp, and voltage vcs of capacitor Cs caused by the opening and closing of switches S1 and S2.

[0112] For Mode I D Explanation. The current will be in mode I. D The path below is Figure 5As shown in (A), the switching element Q is represented by a parasitic diode Di and an input capacitor Ciss connected in parallel therewith. First, at time T0, the gate driver switch S1 is turned on. At this time, the current supplied from the gate power supply Vs flows through capacitors Cp and Cs, charging the input capacitor Ciss of the switching element Q. By charging the input capacitor Ciss of the switching element Q, as... Figure 6 As shown, the gate-source voltage vgs of the switching element Q increases and it transitions to the on state.

[0113] Next, regarding Mode II D Explanation. The current will be applied in Mode II. D The path below is Figure 5 As shown in (B). Mode II D This is the period during which the input capacitor Ciss of the switching element Q is charged and turned on at time T1. At this time, through the parasitic diode Di of the switching element Q, such as... Figure 6 As shown, the gate-source voltage vgs is clamped to a certain voltage V. F .

[0114] Next, regarding Mode III D Explanation. The current will be applied in Mode III. D The path below is Figure 5 As shown in (C). Here, at time T2, switch S1 is turned off, while switch S2 is turned on. Therefore, as... Figure 6 As shown, the input capacitor Ciss of the switching element Q discharges through capacitors Cp and Cs, and then transitions to the off state. Figure 6 As shown, because the gate-source voltage vgs of the switching element Q is turned off at a higher voltage, gate surges can be reduced and damage to the switching element Q can be suppressed.

[0115] Next, on Pattern IV D Explanation. The current will be applied in mode IV. D The path below is Figure 5 As shown in (D). At this time, the input capacitor Ciss, capacitor Cp, and capacitor Cs of the switching element Q are charged and discharged through resistors Rp and Rs. For example... Figure 6 As shown, because the gate-source voltage vgs of the switching element Q remains high, reverse conduction losses can be reduced.

[0116] Next, for pattern V D Explanation. The current will be in mode V. D The path below is Figure 5 As shown in (E). At this time, the input capacitance Ciss and capacitor Cs of the switching element Q discharge through resistors Rs and Rp. Figure 6 As shown, the gate-source voltage vgs of the switching element Q shifts towards 0V according to the RC time constant.

[0117] (simulation)

[0118] Next, make Figure 7 The gate drive circuit Sim1 shown is used as a model corresponding to the gate drive circuit 1 involved in Embodiment 1, and the effect of negative biasing was confirmed using circuit simulator software.

[0119] In the circuit simulator software, the gate voltage was set to 12V, the drive frequency to 100kHz, the duty cycle to 50%, the resistance of resistor Rp to 130Ω, the resistance of resistor Rs to 200Ω, the capacitance of capacitor Cp to 600pF, and the capacitance of capacitor Cs to 22nF, and the simulation was performed.

[0120] Figure 8 The upper section shows the change in the gate voltage vgs of the switching element Q. Figure 8 The lower section illustrates the variation of the input signal Vsig. (As shown in...) Figure 8 As shown by the shaded area, when the switching element Q is turned off (when the input signal Vsig is disconnected), it can be confirmed that the gate voltage vgs is turned off at a higher voltage.

[0121] (Full-bridge circuit)

[0122] The gate drive circuit 1 involved in this embodiment is used as a configuration Figure 2 The gate drive circuits for the opposing bridge arms of a half-bridge circuit as shown have been described. However, gate drive circuit 1 can also be included in... Figure 1 The gate drive circuit of the switching element in a full-bridge circuit with two pins, as shown in (B), is used. Figure 9 This diagram shows only the lower bridge arm of the full-bridge circuit with two pins. The left bridge arm has a switching element Q1, and the right bridge arm has a switching element Q2. The components of the gate drive circuits 1-1 and 1-2 for each of the switching elements Q1 and Q2 are labeled 1 or 2 after the reference numerals. Since the components are the same as those in the gate drive circuit 1 described above, their description is omitted. The gate drive circuits 1-1 for switching element Q1 and 1-2 for switching element Q2 are operated by the same gate power supply Vs.

[0123] Thus, when gate drive circuit 1 is applied to drive the gates of the switching elements in a full-bridge circuit, since there are no capacitors or resistors between the source terminals of each switching element Q1 and Q2 and the negative terminal of the gate power supply Vs, no mutual interference occurs between gate drive circuit 1-1 and gate drive circuit 1-2. For example, at the instant that switching element Q1 is turned on (when the gate is open), current flows through... Figure 10 The current flows in the path shown by the dashed line in (A), and at the instant the switching element Q1 is turned off (when the gate is turned off), the current flows through... Figure 10 The path shown by the dashed line in (B) flows, so there is no increase in noise in the gate-source voltage or interference with the negative bias value. If there is a capacitor and a resistor between the source terminal of each of the switching elements Q1 and Q2 and the negative terminal of the gate power supply Vs, then the capacitor on the side of switching element Q2 will charge due to the parasitic inductance of the wiring, since the current also flows in the other side (connection line 12-2 of the gate drive circuit 1-2 in the example above). As a result, interference such as an increase in noise in the gate-source voltage vgs2 of switching element Q2 or an effect on the negative bias value will occur. Since such mutual interference does not occur even when using gate drive circuit 1 in the gate drive of the switching elements in the full-bridge circuit, the aforementioned increase in noise in the gate-source voltage and interference with the negative bias value can be suppressed.

[0124] exist Figure 11 In the diagram, the gate-source voltage vgs1 of switching element Q1 is shown as a solid line, and the gate-source voltage vgs2 of switching element Q2 is shown as a dashed line. As described above, no increase in noise or negative bias interference was observed at either gate-source voltage vgs1 or gate-source voltage vgs2.

[0125] [Example 2]

[0126] Next, the gate driving circuit 2 according to Embodiment 2 of the present invention will be described. For configurations common to Embodiment 1, the same reference numerals will be used and detailed descriptions will be omitted. Regarding the gate driving circuit 2 according to this embodiment, it can be used as… Figure 1 and Figure 2 The switching circuit shown, along with gate drive circuits GD1 and GD2 that drive the gates of switching elements Q1 and Q2 in the synchronous rectification boost chopper circuit 100, are applied. Additionally, gate drive circuit 2 can also be applied to... Figure 12 The gate drive of the switching element constituting the full-bridge circuit is shown.

[0127] exist Figure 12The diagram shows the gate drive circuit 2 involved in this embodiment. The gate drive circuit 2 involved in this embodiment is configured by adding a mirror clamping circuit 21 to the gate drive circuit 1 involved in Embodiment 1. Figure 13 The operation sequence of a synchronous rectification boost chopper circuit 100 having the gate drive circuit 2 according to Embodiment 2 as gate drive circuit GD1 and gate drive circuit GD2 is shown.

[0128] The mirror clamping circuit 21 includes a switching element Qs (an N-channel MOSFET), a comparator 211, a clamping logic circuit section 212, and a constant voltage source 213. The inverting input terminal of the comparator 211 and the drain terminal of the switching element Qs are connected between capacitors Cs and Cp via a connection line 11 between the output terminal Vout and the gate terminal of the switching element Q. The non-inverting input terminal of the comparator 211 is connected to the positive terminal of the constant voltage source 213, which outputs a voltage Vth. The output terminal of the comparator 211 is connected to the input terminal of the clamping logic circuit section 212. The negative terminal of the constant voltage source 213 is connected to connection line 12. The gate terminal of the switching element Qs is connected to the output terminal of the clamping logic circuit section 212, while the source terminal is connected to connection line 12. The gate driver 20 is configured to include a switch S1, a switch S2, an output terminal Vout, a GND-side terminal Vgnd, and the mirror clamping circuit 21.

[0129] When the voltage input to the non-inverting input terminal, i.e., the voltage at the midpoint between capacitors Cs and Cp, is greater than the threshold voltage Vth input to the inverting input terminal, comparator 211 outputs a High signal from its output terminal. Conversely, when the voltage input to the non-inverting input terminal is less than the voltage input to the inverting input terminal, comparator 211 outputs a Low signal from its output terminal. When a Low signal is input to comparator 211, the clamping logic circuit 212 turns on the switching element Qs.

[0130] Thus, in the gate drive circuit 2 of Embodiment 2, by adding a mirror clamping circuit 21 to the configuration of Embodiment 1, as in Figure 13 Pattern IV S vds_Q1 under mode II (for mode II) S The same applies to vds_Q2. As seen in (), the gate voltage of the switching element Q can be varied in two stages. Therefore, compared to the gate drive circuit 1 according to Embodiment 1, as can be seen from the waveform of vgs_Q1 at the moment T3 when the switching element Q2 is turned on, the gate voltage of the switching element Q during switching noise can be kept lower. Furthermore, the impedance of the mirror current can be reduced by the switching element Qs through the mirror clamping circuit 21. Thus, switching noise can be reduced.

[0131] Next, the operating principle of the gate drive circuit 2 involved in Embodiment 2 will be explained in detail. Figure 14 Figures (A) to (E) illustrate the transfer of current paths in the gate drive circuit. Figure 15 A graph showing the changes in gate-source voltage vgs, capacitor Cp voltage vcp, capacitor Cs voltage vcs, and switching element Qs voltage vqs caused by the opening and closing of switches S1 and S2.

[0132] For Mode I D Explanation. The current will be in mode I. D The path below is Figure 14 As shown in (A), the switching element Q is represented by a parasitic diode Di and an input capacitor Ciss connected in parallel therewith. First, at time T0, the gate driver switch S1 is turned on. At this time, the current supplied from the gate power supply Vs flows through capacitors Cp and Cs, charging the input capacitor Ciss of the switching element Q. By charging the input capacitor Ciss of the switching element Q, as... Figure 15 As shown, the gate-source voltage vgs of the switching element Q increases and it transitions to the on state.

[0133] Next, regarding Mode II D Explanation. The current will be applied in Mode II. D The path below is Figure 14 (B) shows the pattern. Pattern II D During the period when the input capacitor Ciss of the switching element Q is charged and it is turned on at time T1, the parasitic diode Di of the switching element Q, such as... Figure 15 As shown, the gate-source voltage vgs is clamped to a certain voltage V. F .

[0134] Next, regarding Mode III D Explanation. The current will be applied in Mode III. D The path below is Figure 14 As shown in (C). At time T2, switch S1 is turned off and switch S2 is turned on. Therefore, as... Figure 14 As shown in (C), the input capacitor Ciss of the switching element Q discharges through capacitors Cp and Cs, and transitions to the off state. Figure 15 As shown, because the gate-source voltage vgs of the switching element Q is turned off at a higher voltage, gate surges can be reduced and damage to the switching element Q can be suppressed.

[0135] V cp_II and V cs_II They are respectively Mode II DThe voltages across capacitors Cp and Cs at the endpoints, Vqs_III, and V cp_III They are Mode III D The voltage between the drain and source of the switching element Qs in the mirror clamping circuit 21 at the endpoint and the voltage across the capacitor Cp. Additionally, Q... g and C iss These are the gate charge and input capacitance of the switching element Q, respectively. C p and C s These are the capacitances of capacitors Cp and Cs, respectively. The following equation holds between these physical quantities and the threshold voltage Vth at which the switching element Qs of the mirror clamping circuit 21 is turned on.

[0136]

[0137] Next, on Pattern IV D Explanation. The current will be applied in mode IV. D The path below is Figure 14 As shown in (D). At this time, the input capacitor Ciss, capacitor Cp, and capacitor Cs of the switching element Q are charged and discharged through resistors Rp and Rs. For example... Figure 15 As shown, because the gate-source voltage vgs of the switching element Q remains high, reverse conduction losses can be reduced.

[0138] Next, for pattern V D Explanation. The current will be in mode V. D The path below is Figure 14 As shown in (E). If the drain-source voltage of the switching element Qs falls below Vth, then the switching element Qs will shift to the on state. This enables the switching element Q to achieve cross-mode IV. D and mode V D The two-stage shutdown is achieved. As described above, the drain terminal of the switching element Qs is connected to the midpoint between capacitors Cs and Cp, and the source terminal is connected to connection line 12. By increasing the negative bias value of the switching element Q, malfunctions caused by switching noise during the switching of the opposing bridge arm's switching element can be prevented.

[0139] Next, for pattern VI D Explanation. The current will be in mode VI. D The path below is Figure 14 As shown in (F). At this time, the input capacitance Ciss and capacitor Cs of the switching element Q discharge through the resistor Rs and the switched element Qs after it is turned on. Figure 15 As shown, the gate-source voltage vgs of the switching element Q shifts towards 0V according to the RC time constant.

[0140] (simulation)

[0141] Next, make Figure 16 The gate drive circuit Sim2 shown is used as a model corresponding to the gate drive circuit 2 involved in Embodiment 2, and the effect of negative biasing is confirmed using simulator software.

[0142] In the circuit simulator software, similar to Example 1, the gate voltage was set to 12V, the drive frequency was set to 100kHz, the duty cycle was set to 50%, the resistance value of resistor Rp was set to 130Ω, the resistance value of resistor Rs was set to 200Ω, the capacitance of capacitor Cp was set to 600pF, and the capacitance of capacitor Cs was set to 22nF, and a simulation was performed.

[0143] Figure 17 The upper section shows the change in the gate voltage vgs of the switching element Q. Figure 17 The lower section illustrates the variation of the input signal Vsig. (As shown in...) Figure 17 As shown by the shaded area, when the switching element Q is turned off (when the input signal Vsig is disconnected), it can be confirmed that the gate voltage vgs is turned off at a higher voltage. Furthermore, it can be seen that when the switching element Qs of the mirror clamp circuit is turned on, the gate voltage vgs decays sharply. For example, when the switching element of the opposing bridge arm is switched on, reducing the gate-source voltage vgs can reduce switching noise and suppress malfunctions.

[0144] [Example 3]

[0145] Next, the gate driving circuit 3 according to Embodiment 3 of the present invention will be described. For configurations common to Embodiments 1 and 2, the same reference numerals will be used and detailed descriptions will be omitted. The gate driving circuit according to this embodiment can be considered as... Figure 1 and Figure 2 The diagram shows a switching circuit and gate drive circuits GD1 and GD2 that drive the gates of switching elements Q1 and Q2 in the synchronous rectification boost chopper circuit 100, respectively. Additionally, the gate drive circuit 3 can also be used to construct... Figure 9 The gate drive of the switching element in the full-bridge circuit shown.

[0146] exist Figure 18 The diagram shows the gate drive circuit 3 involved in this embodiment. The gate drive circuit 3 involved in this embodiment is configured by adding a diode Dt and a resistor Rt to the gate drive circuit 2 involved in embodiment 2. Figure 19 The operation sequence of the synchronous rectification type boost chopper circuit 100, which includes the gate drive circuit 3 according to Embodiment 3 as gate drive circuit GD1 and gate drive circuit GD2, is shown.

[0147] In the gate drive circuit 3, the diode Dt and resistor Rt, connected in series, are connected in parallel with the capacitor Cp and resistor Rp. The diode Dt is connected in a forward direction from the gate terminal of the switching element Q towards the output terminal Vout. The cathode terminal of the diode Dt is connected to the output terminal Vout, and the anode terminal of the diode Dt is connected to the resistor Rt. The other end of the resistor Rt, with one end connected to the anode terminal of the diode Dt, is connected to the capacitor Cs and resistor Rs. Here, the diode Dt and resistor Rt correspond to the first diode and third resistor of the present invention, respectively.

[0148] By adding diode Dt and resistor Rt to the gate drive circuit 2 according to Embodiment 2, the gate voltage vgs of the switching element Q can be adjusted in mode IV. D The value decreases. Therefore, because it is possible to maintain the pattern IV at a higher value. D The gate voltage during this period can be reduced, thus reducing the switching element Q1 in mode IV. S Inverse conduction loss (for Mode II) S The same applies to the switching element Q2 below. Furthermore, since the gate drive circuit 3, like in Embodiment 2, includes a mirror clamping circuit 21, it can reduce the gate voltage during switching noise caused by the switching of the opposing bridge arm's switching elements. Therefore, for example, it can prevent noise in Mode I. S The switching noise Nz2_Q1 when the switching element Q2 is turned on causes the switching element Q1 to malfunction.

[0149] (simulation)

[0150] Next, make Figure 20 The gate drive circuit Sim3 shown is used as a model corresponding to the gate drive circuit 3 involved in Embodiment 3, and the effect of negative biasing was confirmed using circuit simulator software.

[0151] In the circuit simulator software, the gate voltage was set to 12V, the drive frequency to 100kHz, the duty cycle to 50%, the resistance of resistor Rp to 130Ω, the resistance of resistor Rs to 200Ω, the capacitance of capacitor Cp to 600pF, the capacitance of capacitor Cs to 22nF, and the resistance of resistor Rt to 300Ω, and a simulation was performed.

[0152] Figure 21 The upper section shows the change in the gate voltage vgs of the switching element Q. Figure 22 The lower section illustrates the variation of the input signal Vsig. Figure 18In the upper section, the dashed line shows the waveform of the gate voltage vgs of the gate drive circuit Sim2, which corresponds to the model of Embodiment 2, and the solid line shows the waveform of the gate voltage vgs of the gate drive circuit Sim3, which corresponds to the model of Embodiment 3. In the gate drive circuit 3 involved in Embodiment 3, as in Figure 21 As shown by the shaded area, the timing of mode IVs can be adjusted by changing the resistance value of resistor Rt. Therefore, for example, by adjusting the resistance value of resistor Rt in conjunction with the switching timing of the switching element of the opposing bridge arm, and reducing the gate-source voltage vgs, switching noise can be reduced and malfunctions can be suppressed.

[0153] [Example 4]

[0154] Next, the gate driving circuit 4 according to Embodiment 4 of the present invention will be described. For configurations common to Embodiments 1, 2, and 3, the same reference numerals will be used, and detailed descriptions will be omitted. The gate driving circuit according to this embodiment can be considered as... Figure 1 and Figure 2 The switching circuit shown, and the gate drive circuits GD1 and GD2 that drive the gates of switching elements Q1 and Q2 of the synchronous rectification boost chopper circuit 100, are used in this application. Additionally, the gate drive circuit 4 can also be used to construct... Figure 9 The gate drive of the switching element in the full-bridge circuit shown.

[0155] exist Figure 22 The diagram shows the gate drive circuit 4 involved in this embodiment. The gate drive circuit 4 involved in this embodiment is configured by adding a diode Df and a resistor Rf to the gate drive circuit 3 involved in embodiment 3. Figure 23 The operation sequence of the synchronous rectification type boost chopper circuit 100, which includes the gate drive circuit 4 according to Embodiment 4 as gate drive circuit GD1 and gate drive circuit GD2, is shown.

[0156] In the gate drive circuit 4, a diode Df connected in series and a resistor Rf connected in parallel are connected between the gate and source of the switching element Q. The diode Df is connected with the direction from the source terminal of the switching element Q toward the gate terminal being forward. The cathode terminal of the diode Df is connected between the gate element of the switching element Q and the capacitor Cs and the resistor Rs in the connection line 11 between the gate element of the switching element Q and the output terminal Vout. The anode terminal of the diode Df is connected to one end of the resistor Rf. Furthermore, the other end of the resistor Rf is connected to the connection line 12 between the source terminal of the switching element Q and the mirror clamping circuit 21. The diode Df and the resistor Rf correspond to the second diode and the fourth resistor of the present invention, respectively.

[0157] By adding a diode Df and a resistor Rf to the gate drive circuit 3 according to Embodiment 3, the gate drive circuit 4 can adjust the gate voltage vgs_Q1 of the switching element Q1 in Mode I. S and Mode II S The gate voltage vgs_Q2 of switching element Q2 is increased in mode III. S and Pattern IV S The same applies to the addition below). Furthermore, since the gate drive circuit 4, like in Embodiment 2, includes a mirror clamping circuit 21, it can reduce the gate voltage during switching noise caused by the switching of the opposing bridge arm's switching element. Therefore, for example, it can prevent the switching noise Nz4_Q1 when the switching element Q2 is turned on in mode IS from causing malfunction of the switching element Q1. Additionally, since the gate drive circuit 4, like in Embodiment 3, includes a diode Dt and a resistor Rt connected in parallel with the capacitor Cp and resistor Rp, it can adjust the gate voltage vgs of the switching element Q in mode IV. S The value decreases. Therefore, because it is possible to maintain the pattern IV at a higher value. S The gate voltage during this period can be reduced, thus reducing the switching element Q1 in mode IV. S Inverse conduction loss under (regarding Mode II) S The same applies to the switching element Q2 below.

[0158] (simulation)

[0159] Next, make Figure 24 The gate drive circuit Sim4 shown is used as a model corresponding to the gate drive circuit 4 involved in Embodiment 4, and the effect of negative biasing was confirmed using circuit simulator software.

[0160] In the circuit simulator software, the gate voltage was set to 12V, the drive frequency to 100kHz, the duty cycle to 50%, the resistance of resistor Rp to 130Ω, the resistance of resistor Rs to 200Ω, the capacitance of capacitor Cp to 600pF, the capacitance of capacitor Cs to 22nF, the resistance of resistor Rt to 300Ω, and the resistance of resistor Rf to 150Ω, and a simulation was performed.

[0161] Figure 25 The upper section shows the change in the gate voltage vgs of the switching element Q. Figure 25 The lower section illustrates the variation of the input signal Vsig. Figure 25In the upper section, the dashed line shows the waveform of the gate voltage vgs of the gate drive circuit Sim3, which corresponds to the model in Embodiment 3, and the solid line shows the waveform of the gate voltage vgs of the gate drive circuit Sim4, which corresponds to the model in Embodiment 4. When the switching element Q is turned off, the increase of the gate voltage vgs in mode Is and mode IIs can be adjusted by changing the resistance value of the resistor Rf. Thus, for example, by cooperating with Figure 25 Adjusting the resistance value of resistor Rf during the dead time period, as shown by the shading, can increase the gate-source voltage vgs and reduce reverse conduction losses.

[0162] [Example 5]

[0163] Next, the gate driving circuit 5 according to Embodiment 5 of the present invention will be described. For configurations common to Embodiments 1, 2, 3, and 4, the same reference numerals will be used, and detailed descriptions will be omitted. Regarding the gate driving circuit according to this embodiment, it can serve as… Figure 1 and Figure 2 The switching circuit shown, and the gate drive circuits GD1 and GD2 that drive the gates of switching elements Q1 and Q2 of the synchronous rectification boost chopper circuit 100, are used in this application. Additionally, the gate drive circuit 5 can also be used to construct... Figure 9 The gate drive of the switching element in the full-bridge circuit shown.

[0164] exist Figure 26 The diagram shows the gate drive circuit 5 according to this embodiment. The gate drive circuit 5 according to this embodiment is constructed by adding a resistor Rgon and a diode Dp and a resistor Rgoff connected in series to the gate drive circuit 4 according to embodiment 4. Figure 27 The operation sequence of the synchronous rectification boost chopper circuit 100, which includes the gate drive circuit 5 according to Embodiment 5 as gate drive circuit GD1 and gate drive circuit GD2, is shown.

[0165] In the gate drive circuit 5, a resistor Rgon is connected to the output terminal Vout side of the capacitor Cp. Thus, the capacitor Cp and resistors Rgon and Rp, which are connected in series, are connected in parallel with the diode Dt and resistor Rt, which are also connected in series. Furthermore, in the gate drive circuit 5, the diode Dp and resistor Rgoff, which are connected in series, are connected in parallel with resistor Rgon. Diode Dp is connected with the direction from the gate terminal of the switching element Q towards the output terminal Vout being forward. The cathode terminal of diode Dp is connected to the output terminal Vout, while the anode terminal is connected to one end of resistor Rgoff. The other end of resistor Rgoff is connected to the output terminal Vout side of the capacitor Cp. Here, resistors Rgon, Rgoff, and diode Dp correspond to the fifth resistor, the sixth resistor, and the third diode, respectively.

[0166] The gate drive circuit 5, by adding resistor Rgon, diode Dp, and resistor Rgoff to the configuration of the gate drive circuit 3 in Embodiment 3, which consists of capacitor Cp, resistor Rp, and diode Dt connected in series and resistor Rt connected in parallel, can adjust the switching speed of the switching element Q. Therefore, compared to the gate drive circuit 3, switching noise can be reduced and surges can be turned off. Furthermore, since the gate drive circuit 5, like in Embodiment 2, includes a mirror clamping circuit 21, it can reduce the gate voltage when switching noise occurs due to the switching of the opposing bridge arm's switching element. Therefore, for example, it can prevent the switching noise Nz5_Q1 when the switching element Q2 is turned on in mode IS from causing malfunction of the switching element Q1. Additionally, since the gate drive circuit 5, like in Embodiment 4, includes diode Df and resistor Rf, it can adjust the gate voltage vgs_Q1 of the switching element Q1 in mode I. S and Mode II S The gate voltage vgs_Q2 of switching element Q2 is increased in mode III. S and Pattern IV S The same applies to adding below.

[0167] [Example 6]

[0168] Next, the gate driving circuit 6 according to Embodiment 6 of the present invention will be described. For configurations common to Embodiments 1, 2, 3, 4, and 5, the same reference numerals will be used, and detailed descriptions will be omitted. Regarding the gate driving circuit 6 according to this embodiment, it can serve as… Figure 1 and Figure 2 The switching circuit shown, along with gate drive circuits GD1 and GD2 that drive the gates of switching elements Q1 and Q2 in the synchronous rectification boost chopper circuit 100, are used in applications. Additionally, the gate drive circuit 6 can also be used to construct... Figure 9The gate drive of the switching element in the full-bridge circuit shown.

[0169] exist Figure 28 The diagram shows the gate drive circuit 6 involved in this embodiment. The gate drive circuit 6 involved in this embodiment is constructed by adding a resistor Rg and a capacitor Cg connected in series, as well as a diode Dg and a Zener diode ZDg connected in series, to the gate drive circuit 5 involved in embodiment 5.

[0170] In the gate drive circuit 6, a diode Dg and a Zener diode ZDg, connected in series between the gate and source terminals of the switching element Q and the diode Df and resistor Rf, are connected between connection lines 11 and 12. The anode terminal of diode Dg is connected to connection line 11, the cathode terminal of diode Dg is connected to the cathode terminal of Zener diode ZDg, and the anode terminal of Zener diode ZDg is connected to connection line 12. Furthermore, a capacitor Cg is connected to Zener diode ZDg. That is, one end of capacitor Cg is connected to the midpoint between the cathode terminals of diode Dg and Zener diode ZDg, and the other end of capacitor Cg is connected to connection line 12. Also, one end of capacitor Cg is connected to one end of resistor Rg. The other end of resistor Rg is connected to the positive side of the gate power supply Vs via the end opposite to the output terminal Vout side of the switch S1 of the gate driver 20.

[0171] In the gate drive circuit 6, a constant voltage is generated from the gate power supply Vs via the resistor Rg, capacitor Cg, and Zener diode ZDg connected as described above. This constant voltage value corresponds to the Zener voltage design of the Zener diode ZDg. Therefore, when a gate voltage vgs larger than the constant voltage value is applied, the gate current flows from connection line 11 to diode Dg. At this time, since the voltage of the Zener diode ZDg, which supplies the Zener current, is maintained at the Zener voltage, the gate voltage vgs is kept below the constant voltage value, and voltage clamping is achieved. With this configuration, excessive gate surges can be suppressed in the gate drive circuit 6. Furthermore, as... Figure 28 As shown, when the current-driven JFET is used as a switching element Q, since the gate voltage is applied according to the gate current, the short-circuit current during a short circuit can be suppressed by suppressing the gate voltage, i.e., suppressing the gate current. The resistor Rg, capacitor Cg, Zener diode ZDg, and diode Dg correspond to the clamping circuit of this invention, and the constant voltage value designed for the Zener voltage of the Zener diode corresponds to the predetermined voltage value of this invention.

[0172] A constant voltage circuit is generated by resistor Rg, capacitor Cg, and Zener diode ZDg. However, the structure of a constant voltage circuit is not limited to this and can also be constructed by voltage regulators, etc.

[0173] [Example 7]

[0174] Next, the gate driving circuit 6 according to Embodiment 7 of the present invention will be described. For configurations common to Embodiments 1, 2, 3, 4, 5, and 6, the same reference numerals will be used, and detailed descriptions will be omitted. The gate driving circuit 7 according to this embodiment can be considered as... Figure 1 and Figure 2 The switching circuit shown, along with gate drive circuits GD1 and GD2 that drive the gates of switching elements Q1 and Q2 in the synchronous rectification boost chopper circuit 100, are used in applications. Additionally, the gate drive circuit 7 can also be used to construct... Figure 9 The gate drive of the switching element in the full-bridge circuit shown.

[0175] exist Figure 29 The diagram shows the gate drive circuit 7 according to this embodiment. The gate drive circuit 7 according to this embodiment is configured by adding a diode Dc to the gate drive circuit 6 according to embodiment 6.

[0176] In the gate drive circuit 7, diode Dc is connected between the midpoint of capacitors Cs and Cp in connection line 11 and connection line 12. The cathode terminal of diode Dc is connected to the side of connection line 11, while the anode terminal is connected between resistor Rf in connection line 12 and mirror clamping circuit 21. Diode Dc corresponds to the fourth diode of this invention.

[0177] In the gate drive circuit 7, as described above, the diode Dc is connected in a forward direction, with the current flowing from the connection line 12 connected to the source terminal of the switching element Q toward the connection line 11 connected to the gate terminal. Therefore, during the off-state of the switching element Q, when switching noise is generated at the gate voltage vgs, the diode Dc can reduce the impedance and bypass the noise. As a result, the switching noise occurring in the switching element Q can be reduced.

[0178] <Appendix 1>

[0179] A driving circuit (1, 2, 3, 4, 5) for driving a switching element (Q), characterized in that it comprises:

[0180] The control unit (10) has a first terminal (Vout) connected to the gate terminal of the switching element (Q) and a second terminal (Vgnd) connected to the source terminal of the switching element (Q), and outputs a control signal from the first terminal (Vout) to the gate terminal;

[0181] A first capacitor (Cs) and a first resistor (Rs) connected in parallel; and

[0182] The second capacitor (Cp) and the second resistor (Rp) are connected in parallel.

[0183] The first capacitor (Cs) and the first resistor (Rs) are connected in series to the first connection line (11) on the gate terminal side of the first connection line (11) connecting the gate terminal and the first terminal (Vout).

[0184] The second capacitor (Cp) and the second resistor (Rp) are connected in series to the first connection line (11) at the first terminal (Vout) side.

[0185] Explanation of reference numerals in the attached figures

[0186] 1, 2, 3, 4, 5: Gate drive circuit

[0187] 10: Gate Driver

[0188] 11, 12: Connecting wires

[0189] 100, 200: Switching circuit

[0190] Q: Switching elements

[0191] Cs, Cp: Capacitors

[0192] Rs, Rp: Resistance.

Claims

1. A driving circuit for a switching element, characterized in that, have: The control unit has a first terminal connected to the gate terminal of the switching element via a first connection line and a second terminal connected to the source terminal of the switching element via a second connection line, and outputs a control signal from the first terminal to the gate terminal; A first capacitor and a first resistor connected in parallel; The second capacitor and the second resistor are connected in parallel; as well as The first diode and the third resistor are connected in series. On the gate terminal side of the first connection line, the first capacitor and the first resistor are connected in series to the first connection line. On the first terminal side of the first connecting line, the second capacitor and the second resistor are connected in series to the first connecting line. The first diode and the third resistor are connected in parallel to the second capacitor and the second resistor. The cathode terminal of the first diode is connected to the first terminal.

2. The driving circuit for the switching element according to claim 1, characterized in that, A mirror clamping circuit is provided between the midpoint of the first capacitor and the first resistor of the first connecting line and the midpoint of the second capacitor and the second resistor and the second connecting line.

3. The driving circuit for the switching element according to claim 1, characterized in that, A second diode and a fourth resistor, connected in series, are connected between the first capacitor and the first resistor on the first connection line and the gate terminal, and between the second connection line and the second connection line. The cathode terminal of the second diode is connected to the first connecting line.

4. The driving circuit for the switching element according to claim 1, characterized in that, Connect the fifth resistor in series to the first terminal side of the second capacitor. The second capacitor and the fifth resistor are connected in parallel to the second resistor. The third diode and the sixth resistor, which are connected in series, are connected in parallel to the fifth resistor. The cathode terminal of the third diode is connected to the first terminal.

5. The driving circuit for the switching element according to claim 1, characterized in that, The driving circuit of the switching element is provided with a clamping circuit that keeps the voltage of the gate terminal of the source terminal of the switching element below a predetermined voltage value.

6. The driving circuit for the switching element according to claim 1, characterized in that, Connect the fourth diode between the midpoint of the first capacitor and the first resistor and the second capacitor and the second resistor in the first connection line and the second connection line. The cathode terminal of the fourth diode is connected to the first connection line.

7. A switching circuit comprising the switching element driven by a driving circuit of the switching element according to any one of claims 1 to 6.

8. The switching circuit according to claim 7, wherein, The switching circuit includes a half-bridge circuit composed of the switching elements.

9. The switching circuit according to claim 7, wherein, The switching circuit includes a full-bridge circuit composed of the switching elements.

Images