Preprocessing device, method and time measurement system for a time signal

Abstract

This application relates to a time signal preprocessing apparatus, method, and time measurement system. The apparatus includes a jitter detection module and a filtering module. The jitter detection module receives the time signal to be measured and performs jitter detection on it to output an initial state signal. The filtering module, connected to the jitter detection module, receives the initial state signal, determines its operating mode based on the initial state signal, and performs jitter filtering on the time signal according to the determined operating mode. Using this apparatus, jitter detection and filtering can be performed on the time signal to be measured, ensuring that the signal output from the preprocessing apparatus to the time measurement unit is jitter-free, thus completing the time measurement.

Description

Technical Field

[0001] This application relates to the field of semiconductor automatic testing technology, and in particular to a time signal preprocessing apparatus, method and time measurement system. Background Technology

[0002] Digital test sub-boards are the main components of Automatic Test Equipment (ATE) for performing functional tests on the digital components of digital chips or mixed-signal chips, and are an important part of ATE equipment. Digital sub-boards integrate dozens or even hundreds of channels and are complete digital test subsystems that include dynamic functional testing, DC and time parameter measurements. They can quickly, accurately, and comprehensively test various large, medium, and small-scale random logic digital integrated circuits and various general-purpose memory chips.

[0003] A digital daughterboard generally consists of a pin driver chip, a controller, and memory. The chip integrates multiple functions such as drivers, comparators, and electronic loads, while the controller is typically a Field Programmable Gate Array (FPGA). Time parameter measurement is a common test function in ATE equipment. In digital daughterboards with integrated time measurement functionality, the time-measured signal is converted into a digital signal by the chip's comparator and sent to the controller's Time Measurement Unit (TMU) for measurement. Due to the very high channel integration of digital daughterboards—often dozens or hundreds of channels in a single board—achieving a dedicated TMU for each channel presents a challenge in terms of hardware and logic resources. Because some chips' comparators lack hysteresis, in practical time measurement applications, it has been found that when the rising or falling edge of the time-measured signal is very slow, the comparator's output signal may exhibit jitter. This jittered signal, when sent to the time measurement unit, can lead to measurement failure or incorrect results, preventing accurate measurement. Summary of the Invention

[0004] Therefore, it is necessary to provide a preprocessing device and method based on FPGA that can perform jitter filtering on the measured time signal to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a time signal preprocessing apparatus. The apparatus includes:

[0006] The jitter detection module is used to receive the measured time signal and perform jitter detection on the measured time signal to output the initial state signal of the measured time signal;

[0007] A filtering module, connected to the jitter detection module, is used to receive the initial state signal, determine the operating mode of the filtering module based on the initial state signal, and perform jitter filtering processing on the measured time signal according to the determined operating mode.

[0008] In one embodiment, the operating mode includes a low-level sensitive mode and a high-level sensitive mode, and the initial state signal includes a high-level signal and a low-level signal; the filtering module includes:

[0009] The high-level sensitive unit is configured with a high-level sensitive mode, which is used to receive the measured time signal and a preset high-level sensitive state signal, perform logical operations on the received signal, and output a first valid signal when the measured time signal is a high-level signal;

[0010] The low-level sensitive unit is configured with a low-level sensitive mode, which is used to receive the measured time signal and a preset low-level sensitive state signal, perform logical operations on the received signal, and output a second valid signal when the measured time signal is a low-level signal.

[0011] A first flip-flop has its D terminal used to receive the initial state signal. The asynchronous preset terminal of the first flip-flop is connected to the output terminal of the high-level sensitive unit to receive the first valid signal. The asynchronous clear terminal of the first flip-flop is connected to the output terminal of the low-level sensitive unit to receive the second valid signal. The first flip-flop is used to perform jitter filtering on the measured time signal based on one of the first valid signal and the second valid signal, as well as the initial state signal, to output a target time signal. The target time signal has the opposite level to the initial state signal.

[0012] In one embodiment, the high-level sensitive unit includes a first AND gate, the first input of which is used to receive the measured time signal, the second input of which is used to receive the preset high-level sensitive state signal, and the output of which is connected to the asynchronous preset terminal.

[0013] In one embodiment, the low-level sensitive unit includes:

[0014] The first NOT gate, whose input is used to receive the measured time signal and invert the measured time signal;

[0015] The second AND gate has its first input connected to the output of the first NOT gate, its second input used to receive the preset low-level sensitive state signal, and its output connected to the asynchronous clear terminal.

[0016] In one embodiment, the jitter detection module includes:

[0017] The first jitter detection trigger unit is used to receive the measured time signal and output a first detection signal according to the measured time signal and a preset state signal;

[0018] The second jitter detection trigger unit is used to receive the measured time signal and output a second detection signal according to the measured time signal and a preset state signal;

[0019] The processing unit is connected to the first jitter detection trigger unit and the second jitter detection trigger unit respectively, and is used to determine whether the measured time signal jitters according to the first detection signal and the second detection signal, and output the initial state signal.

[0020] In one embodiment, the first jitter detection triggering unit includes:

[0021] The third AND gate has a first input terminal for receiving the measured time signal and a second input terminal for receiving the preset state signal.

[0022] The second flip-flop has its asynchronous preset terminal connected to the output terminal of the third AND gate, and is used to receive the first trigger result output by the output terminal of the third AND gate, and output a first detection signal according to the first trigger result.

[0023] In one embodiment, the second jitter detection triggering unit includes:

[0024] The second NOT gate is used to receive the measured time signal and invert the measured time signal.

[0025] The fourth AND gate has its first input connected to the output of the second NOT gate, and its second input is used to receive the preset state signal.

[0026] The third flip-flop has its asynchronous preset terminal connected to the output terminal of the fourth AND gate, and is used to receive the second triggering result output by the output terminal of the fourth AND gate, and output a second detection signal according to the second triggering result.

[0027] In one embodiment, the first detection signal and the second detection signal are either low-level signals or high-level signals, wherein the processing unit is further configured to:

[0028] If the first detection signal output is a high-level signal and the second detection signal output is a low-level signal, then the initial state signal output is a non-jittering high-level signal;

[0029] If the first detection signal output is a low-level signal and the second detection signal output is a high-level signal, then the initial state signal output is a non-jittering low-level signal;

[0030] If the first detection signal output is a high-level signal and the second detection signal output is a high-level signal, then the measured time signal is determined to be a jitter signal.

[0031] In one embodiment, if the measured time signal is determined to be a jitter signal, the processing unit is further configured to:

[0032] Obtain the filtered delay signal, and filter and delay the jitter signal based on the filtered delay signal to obtain the jitter end signal;

[0033] The first detection signal and the second detection signal of the jitter end signal are obtained based on the first jitter detection trigger unit and the second jitter detection trigger unit, and the initial state signal is output according to the first detection signal and the second detection signal.

[0034] In one embodiment, it further includes:

[0035] The first selection module is connected to the jitter detection module and is used to determine the measured time signal and output the measured time signal to the jitter detection module.

[0036] A time control module, connected to the jitter detection module and the filtering module, is used to control the filtering time;

[0037] The self-test module is used to output a self-test signal so that the time measurement unit can evaluate whether the time measurement unit is working properly.

[0038] The second selection module is connected to the self-test module, the first selection module, and the filtering module, and is used to output one of the self-test signal, the target time signal, and the measured time signal to the time measurement unit.

[0039] Secondly, this application also provides a time measurement system, comprising:

[0040] A conversion device is used to acquire an external time signal and convert the external time signal into the measured time signal;

[0041] The aforementioned time signal preprocessing device is used to perform jitter filtering on the measured time signal;

[0042] The time measurement unit is connected to the time signal preprocessing device and is used to measure the time signal after jitter filtering.

[0043] Thirdly, this application also provides a method for preprocessing time signals, the method comprising:

[0044] Receive the time signal to be measured, and perform jitter detection on the time signal to be measured, so as to output the initial state signal of the time signal to be measured;

[0045] The system receives the initial state signal, determines the operating mode based on the initial state signal, and performs jitter filtering on the measured time signal according to the determined operating mode.

[0046] In one embodiment, the initial state signal includes a low-level signal; the step of receiving the initial state signal, determining the operating mode based on the initial state signal, and performing jitter filtering on the measured time signal based on the determined operating mode includes:

[0047] When the received initial state signal is a low-level signal, the working mode is determined to be a high-level sensitive mode. The measured time signal and the preset high-level sensitive mode signal are received, and logical operations are performed on the received signals. When the measured time signal is high, the first valid signal is output.

[0048] The measured time signal is subjected to jitter filtering based on the first valid signal and the initial state signal to output a target time signal, the target time signal having the opposite level to the initial state signal.

[0049] In one embodiment, the initial state signal further includes a high-level signal; the step of receiving the initial state signal, determining the operating mode of the filtering module based on the initial state signal, and performing jitter filtering processing on the measured time signal according to the determined operating mode includes:

[0050] When the received initial state signal is a high-level signal, the working mode is determined to be a low-level sensitive mode. The measured time signal and the preset low-level sensitive mode signal are received, and logical operations are performed on the received signals. When the measured time signal is low, a second valid signal is output.

[0051] The measured time signal is subjected to jitter filtering based on the second valid signal and the initial state signal to output a target time signal, the target time signal having the opposite level to the initial state signal.

[0052] The aforementioned time signal preprocessing apparatus, method, and time measurement system detect jitter in the time signal under test using a jitter detection module to determine the initial state signal of the time signal under test. The filtering module performs jitter filtering on the time signal under test based on the initial state signal. This allows the time signal to be filtered and de-jittered before entering the time measurement unit, so as to output a jitter-free time signal to the time measurement unit, thereby successfully completing the time measurement and improving the effectiveness and accuracy of the time measurement. Attached Figure Description

[0053] Figure 1 This is a structural framework diagram of a preprocessing system in one embodiment;

[0054] Figure 2 This is a diagram showing the working mode transitions of the state machine in one embodiment;

[0055] Figure 3 This is a structural diagram of the preprocessing apparatus in one embodiment;

[0056] Figure 4 This is a structural diagram of the preprocessing apparatus in one embodiment;

[0057] Figure 5 This is a structural diagram of the preprocessing apparatus in one embodiment;

[0058] Figure 6 This is a structural diagram of the preprocessing apparatus in one embodiment;

[0059] Figure 7 This is a structural diagram of the preprocessing apparatus in one embodiment;

[0060] Figure 8 This is a waveform diagram of the measured time signal in one embodiment;

[0061] Figure 9 This is a schematic diagram of the steps of a preprocessing method in one embodiment;

[0062] Figure 10 This is a schematic diagram of the steps of a preprocessing method in one embodiment;

[0063] Figure 11 This is a schematic diagram of the steps of a preprocessing method in one embodiment;

[0064] Figure 12 This is a schematic diagram of the steps of a preprocessing method in one embodiment;

[0065] Figure 13 Here is a flowchart of a preprocessing method in one embodiment;

[0066] Figure 14 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0068] The time signal preprocessing apparatus provided in this application embodiment can be applied to, for example... Figure 1 The time measurement system shown includes a conversion device 10, a preprocessing device 20, and a time measurement unit 30. The conversion device 10 acquires an external time signal and converts it into the time signal to be measured. This conversion device can be a comparator, including a high-level threshold comparator and a low-level threshold comparator. The output signal of the high-level threshold comparator is called CMPH, and the output signal of the low-level threshold comparator is called CMPL. Different comparator output signals need to be selected for measuring different time parameters. The conversion device 10 acquires the external time signal and converts it into a digital signal, i.e., the time signal to be measured. The preprocessing device 20 is located in an FPGA, which includes a lookup table and D flip-flops. The D flip-flops can be programmed to perform preprocessing functions to acquire the preprocessing device 20, which is used to perform jitter filtering on the time signal to be measured. The time measurement unit 30 is connected to the preprocessing device 20 and is used to measure the time signal after jitter filtering.

[0069] The FPGA is also equipped with a finite state machine (FSM), hereinafter referred to as the state machine, which acts as a control center, controlling the processing flow of the preprocessing method by controlling the transitions between various working modes. Figure 2 As shown, the operating modes of the state machine include: IDLE mode, high-level sensitive mode SEL_HIGH, low-level sensitive mode SEL_LOW, high-level sensitive delay mode FILTER_HIGH, and low-level sensitive delay mode FILTER_LOW. IDLE mode is the start state, in which the jitter detection module confirms the initial state signal INIT_ST of the input signal. The filtering module performs jitter filtering processing on the measured time signal under the high-level sensitive mode SEL_HIGH and the high-level sensitive delay mode FILTER_HIGH, as well as the low-level sensitive mode SEL_LOW and the low-level sensitive delay mode FILTER_LOW.

[0070] In one embodiment, such as Figure 3As shown, a time signal preprocessing device is provided, including a jitter detection module 200 and a filtering module 210.

[0071] The jitter detection module 200 is used to receive the time signal to be measured, perform jitter detection on the time signal to be measured, and output the initial state signal of the time signal to be measured.

[0072] The external time signal is converted into a digital signal by a conversion device such as a comparator. The jitter detection module 200 receives the digital signal and uses it as the time signal to be measured. The time signal to be measured is detected to see if there is jitter. If there is no jitter, the initial state signal INIT_ST of the time signal to be measured is determined. The initial state signal includes a low-level signal and a high-level signal.

[0073] The filtering module 210, connected to the jitter detection module, is used to receive the initial state signal, determine the working mode of the filtering module according to the initial state signal, and perform jitter filtering processing on the measured time signal according to the determined working mode.

[0074] The filtering module is configured with a high-level sensitive mode and a low-level sensitive mode, and can select the corresponding working mode to perform filtering and de-jitter processing on the initial state signal based on different initial state signals.

[0075] In this embodiment, the jitter detection module detects jitter in the time signal under test to determine the initial state signal of the time signal under test. The filtering module performs jitter filtering on the time signal under test based on the initial state signal to output a jitter-free time signal to the time measurement unit, thereby successfully completing the time measurement and improving the effectiveness and accuracy of the time measurement.

[0076] In one embodiment, such as Figure 4 As shown, the jitter detection module 200 includes a first jitter detection trigger unit 202, a second jitter detection trigger unit 204, and a processing unit 206.

[0077] The first jitter detection trigger unit 202 is used to receive the measured time signal and output a first detection signal according to the measured time signal and a preset state signal.

[0078] The first jitter detection trigger unit 202 can be a jitter detection trigger. The preset state signal is a signal that the state machine is in the IDLE state. In the IDLE state, the measured time signal is input to the jitter detection trigger. Based on the first triggering result of the jitter detection trigger by the measured time signal, a first detection signal can be output.

[0079] The second jitter detection trigger unit 204 is used to receive the measured time signal and output a second detection signal according to the measured time signal and the preset state signal.

[0080] The second jitter detection trigger unit 204 can be a jitter detection trigger. In the IDLE state, the time signal to be measured is input to the jitter detection trigger, and a second detection signal can be output based on the second triggering result of the jitter detection trigger according to the time signal to be measured.

[0081] The processing unit 206 is connected to the first jitter detection trigger unit 202 and the second jitter detection trigger unit 204 respectively, and is used to determine whether the measured time signal jitters according to the first detection signal and the second detection signal, and output the initial state signal.

[0082] Processing unit 206 analyzes the initial state of the measured time signal based on the first detection signal and the second detection signal to determine whether it is low or high. Specifically, the first detection signal and the second detection signal are either 0 or 1. Processing unit 206 is further configured to:

[0083] If the first detection signal output is 1 and the second detection signal output is 0, then the initial state signal is output as a high level without jitter.

[0084] If the first detection signal JIT_DECT0 outputs 1 and the second detection signal JIT_DECT1 outputs 0, it indicates that the measured time signal TMU_SIGNAL input is 1 and there is no jitter, i.e., a high level without jitter.

[0085] If the first detection signal output is 0 and the second detection signal output is 1, then the initial state signal output is a low level without jitter.

[0086] If the first detection signal JIT_DECT0 outputs 0 and the second detection signal JIT_DECT1 outputs 1, it indicates that the input of the measured time signal TMU_SIGNAL is 0 and there is no jitter, i.e., a low level without jitter.

[0087] If the first detection signal output is 1 and the second detection signal output is 1, then the measured time signal is determined to be a jitter signal.

[0088] If both the first detection signal JIT_DECT0 and the second detection signal JIT_DECT output 1, it indicates that the measured time signal TMU_SIGNAL is jittering, and its high or low level cannot be determined at this time.

[0089] In this embodiment, the first jitter detection trigger unit outputs a first detection signal of the measured time signal, and the second jitter detection trigger unit outputs a second detection signal of the measured time signal, thereby enabling the processing unit to determine the initial state signal of the measured time signal based on the first detection signal and the second detection signal.

[0090] In one embodiment, such as Figure 5 As shown, the first jitter detection trigger unit 202 includes a third AND gate 2022 and a second trigger 2024.

[0091] The third AND gate 2022 has a first input terminal for receiving the measured time signal and a second input terminal for receiving the preset IDLE state signal.

[0092] The second flip-flop 2024 has its asynchronous preset terminal connected to the output terminal of the third AND gate. It is used to receive the first trigger result output by the output terminal of the third AND gate and output a first detection signal according to the first trigger result.

[0093] The first jitter detection trigger unit 202 can be as follows: Figure 5 The jitter detection trigger shown includes a D input, an enable input CE, and an asynchronous preset input PRE. The D input of the jitter detection trigger is connected to a low level (0), the enable input CE is connected to the inverted signal of FSM_IS_IDLE, and the asynchronous preset input PRE is connected to the third AND gate 2022. FSM_IS_IDLE is a flag signal indicating that the state machine is currently in the IDLE state. Connecting the enable input CE to the inverted signal of FSM_IS_IDLE indicates that if the state machine is not currently in the IDLE state, this D trigger is enabled. When the state machine is not in the IDLE state, the output Q of the second trigger 3024 outputs 0, meaning that in other states, this jitter detection trigger 0 is reset.

[0094] When a measurement begins, the user initiates a start measurement command via software on the terminal. The state machine receives the start measurement command, i.e. Figure 2 When TMU_START is active, the state machine enters the IDLE state, FSM_IS_IDLE is active, and the enable terminal CE is inactive. At this time, the output of the jitter detection trigger is determined by the asynchronous preset terminal PRE. The asynchronous preset terminal PRE is connected to the third AND gate 2022. The first input of the third AND gate is used to receive the measured time signal TMU_SIGNAL, and the second input of the third AND gate is used to receive the preset state signal, i.e., the FSM_IS_IDLE signal.

[0095] The output of the third AND gate 2022 includes 1 or 0, and the second trigger 2024 determines the first detection signal JIT_DECT0 of the first jitter detection trigger unit based on the output.

[0096] In this embodiment, by connecting a third AND gate to the asynchronous preset terminal of the first jitter detection trigger unit, the first detection signal is determined based on the trigger result of the third AND gate.

[0097] In one embodiment, such as Figure 6 As shown, the second jitter detection trigger unit 204 includes a fourth AND gate 2042, a second NOT gate 2044, and a third trigger 2046.

[0098] The second NOT gate 2044 is used to receive the measured time signal and invert the measured time signal.

[0099] The fourth AND gate 2042 has its first input connected to the output of the second NOT gate, and its second input is used to receive the preset IDLE state signal.

[0100] The third flip-flop 2046 has its PRE terminal connected to the output terminal of the fourth AND gate, and is used to receive the second trigger result output by the output terminal of the fourth AND gate, and output a second detection signal according to the second trigger result.

[0101] The second motion detection trigger unit 204 can be as follows: Figure 6 The jitter detection trigger shown includes a D input, an enable input CE, and an asynchronous preset input PRE. The D input of the jitter detection trigger is connected to a low level, the enable input CE is connected to the inverted signal of FSM_IS_IDLE, and the asynchronous preset input PRE is connected to the fourth AND gate 2042. FSM_IS_IDLE is a flag signal indicating that the state machine is currently in the IDLE state. Connecting the enable input CE to the inverted signal of FSM_IS_IDLE indicates that if the state machine is currently not in the IDLE state, this D trigger is enabled. When the state machine is not in the IDLE state, the output Q of the third trigger 2046 outputs 0, meaning that in other states, this jitter detection trigger is reset.

[0102] When a measurement begins, the user initiates a start measurement command via software on the terminal. The state machine receives the start measurement command, i.e. Figure 2When TMU_START is active, the state machine enters the IDLE state, FSM_IS_IDLE is active, and the enable terminal CE is inactive. At this time, the output of the jitter detection trigger is determined by the asynchronous preset terminal PRE. The asynchronous preset terminal PRE is connected to the fourth AND gate 2042. The second NOT gate 2044 receives the measured time signal TMU_SIGNAL and inverts it; for example, if TMU_SIGNAL is low (input 0), it is inverted to 1. The first input of the third AND gate 2044 is connected to the output of the second NOT gate 2044, and the second input of the third AND gate 2044 receives the FSM_IS_IDLE signal.

[0103] The output of the fourth AND gate 2042 includes 1 or 0, and the third trigger 2046 determines the second detection signal JIT_DECT1 of the second jitter detection trigger unit based on the output.

[0104] In this embodiment, by connecting a fourth AND gate to the asynchronous preset terminal of the second jitter detection trigger unit, the second detection signal is determined based on the triggering result of the fourth AND gate.

[0105] In one embodiment, if the measured time signal is determined to be a jitter signal, the processing unit 206 is further configured to:

[0106] Obtain the filtered delay signal, and filter and delay the jitter signal based on the filtered delay signal to obtain the jitter end signal.

[0107] When the first and second detection signals determine that the current input time signal is jittering, the user can activate the filtering delay by setting the filtering time parameter through software. The filtering time parameter is set according to the characteristics of the input signal. If the input signal edge is relatively steep, the filtering time parameter can be set smaller; if the input signal edge is relatively gentle, the filtering time parameter can be set larger. After the state machine obtains the filtering delay signal, it jumps to the high-level filtering mode FILTER_HIGH or the low-level filtering mode FILTER_LOW to activate the filtering delay and wait for the signal jitter to end.

[0108] The first detection signal and the second detection signal of the jitter end signal are obtained based on the first jitter detection trigger unit and the second jitter detection trigger unit, and the initial state signal is output according to the first detection signal and the second detection signal.

[0109] Once the signal jitter ends, the initial state signal can be detected based on the signal after the jitter ends. By acquiring the first detection signal and the second detection signal of the jitter end signal, the initial state signal can be output based on the first detection signal and the second detection signal.

[0110] In this embodiment, when jitter is detected in the measured time signal, a filtering delay is initiated to wait for the jitter to end. The signal after the jitter ends can then be detected and an initial state signal can be output.

[0111] In one embodiment, such as Figure 7 As shown, the operating modes include a low-level sensitive mode and a high-level sensitive mode, and the initial state signal includes a high-level signal and a low-level signal; the filtering module 210 includes:

[0112] The high-level sensitive unit 212 is configured with a high-level sensitive mode, which is used to receive the measured time signal and the preset high-level sensitive mode signal, perform logical operations on the received signal, and output a first valid signal when the measured time signal is a high-level signal.

[0113] The high-level sensitive unit 212 includes a first AND gate 2122. The first input terminal of the first AND gate is used to receive the measured time signal, and the second input terminal of the first AND gate is used to receive the preset high-level sensitive mode signal, namely the FSM_IS_SEL_HIGH signal. The output terminal of the first AND gate is connected to the asynchronous preset terminal PRE.

[0114] The low-level sensitive unit 214 is configured with a low-level sensitive mode, which is used to receive the measured time signal and the preset low-level sensitive state signal, perform logical operations on the received signal, and output a second valid signal when the measured time signal is a low-level signal.

[0115] The low-level sensitive unit 214 includes a second AND gate 2142 and a first NOT gate 2144. The first NOT gate 2144 is used to invert the measured time signal. The first input terminal of the second AND gate 2142 is connected to the output terminal of the first NOT gate 2144. The second input terminal of the second AND gate 2142 is used to receive the preset low-level sensitive mode signal, i.e., the FSM_IS_SEL_LOW signal. The output terminal of the second AND gate 2142 is connected to the asynchronous clear terminal.

[0116] A first flip-flop 216 has its D terminal used to receive the initial state signal. The asynchronous preset terminal PRE of the first flip-flop is connected to the output terminal of the high-level sensitive unit and is used to receive the first valid signal. The asynchronous clear terminal CLR of the first flip-flop is connected to the output terminal of the low-level sensitive unit and is used to receive the second valid signal. The first flip-flop is used to perform jitter filtering on the measured time signal based on one of the first and second valid signals and the initial state signal to output a target time signal. The target time signal has the opposite level to the initial state signal.

[0117] The filtering module can be, for example, Figure 6 The D flip-flop shown includes a D input, an asynchronous preset input PRE, an asynchronous clear input CLR, and a Q output. The signal connected to the D input is the initial state signal INIT_ST of the measured time signal, and the output of the Q output is jointly determined by the asynchronous preset input PRE and the asynchronous clear input CLR.

[0118] The asynchronous preset terminal PRE is connected to the high-level sensitive unit 212. The high-level sensitive unit 212 includes a first AND gate 2122. The first input terminal of the first AND gate 2122 is used to receive the measured time signal TMU_SIGNAL. The second input terminal of the first AND gate is used to receive the preset high-level sensitive mode signal. The output terminal of the first AND gate is connected to the PRE terminal.

[0119] The asynchronous clear terminal CLR is connected to the low-level sensitive unit 214 and includes a second AND gate 2142 and a first NOT gate 2144. The first NOT gate 2144 is used to receive the measured time signal TMU_SIGNAL and invert the measured time signal. The first input terminal of the second AND gate 2142 is connected to the output terminal of the first NOT gate 2144, the second input terminal of the second AND gate 2142 is used to receive the preset low-level sensitive mode signal, and the output terminal of the second AND gate 2142 is connected to the CLR terminal.

[0120] When the initial state signal INIT_ST is low, the low-level signal is latched into the first flip-flop as INIT_ST. The state machine then jumps to the high-level sensitive mode SEL_HIGH. That is, the first flip-flop obtains the preset high-level sensitive mode signal and satisfies the condition of the second input terminal of the first AND gate. If the measured time signal becomes high, that is, both input terminals of the first AND gate 2122 are valid, then the first AND gate is valid and the output is 1. At this time, the condition of the second input terminal SEL_LOW of the second AND gate 2142 is not satisfied, so the second AND gate 2142 is invalid. The output result of the Q output terminal of the first flip-flop 216 is determined by the first AND gate 2122 of the asynchronous preset terminal, and the output is 1. That is, in the SEL_HIGH state, when the measured time signal becomes high, regardless of whether there is jitter, the Q output terminal of the first flip-flop 216 outputs a high level.

[0121] When the initial state signal INIT_ST is high, the high-level signal is latched into the first flip-flop as INIT_ST. The state machine jumps to the low-level sensitive mode SEL_LOW, that is, the filtering module obtains the preset low-level sensitive mode signal and satisfies the condition of the second input terminal of the second AND gate 2142. If the measured time signal becomes low, the output of the first input terminal of the second AND gate 2142 is 1 after inversion, that is, both input terminals are valid, so the second AND gate 2142 is valid and the output is 1. At this time, the condition of the second input terminal SEL_HIGH of the first AND gate 2122 is not satisfied, so the first AND gate 2122 is invalid. The output result of the Q output terminal of the first flip-flop 216 is determined by the second AND gate of the asynchronous clear terminal, and the output is 0. That is, in the SEL_LOW state, when the received measured time signal becomes low, regardless of whether there is jitter, the Q output terminal of the first flip-flop 216 will output low.

[0122] In this embodiment, by connecting the asynchronous preset terminal and the asynchronous clear terminal of the first flip-flop to the first AND gate and the second AND gate respectively, the filtering module is configured with a high-level sensitive unit and a low-level sensitive unit, which can filter and de-jitter the measured time signal based on the initial state signal and subsequent changes of the measured time signal.

[0123] In one embodiment, such as Figure 13 As shown, the preprocessing device further includes a first selection module 220, a time control module 230, a self-test module 240, and a second selection module 250.

[0124] The first selection module 220 is connected to the jitter detection module 200 and is used to determine the measured time signal and output the measured time signal to the jitter detection module 200.

[0125] In this process, the time signals from multiple channels can share a single preprocessing device. The first selection module is used to select the time signal to be measured from the time signals from multiple channels.

[0126] The time control module 230 is connected to the jitter detection module 200 and the filtering module 210, and is used to control the filtering time.

[0127] When it is necessary to filter and de-jitter the measured time signal, the user sets the filtering time in the software, and the time control module 230 controls the filtering time parameter through the state machine.

[0128] The self-test module 240 is used to output a self-test signal so that the time measurement unit can evaluate whether the time measurement unit is working properly.

[0129] Before measurement, a self-test signal can be generated by the self-test module 240, and the time measurement unit measures the period of the self-test signal to determine whether the time measurement unit is working properly.

[0130] The second selection module 250 is connected to the self-test module 240, the first selection module 220, and the filtering module 210, and is used to output one of the self-test signal, the target time signal, and the measured time signal to the time measurement unit.

[0131] The second selection module 250 is used to select the self-test signal and send the self-test signal to the time measurement unit when it is necessary to determine whether the time measurement unit is working properly; the second selection module 250 is also used to output the target time signal after filtering by the filtering module 210 or the non-jittering measured time signal selected by the first selection module 220 to the time measurement unit for time measurement.

[0132] In this embodiment, the time signal to be measured is determined from the time signals of multiple channels by the first selection module, which enables multiple channels to share a preprocessing device. The filtering time parameters are controlled by the time control module, making the operation flexible. The self-test module generates a self-test signal, which can avoid interference from system factors on time measurement and improve test efficiency and test accuracy.

[0133] In one embodiment, a time measurement system is provided; please refer to [reference needed]. Figure 1 It includes a conversion device 10, a preprocessing device 20, and a time measurement unit 30.

[0134] The conversion device 10 is used to acquire an external time signal and convert the external time signal into the time signal to be measured.

[0135] The aforementioned time signal preprocessing device 20 is used to perform jitter filtering on the measured time signal.

[0136] Among them, such as Figure 8 As shown, when the rising or falling edge of the external time signal acquired by the conversion device is relatively slow, the measured time signals CMPH and CMPL output by the comparator will have jitter, causing the time measurement unit to be unable to complete the measurement of the measured time signal. The preprocessing device can filter and de-jitter the measured time signal to obtain the de-jittered signals CMPH_FILTER and CMPL_FILTER, so that the time measurement unit can complete the measurement function.

[0137] The time measurement unit 30 is connected to the time signal preprocessing device and is used to measure the time signal after jitter filtering.

[0138] In this embodiment, an external time signal is acquired by a conversion device and converted into a time signal to be measured. A preprocessing device performs filtering and jitter removal on the time signal to be measured, so that the time measurement unit can measure the filtered and jitter-removed time signal to improve the effectiveness and accuracy of the measurement.

[0139] In one embodiment, such as Figure 9 As shown, a preprocessing method for time signals is provided, the method comprising:

[0140] Step 902: Receive the time signal to be measured and perform jitter detection on the time signal to be measured to output the initial state signal of the time signal to be measured.

[0141] The measured time signal is composed of, for example: Figure 5 and Figure 6 The D flip-flop shown receives and detects the initial state signal, which includes a non-jittering low-level signal and a non-jittering high-level signal.

[0142] Step 904: Receive the initial state signal, determine the working mode based on the initial state signal, and perform jitter filtering on the measured time signal according to the determined working mode.

[0143] As Figure 7 The D flip-flop shown receives the initial state signal and latches it. The state machine jumps to the corresponding working mode according to the initial state signal and performs jitter filtering on the measured time signal based on subsequent changes in the measured time signal.

[0144] In this embodiment, by performing jitter detection on the measured time signal to determine the initial state signal of the measured time signal, and performing jitter filtering processing on the measured time signal based on the initial state signal, the time signal is filtered and jitter-reduced before entering the time measurement unit, thereby successfully completing the time measurement and improving the effectiveness of the measurement.

[0145] In one embodiment, such as Figure 10 As shown, the operating mode includes a high-level sensitive mode, and the initial state signal includes a low-level signal; the step of receiving the initial state signal, determining the operating mode based on the initial state signal, and performing jitter filtering on the measured time signal based on the determined operating mode includes steps 1002-1004.

[0146] Step 1002: When the received initial state signal is a low-level signal, configure a high-level sensitive mode, receive the measured time signal and the preset high-level sensitive mode signal, perform logical operations on the received signal, and output a first valid signal when the measured time signal is high.

[0147] When the initial state signal is a low-level signal, the state machine jumps to the high-level sensitive mode. When a high level is detected, that is, both inputs of the first AND gate are valid, the first AND gate is valid and the output of the first AND gate is 1.

[0148] Step 1004: Perform jitter filtering on the measured time signal based on the first valid signal and the initial state signal to output a target time signal, wherein the level of the target time signal is opposite to that of the initial state signal.

[0149] When the initial state signal is low and a high level is detected in the high-level sensitive state, the state machine jumps to the high-level filtering mode. At this time, the IDLECNT_END terminal of the filtering module is valid. The user sets the filtering time parameter through software. The state machine performs filtering and delay processing on the current signal according to the filtering time parameter, waiting for the jitter to end so that the jitter of the signal does not affect the output of the first flip-flop. Then, the first flip-flop outputs the target time signal with a high level according to the first valid signal of the first AND gate.

[0150] In this embodiment, by switching to a high-level sensitive mode when the initial state signal is low, the effect of filtering and de-jittering the measured time signal based on the output signal of the first AND gate is achieved, and a high level is output.

[0151] In one embodiment, such as Figure 11As shown, the operating mode also includes a low-level sensitive mode, and the initial state signal also includes a high-level signal; the step of receiving the initial state signal, determining the operating mode of the filtering module based on the initial state signal, and performing jitter filtering processing on the measured time signal based on the determined operating mode includes steps 1102-1104.

[0152] Step 1102: When the received initial state signal is a high-level signal, configure a low-level sensitive mode, receive the measured time signal and the preset low-level sensitive mode signal, perform logical operations on the received signal, and output a second valid signal when the measured time signal is low.

[0153] When the initial state signal is a high-level signal, the state machine jumps to the low-level sensitive mode. When a low level is detected, that is, both inputs of the second AND gate are valid, the second AND gate is valid and the output of the second AND gate is 1.

[0154] Step 1104: Perform jitter filtering on the measured time signal based on the second valid signal and the initial state signal to output a target time signal, wherein the level of the target time signal is opposite to that of the initial state signal.

[0155] When the initial state signal is high and a low level is detected in the low-level sensitive mode, the IDLECNT_END terminal of the filtering module is valid. The user sets the filtering time parameter through software. The state machine performs filtering and delay processing on the current signal according to the filtering time parameter, waiting for the jitter to end so that the jitter of the signal does not affect the output of the first flip-flop. Then, the first flip-flop outputs the target time signal with a low level according to the second signal output of the second gate.

[0156] In this embodiment, by switching to a low-level sensitive mode when the initial state signal is high, the effect of filtering and de-jittering the measured time signal based on the output signal of the second gate is achieved, resulting in a low-level output.

[0157] In one embodiment, such as Figure 12 As shown, the step of receiving the measured time signal and performing jitter detection on the measured time signal to output the initial state signal of the measured time signal includes steps 1202-1208.

[0158] Step 1202: Receive the measured time signal and output a first detection signal based on the first triggering result of the first jitter detection triggering unit according to the measured time signal.

[0159] Among them, through such Figure 5 The jitter detection trigger 0 shown detects the time signal being measured and outputs the first detection signal.

[0160] Step 1204: Receive the measured time signal and output a second detection signal based on the second triggering result of the second jitter detection triggering unit according to the measured time signal.

[0161] Among them, through such Figure 6 The jitter detection trigger 1 shown detects the time signal being measured and outputs a second detection signal.

[0162] Step 1206: Determine whether the measured time signal is jittering based on the first detection signal and the second detection signal, so as to output the initial state signal.

[0163] The processing unit determines whether the initial state signal of the measured time signal is high or low based on the first detection signal and the second detection signal.

[0164] In this embodiment, by acquiring the first detection signal and the second detection signal of the time signal being measured, the initial state signal of the time signal being measured can be determined based on the first detection signal and the second detection signal.

[0165] In one embodiment, after performing jitter filtering on the measured time signal based on the first valid signal and the initial state signal to output a target time signal, and after performing jitter filtering on the measured time signal based on the second valid signal and the initial state signal to output a target time signal, the method further includes:

[0166] Enter the inverse sensitive mode of the output target time signal to complete the subsequent jitter filtering processing of the measured time signal.

[0167] For example, if it is in a high-level sensitive delay state, it will switch to a low-level sensitive mode after the filtering delay is completed; if it is in a low-level sensitive delay state, it will switch to a high-level sensitive mode after the filtering delay is completed, thereby completing the jitter filtering of the measured time signal based on FPGA.

[0168] In this embodiment, by switching to the inverse sensitive state after filtering is completed, subsequent jitter filtering processing of the measured time signal can be achieved.

[0169] In one embodiment, such as Figure 13 As shown, before receiving the measured time signal and performing jitter detection on the measured time signal to output the initial state signal of the measured time signal, the method further includes:

[0170] Determine whether the measured time signal is jittering. If the measured time signal is determined to be free of jitter, then output the measured time signal to the time measurement unit.

[0171] Before testing, a self-test signal is sent to the time measurement unit via the self-test module TEST_GEN to determine if the time measurement unit is in a normal state. If the time measurement unit is normal, a test time signal TMU_SIGNAL is selected from the multiple channels CMPH0-CMPH15 and CMPL0-CMPL15 output by the comparator via the first selection module 220 FIRST_SEL. If the software directly determines that the test time signal has no jitter, the test time signal TMU_SIGNAL is directly output to the time measurement unit. If it is uncertain whether the test time signal TMU_SIGNAL has jitter, it is sent to SIGNAL_FILTER for jitter detection by the jitter detection module. The user controls the jitter detection via the time control module 230. FILTER_TIME_CTRL controls the filtering time parameter. Different filtering time parameters can be set for different signal edge conditions to achieve the measurement of all signals in multiple channels. The filtering module performs jitter filtering on the measured time signal to obtain the filtered and jitter-free signal POST_TMU_SIGNAL.

[0172] In this embodiment, by pre-determining whether the time signal being measured is jittering, if it is not jittering, it is directly output to the time measurement unit for measurement, which can simplify the testing process and improve preprocessing efficiency.

[0173] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 14 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a time signal preprocessing method. The display screen can be an LCD screen or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0174] Those skilled in the art will understand that Figure 14 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0175] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of any of the aforementioned time signal preprocessing methods.

[0176] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the aforementioned time signal preprocessing methods.

[0177] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the aforementioned time signal preprocessing methods.

[0178] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0179] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0180] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A preprocessing device for time signals, characterized in that, include: The jitter detection module is used to receive the measured time signal and perform jitter detection on the measured time signal to output the initial state signal of the measured time signal; A filtering module, connected to the jitter detection module, is used to receive the initial state signal, determine the working mode of the filtering module according to the initial state signal, and perform jitter filtering processing on the measured time signal according to the determined working mode. The operating mode includes a high-level sensitive mode, and the initial state signal includes a low-level signal; the filtering module includes: The high-level sensitive unit is configured with a high-level sensitive mode, which is used to receive the measured time signal and a preset high-level sensitive state signal, perform logical operations on the received signal, and output a first valid signal when the measured time signal is a high-level signal; The first flip-flop has its D terminal used to receive the initial state signal. The asynchronous preset terminal of the first flip-flop is connected to the output terminal of the high-level sensitive unit and is used to receive the first valid signal. The first flip-flop is used to perform jitter filtering on the measured time signal according to the first valid signal and the initial state signal to output a target time signal. The target time signal has the opposite level to the initial state signal.

2. The pretreatment apparatus according to claim 1, characterized in that, The operating mode also includes a low-level sensitive mode, and the initial state signal also includes a high-level signal; the filtering module also includes: The low-level sensitive unit is configured with a low-level sensitive mode, which is used to receive the measured time signal and a preset low-level sensitive state signal, perform logical operations on the received signal, and output a second valid signal when the measured time signal is a low-level signal. The asynchronous clear terminal of the first flip-flop is connected to the output terminal of the low-level sensitive unit to receive the second valid signal. The first flip-flop is also used to perform jitter filtering on the measured time signal according to the second valid signal and the initial state signal to output a target time signal, the target time signal being opposite in level to the initial state signal.

3. The pretreatment apparatus according to claim 1, characterized in that, The high-level sensitive unit includes: The first AND gate has its first input terminal used to receive the measured time signal, its second input terminal used to receive the preset high-level sensitive state signal, and its output terminal connected to the asynchronous preset terminal.

4. The pretreatment apparatus according to claim 2, characterized in that, The low-level sensitive unit includes: The first NOT gate, whose input is used to receive the measured time signal and invert the measured time signal; The second AND gate has its first input connected to the output of the first NOT gate, its second input used to receive the preset low-level sensitive state signal, and its output connected to the asynchronous clear terminal.

5. The pretreatment apparatus according to claim 2, characterized in that, The jitter detection module includes: The first jitter detection trigger unit is used to receive the measured time signal and output a first detection signal according to the measured time signal and a preset state signal; The second jitter detection trigger unit is used to receive the measured time signal and output a second detection signal according to the measured time signal and a preset state signal; The processing unit is connected to the first jitter detection trigger unit and the second jitter detection trigger unit respectively, and is used to determine whether the measured time signal jitters according to the first detection signal and the second detection signal, and output the initial state signal.

6. The pretreatment apparatus according to claim 5, characterized in that, The first jitter detection trigger unit includes: The third AND gate has a first input terminal for receiving the measured time signal and a second input terminal for receiving the preset state signal. The second flip-flop has its asynchronous preset terminal connected to the output terminal of the third AND gate, and is used to receive the first trigger result output by the output terminal of the third AND gate, and output a first detection signal according to the first trigger result.

7. The pretreatment apparatus according to claim 5, characterized in that, The second jitter detection trigger unit includes: The second NOT gate is used to receive the measured time signal and invert the measured time signal. The fourth AND gate, wherein the first input terminal of the fourth AND gate is connected to the output terminal of the second NOT gate, and the second input terminal of the fourth AND gate is used to receive the preset state signal; The third flip-flop has its asynchronous preset terminal connected to the output terminal of the fourth AND gate, and is used to receive the second triggering result output by the output terminal of the fourth AND gate, and output a second detection signal according to the second triggering result.

8. The pretreatment apparatus according to claim 5, characterized in that, The first detection signal and the second detection signal are either low-level signals or high-level signals, wherein the processing unit is further configured to: If the first detection signal output is a high-level signal and the second detection signal output is a low-level signal, then the initial state signal output is a non-jittering high-level signal; If the first detection signal output is a low-level signal and the second detection signal output is a high-level signal, then the initial state signal output is a non-jittering low-level signal; If the first detection signal output is a high-level signal and the second detection signal output is a high-level signal, then the measured time signal is determined to be a jitter signal.

9. The pretreatment apparatus according to claim 8, characterized in that, If the measured time signal is determined to be a jitter signal, the processing unit is further configured to: Obtain the filtered delay signal, and filter and delay the jitter signal based on the filtered delay signal to obtain the jitter end signal; The first detection signal and the second detection signal of the jitter end signal are obtained based on the first jitter detection trigger unit and the second jitter detection trigger unit, and the initial state signal is output according to the first detection signal and the second detection signal.

10. The pretreatment apparatus according to claim 1, characterized in that, Also includes: The first selection module is connected to the jitter detection module and is used to determine the measured time signal and output the measured time signal to the jitter detection module. A time control module, connected to the jitter detection module and the filtering module, is used to control the filtering time; The self-test module is used to output a self-test signal so that the time measurement unit can evaluate whether the time measurement unit is working properly. The second selection module is connected to the self-test module, the first selection module, and the filtering module, and is used to output one of the self-test signal, the target time signal, and the measured time signal to the time measurement unit.

11. A time measurement system, characterized in that, include: A conversion device is used to acquire an external time signal and convert the external time signal into the measured time signal; The time signal preprocessing apparatus as described in any one of claims 1-10 is used to perform jitter filtering processing on the measured time signal; The time measurement unit is connected to the time signal preprocessing device and is used to measure the time signal after jitter filtering.

12. A method for preprocessing time signals, characterized in that, The method includes: Receive the time signal to be measured, and perform jitter detection on the time signal to be measured, so as to output the initial state signal of the time signal to be measured; The system receives the initial state signal, determines the working mode based on the initial state signal, and performs jitter filtering on the measured time signal based on the determined working mode. The initial state signal includes a low-level signal; the process of receiving the initial state signal, determining the operating mode based on the initial state signal, and performing jitter filtering on the measured time signal based on the determined operating mode includes: When the received initial state signal is a low-level signal, the working mode is determined to be a high-level sensitive mode. The measured time signal and the preset high-level sensitive mode signal are received, and logical operations are performed on the received signals. When the measured time signal is high, the first valid signal is output. The measured time signal is subjected to jitter filtering based on the first valid signal and the initial state signal to output a target time signal, the target time signal having the opposite level to the initial state signal.

13. The method according to claim 12, characterized in that, The initial state signal further includes a high-level signal; the step of receiving the initial state signal, determining the operating mode based on the initial state signal, and performing jitter filtering processing on the measured time signal based on the determined operating mode includes: When the received initial state signal is a high-level signal, the working mode is determined to be a low-level sensitive mode. The measured time signal and the preset low-level sensitive mode signal are received, and logical operations are performed on the received signals. When the measured time signal is low, a second valid signal is output. The measured time signal is subjected to jitter filtering based on the second valid signal and the initial state signal to output a target time signal, the target time signal having the opposite level to the initial state signal.

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