Semiconductor element with redistribution structure and method for manufacturing the same

Abstract

A semiconductor device includes a first chip and a second chip on the first chip. The first chip includes a first substrate including a central region and a surrounding region surrounding the central region, a first central bonding pad over the central region of the first substrate, and a first surrounding bonding pad over the surrounding region of the first substrate. The second chip includes a plurality of surrounding higher bonding pads on a surrounding region of the second chip and respectively over the first central bonding pad and the first surrounding bonding pad, a plurality of redistribution structures respectively on the surrounding higher bonding pads and extending toward a central region of the second chip, a plurality of central lower bonding pads on the central region of the second chip and respectively on the redistribution structures, and a plurality of memory cells electrically coupled to the central lower bonding pads.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Patent Application No. 17 / 550,317 (i.e., priority date of “December 14, 2021”), the contents of which are incorporated herein in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device having a redistribution structure and a method of fabricating the same. BACKGROUND

[0003] Semiconductor devices have been used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. The size of semiconductor devices continues to shrink to meet the demand for increasing computing power. However, various problems arise during the shrinking process, and these problems continue to increase. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reduced complexity.

[0004] The above “background” description is for the purpose of generally presenting the context of the disclosure. The above “background” description is not, and should not be interpreted to be, art-acknowledging or art- establishing for what the present disclosure is, the present disclosure achieves every challenge it is “background” to solve, and each and every “background” statement recited above should not be interpreted to be an admission of any kind of suggestion that this application is in the prior art. SUMMARY

[0005] One aspect of the present disclosure provides a semiconductor device, comprising: a first chip comprising: a first middle dielectric layer on a first substrate; a plug structure in the first middle dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer on the first middle dielectric layer and away from the plug structure; a first lower bonding pad on the first redistribution layer; and a second lower bonding pad on the plug structure. The semiconductor device further comprises a second chip on the first chip, comprising: a first higher bonding pad on the first lower bonding pad; a second higher bonding pad on the second lower bonding pad; and a plurality of memory units electrically coupled to the first higher bonding pad and the second higher bonding pad.

[0006] In some embodiments, the first chip is configured as a logic chip and the second chip is configured as a memory chip.

[0007] In some embodiments, the plug structure comprises a bottom plug on the first substrate, a landing pad on the bottom plug, and a top plug between the landing pad and the second lower bonding pad.

[0008] In some embodiments, the semiconductor device comprises a first barrier layer between the top plug and the second lower bonding pad.

[0009] In some embodiments, the semiconductor element includes a second barrier layer between the landing pad and the top plug.

[0010] In some embodiments, the semiconductor element includes a third barrier layer between the top plug and the second lower bonding pad, and a fourth barrier layer between the first lower bonding pad and the first redistribution layer.

[0011] In some embodiments, a bottom surface of the third barrier layer is at a vertical level lower than a top surface of the first redistribution layer.

[0012] In some embodiments, a width of the first chip and a width of the second chip are substantially the same.

[0013] In some embodiments, the bottom plug includes aluminum, copper, or a combination thereof, and the top plug includes tungsten.

[0014] In some embodiments, the third barrier layer includes titanium and titanium nitride.

[0015] In some embodiments, the memory cells are configured as a capacitor array or a floating array.

[0016] Another aspect of the present disclosure provides a semiconductor element, including: a first chip including: a first substrate including a central region and a surrounding region surrounding the central region; a first central bonding pad over the central region of the first substrate; and a first surrounding bonding pad over the surrounding region of the first substrate. The semiconductor element further includes a second chip over the first chip, including: a plurality of surrounding higher bonding pads over a surrounding region of the second chip and respectively over the first central bonding pad and the first surrounding bonding pad; a plurality of redistribution structures respectively over the surrounding higher bonding pads and extending toward a central region of the second chip; a plurality of central lower bonding pads over the central region of the second chip and respectively over the redistribution structures; and a plurality of memory cells electrically coupled to the central lower bonding pads.

[0017] In some embodiments, the redistribution structures include: a plurality of redistribution layers respectively over the surrounding higher bonding pads and respectively extending from the surrounding region of the second chip toward the central region of the second chip; and a plurality of redistribution plugs over the central region of the second chip and respectively and correspondingly between the central lower bonding pads and the redistribution layers.

[0018] In some embodiments, the semiconductor element includes a plurality of first support plugs respectively located on the redistribution layer, wherein the first support plugs are away from the redistribution plugs and the first support plugs are floating.

[0019] In some embodiments, the semiconductor element includes a plurality of second support plugs respectively located on the redistribution layer, wherein the second support plugs are away from the first support plugs and the second support plugs are floating.

[0020] In some embodiments, a distance between an adjacent pair of the redistribution plug and the first support plug is substantially the same as a distance between an adjacent pair of the first support plug and the second support plug.

[0021] In some embodiments, the semiconductor element includes a molding layer located on the first chip and covering the second chip.

[0022] Another aspect of the present disclosure provides a method of manufacturing a semiconductor element, including: providing a first substrate including a functional unit; forming a plug structure on the first substrate and electrically coupled to the functional unit; forming a first redistribution layer above the first substrate; forming a first lower bonding pad on the first redistribution layer; forming a second lower bonding pad on the plug structure, wherein the first substrate, the plug structure, the first redistribution layer, the first lower bonding pad, and the second lower bonding pad together constitute a first chip; and bonding a second chip to the first chip. The second chip includes a first higher bonding pad bonded to the first lower bonding pad, a second higher bonding pad bonded to the second lower bonding pad, and a plurality of memory units electrically coupled to the first higher bonding pad and the second higher bonding pad.

[0023] In some embodiments, the first chip is configured as a logic chip and the second chip is configured as a memory chip, and the memory units are configured as a capacitor array or a floating array.

[0024] In some embodiments, the plug structure includes a bottom plug formed on the first substrate, a landing pad formed on the bottom plug, and a top plug formed on the landing pad.

[0025] Due to the design of the semiconductor element of the present disclosure, data signals can be transmitted through the first higher bonding pad, the first lower bonding pad, and the first redistribution layer without passing through the conductive components of the first chip, the plug structure, and the functional unit. As a result, the transmission distance can be reduced, and thus the performance of the semiconductor element can be improved. In addition, since the transmission distance is short, the power consumption of the semiconductor element can be reduced.

[0026] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features will be described in the description that follows, and conclusions can be drawn from the description, the novel teachings of the present disclosure will be elucidated in the detailed description that follows. Those skilled in the art will appreciate that they can readily use the conception(s) and the specific embodiment(s) disclosed in the following description to modify or design other structures and methods without departing from the spirit and scope of the present disclosure. It is therefore intended that the present disclosure be considered as in all respects as illustrative and not restrictive, and that reference be made to the appended claims rather than to the foregoing description to determine the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0027] The various features of the present disclosure can be better understood by reading the above description in conjunction with the accompanying drawings as follows. It is emphasized that, according to the standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0028] Figure 1 A method for fabricating a semiconductor device is shown in the form of a flow chart according to an embodiment of the present disclosure.

[0029] Figures 2 to 8 A fabrication process for a semiconductor device is shown in a cross-sectional schematic view according to an embodiment of the present disclosure.

[0030] Figures 9 to 11 A semiconductor device is shown in a cross-sectional schematic view according to some embodiments of the present disclosure.

[0031] Figure 12 A method for fabricating a semiconductor device is shown in the form of a flow chart according to another embodiment of the present disclosure.

[0032] Figure 13 A portion of a fabrication process for a semiconductor device is shown in a top view schematic according to another embodiment of the present disclosure.

[0033] Figure 14 is a cross-sectional schematic view taken along Figure 13 the centerline A-A'.

[0034] Figure 15 A portion of a fabrication process for a semiconductor device is shown in a top view schematic according to another embodiment of the present disclosure.

[0035] Figure 16 is a cross-sectional schematic view taken along Figure 15 the centerline A-A'.

[0036] Figure 17 A portion of a fabrication process for a semiconductor device is shown in a top view schematic according to another embodiment of the present disclosure.

[0037] Figure 18is a cross-sectional view taken along Figure 17 A-A' is a cross-sectional view taken along

[0038] Figure 19 According to another embodiment of the present disclosure, a portion of a fabrication flow of a semiconductor element is shown in a top view schematic.

[0039] Figure 20 is a cross-sectional view taken along Figure 19 A-A' is a cross-sectional view taken along

[0040] Figures 21 to 23 According to another embodiment of the present disclosure, a portion of a fabrication flow of a semiconductor element is shown in a cross-sectional view schematic.

[0041] wherein the reference signs are explained as follows:

[0042] 1A: semiconductor element

[0043] 1B: semiconductor element

[0044] 1C: semiconductor element

[0045] 1D: semiconductor element

[0046] 1E: semiconductor element

[0047] 10: fabrication method

[0048] 20: fabrication method

[0049] 100: first chip

[0050] 100FS: front surface

[0051] 111: first substrate

[0052] 113: first intermediate dielectric layer

[0053] 115: bottom dielectric layer

[0054] 117: top dielectric layer

[0055] 121: plug structure

[0056] 123: bottom plug

[0057] 125: landing pad

[0058] 127: top plug

[0059] 131: first redistribution layer

[0060] 131TS: top surface

[0061] 131BS: bottom surface

[0062] 141: first bottom passivation layer

[0063] 143: first top passivation layer

[0064] 145: spacer opening

[0065] 147: spacer opening

[0066] 151: first lower bonding pad

[0067] 153: second lower bonding pad

[0068] 155: protrusion

[0069] 161: first barrier layer

[0070] 163: second barrier layer

[0071] 165: third barrier layer

[0072] 165-1: U-shaped protrusion

[0073] 165BS: bottom surface

[0074] 167: fourth barrier layer

[0075] 200: second chip

[0076] 200FS: front surface

[0077] 211: second substrate

[0078] 213: second intermediate dielectric layer

[0079] 221: memory cell

[0080] 231: second top passivation layer

[0081] 241: first higher bonding pad

[0082] 243: second higher bonding pad

[0083] 300: third chip

[0084] 311: third substrate

[0085] 313: third bottom intermediate dielectric layer

[0086] 315: interconnect layer

[0087] 317: third top intermediate dielectric layer

[0088] 321: memory cell

[0089] 331: third bottom passivation layer

[0090] 333: third top passivation layer

[0091] 341: central lower bonding pad

[0092] 343: peripheral higher bonding pad

[0093] 351: redistribution structure

[0094] 353: redistribution plug

[0095] 355: second redistribution layer

[0096] 361: first support plug

[0097] 363: second support plug

[0098] 400: fourth chip

[0099] 500: fifth chip

[0100] 511: fifth substrate

[0101] 513: fifth intermediate dielectric layer

[0102] 533: fifth top passivation layer

[0103] 541: fifth central bonding pad

[0104] 543: fifth peripheral bonding pad

[0105] 611: molding layer

[0106] CR1: central region

[0107] CR2: central region

[0108] D1: distance

[0109] D2: distance

[0110] PL1: peripheral region

[0111] PL2: peripheral region

[0112] S11: step

[0113] S13: step

[0114] S15: step

[0115] S17: step

[0116] S19: step

[0117] S21: step

[0118] S23: step

[0119] S25: step

[0120] S27: step

[0121] S29: step

[0122] S31: step

[0123] VL1: vertical horizontal

[0124] W1: width

[0125] W2: width

[0126] W3: width

[0127] W4: width

[0128] W5: width

[0129] W6: width

[0130] W7: width

[0131] X: direction

[0132] Y: direction

[0133] Z: direction DETAILED DESCRIPTION

[0134] The following disclosure provides many different embodiments, or examples, for implementing different components of the present disclosure. Each of the following examples can be implemented in any of the several embodiments or examples of the present disclosure. In the following description, for purposes of explanation, specific details are set forth to provide a thorough understanding of embodiments of the present disclosure. However, it will be apparent to one skilled in the art that these specific details are not required in every case, and that claim should not be limited to the specific details presented.

[0135] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0136] It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers can be present.

[0137] It should be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element, and, similarly, a second element discussed below could be termed a first element without departing from the teachings of the present disclosure.

[0138] Unless context dictates otherwise, use herein of the word "about" to modify a dimension, layout, position, shape, size, quantity, or other measure is not intended to be limiting in any way. Rather, such use is intended to encompass variations in the dimension, layout, position, shape, size, quantity, or other measure that are within acceptable ranges due to, for example, manufacturing processes. Such variations are intended to be within the scope of the present disclosure. The word "substantially" can be used herein to reflect this intended meaning. For example, items described as "substantially identical," "substantially equivalent," or "substantially planar" can be identical, equivalent, or planar, or can be within acceptable ranges of being identical, equivalent, or planar due to, for example, manufacturing processes.

[0139] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing a semiconductor property, and an electro-optical element, a light-emitting display element, a semiconductor circuit, and an electronic element are included in the category of semiconductor elements.

[0140] It should be noted that in the description of the present disclosure, above or up corresponds to the arrow direction of the direction Z, and below or down corresponds to the arrow direction opposite to the direction Z.

[0141] It should be noted that the words "forming," "formed," and "form" can mean and include any method of creating, building, patterning, implanting, or depositing an element, dopant, or material. Examples of forming methods can include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

[0142] It should be noted that in the description of the present disclosure, the functions or steps mentioned herein can occur in a different order than mentioned in the figures. For example, two figures shown in succession can actually be performed at substantially the same time or sometimes in reverse order depending on the functions or steps involved.

[0143] Figure 1 A method 10 of fabricating a semiconductor element 1A is shown in the form of a flowchart according to an embodiment of the present disclosure. Figures 2 to 8 A fabrication flow of a semiconductor element 1A is shown in the form of a cross-sectional schematic diagram according to an embodiment of the present disclosure.

[0144] Referring to Figures 1 to 4 At step S11, a first substrate 111 can be provided, a first redistribution layer 131 can be formed over the first substrate 111, and a plug structure 121 can be formed on the first substrate 111.

[0145] Referring to Figure 2 In some embodiments, the first substrate 111 can include a bulk semiconductor substrate composed entirely of at least one semiconductor material, a plurality of element members (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive components (not shown for clarity). The bulk semiconductor substrate can include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations of the foregoing.

[0146] In some embodiments, the first substrate 111 can further comprise a semiconductor-on-insulator structure comprising, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer can comprise the same materials as the bulk semiconductor substrate described above. The insulating layer can be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer can be a dielectric oxide, such as silicon oxide. For another example, the insulating layer can be a dielectric nitride, such as silicon nitride or boron nitride. For yet another example, the insulating layer can comprise a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer can have a thickness between about 10 nm and about 200 nm.

[0147] It should be noted that the word "about" when used in the recitations of the present disclosure to modify the amount of a component, a constituent, or a reactant employed in the present disclosure means, for example, an amount that can vary due to typical measuring and liquid handling procedures used in preparing a concentrated solution or a solution. In addition, variations can occur due to differences in the manufacture, source, or purity of the ingredients employed in the compositions or methods. In one aspect, the word "about" means within 10% of the reported value. In another aspect, the word "about" means within 5% of the reported value. In yet another aspect, the word "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0148] A plurality of element structures can be formed on the first substrate 111. Some portions of the element structures can be formed in the first substrate 111. The element structures can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, finfield-effect-transistors, the like, or a combination thereof.

[0149] The dielectric layer can be formed on the first substrate 111 and cover the element members. In some embodiments, the dielectric layer can include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, similar materials thereof, or combinations of the foregoing. The low-k dielectric materials can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric materials can have a dielectric constant less than 2.0. Fabrication techniques for the dielectric layer can include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. Planarization processes can be performed after deposition processes to remove excess material and provide a substantially planar surface for subsequent process steps.

[0150] The conductive components can include interconnect layers, conductive vias, and conductive pads. The interconnect layers can be separated from one another and can be horizontally disposed in the dielectric layer along the direction Z. In the present embodiment, the topmost interconnect layer can be designated as a conductive pad. The conductive vias can connect adjacent interconnect layers along the direction Z, adjacent element members and interconnect layers, and adjacent conductive pads and interconnect layers. In some embodiments, the conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the conductive components can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations of the foregoing. The conductive components can be formed during formation of the dielectric layer.

[0151] The element members and the conductive components can together form a functional unit. In the present disclosure, a functional unit generally refers to functionally related circuitry that is divided into different units for functional purposes. In some embodiments, a functional unit can generally be a highly complex circuit, such as a processor core or an accelerator unit. In some other embodiments, the complexity and functionality of a functional unit can be more or less complex.

[0152] Reference is made to Figure 2A bottom dielectric layer 115 can be formed on the first substrate 111. In some embodiments, the bottom dielectric layer 115 can include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, similar materials thereof, or combinations of the foregoing. Fabrication techniques of the bottom dielectric layer 115 can include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. A planarization process can be performed after the deposition process to remove excess material and provide a substantially planar surface for subsequent process steps.

[0153] Referring to Figure 2 The bottom plug 123 can be formed along the bottom dielectric layer 115 and electrically coupled to a corresponding component in the first substrate 111. In other words, the bottom plug 123 can be associated with a functional unit in the first substrate 111. In some embodiments, the bottom plug 123 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or combinations of the foregoing. In the present embodiment, the bottom plug 123 can include an alloy of aluminum and copper.

[0154] Referring to Figure 2 A landing pad 125 can be formed on the bottom plug 123. The width W2 of the landing pad 125 can be greater than the width Wl of the bottom plug 123. In some embodiments, the landing pad 125 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or combinations of the foregoing. In some embodiments, fabrication techniques of the landing pad 125 can include performing a blanket deposition process followed by a patterning and etching process.

[0155] Referring to Figure 3 A top dielectric layer 117 can be formed on the bottom dielectric layer 115 and covering the landing pad 125. The top dielectric layer 117 can include the same material as the bottom dielectric layer 115, the description of which is not repeated here. Fabrication techniques of the top dielectric layer 117 can include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. A planarization process can be performed after the deposition process to remove excess material and provide a substantially planar surface for subsequent process steps. The bottom dielectric layer 115 and the top dielectric layer 117 can together constitute a first inter-dielectric layer 113.

[0156] Referring to Figure 3A first redistribution layer 131 can be formed on the first intermediate dielectric layer 113. In some embodiments, the first redistribution layer 131 can be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination of the foregoing. In some embodiments, the first redistribution layer 131 can be formed using a blanket deposition process followed by a patterning and etching process. It should be noted that the first redistribution layer 131 is not electrically coupled to any functional unit in the first substrate 111.

[0157] Referring to Figure 4 A first bottom passivation layer 141 can be formed on the first intermediate dielectric layer 113 and covering the first redistribution layer 131. In some embodiments, the first bottom passivation layer 141 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, carbon silicon nitride, similar materials thereof, or a combination of the foregoing. In some embodiments, the bottom passivation layer 141 can include, for example, a polymer layer including polyimide, polybenzoxazole, benzocyclobutene, epoxy, silicone, acrylate s, nano-filled phenoresin, siloxane, fluorinated polymer, polynorbornene, or similar materials thereof. A planarization process can be performed until the top surface 131TS of the first redistribution layer 131 is exposed to remove excess material and provide a substantially planar surface for subsequent processing steps.

[0158] It should be noted that, in the description of the present disclosure, the surface of an element (or component) at the highest vertical level along the direction Z is referred to as the top surface of the element (or component). The surface of an element (or component) at the lowest vertical level along the direction Z is referred to as the bottom surface of the element (or component).

[0159] Referring to Figure 4The top plug 127 can extend along the first bottom passivation layer 141 to the top dielectric layer 117 and formed on the landing pad 125. The width W3 of the top plug 127 can be greater than the width Wl of the bottom plug 123. The width W3 of the top plug 127 can be less than the width W2 of the landing pad 125. In some embodiments, the top plug 127 can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination of the foregoing. A masking layer (not shown for clarity) that masks the first redistribution layer 131 can be used to perform a patterning process to form a plug opening (not shown for clarity) to expose a portion of the landing pad 125. A subsequent deposition process can be performed to deposit the above-mentioned material to fill the plug opening. A planarization process can be performed until the top surface 131TS of the first redistribution layer 131 is exposed to remove excess material while forming the top plug 127. In the present embodiment, the top plug 127 can include tungsten.

[0160] The bottom plug 123, the landing pad 125, and the top plug 127 can together constitute a plug structure 121. The plug structure 121 can be electrically coupled to a corresponding functional unit in the first substrate 111. In other words, the plug structure 121 can be associated with a functional unit in the first substrate 111.

[0161] Referring to Figure 1 , Figure 5 , and Figure 6 , at step S13, a first lower bonding pad 151 can be formed on the first redistribution layer 131, and a second lower bonding pad 153 can be formed on the plug structure 121, where the first substrate 111, the plug structure 121, the first redistribution layer 131, the first lower bonding pad 151, and the second lower bonding pad 153 together constitute the first chip 100.

[0162] Referring to Figure 5A first top passivation layer 143 can be formed on the first bottom passivation layer 141. In some embodiments, the first top passivation layer 143 can include a material such as polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, solder resist film, or the like. Polymeric materials such as polyimide can have many attractive properties such as the ability to fill high aspect ratio openings, a relatively low dielectric constant (about 3.2), a simple deposition process, reduced sharp features or steps in the underlying layer, and high temperature resistance after curing. In some embodiments, the first top passivation layer 143 can be formed using a technique such as spin coating, lamination, deposition, or the like. The deposition can include chemical vapor deposition such as plasma enhanced chemical vapor deposition. The process temperature for the plasma enhanced chemical vapor deposition can be between about 350 °C and about 450 °C. The process pressure for the plasma enhanced chemical vapor deposition can be between about 2.0 Torr and about 2.8 Torr. The process duration for the plasma enhanced chemical vapor deposition can be between about 8 seconds and about 12 seconds.

[0163] Referring to Figure 5 In some embodiments, a plurality of pad openings 145, 147 can be formed through the first top passivation layer 143. The first redistribution layer 131 can be exposed through the pad openings 145, and the top plug 127 can be exposed through the pad openings 147. The pad openings 145, 147 can be formed using a lithography process followed by an etching process. In some embodiments, the etching process can be a non-isotropic dry etching process using argon and tetrafluoromethane as etchants. The process temperature for the etching process can be between about 120 °C and about 160 °C. The process pressure for the etching process can be between about 0.3 Torr and about 0.4 Torr. The process duration for the etching process can be between about 33 seconds and about 39 seconds. Alternatively, in some embodiments, the etching process can be a non-isotropic dry etching process using helium and nitrogen trifluoride as etchants. The process temperature for the etching process can be between about 80 °C and about 100 °C. The process pressure for the etching process can be between about 1.2 Torr and about 1.3 Torr. The process duration for the etching process can be between about 20 seconds and about 30 seconds.

[0164] Referring to Figure 6A conductive material can be formed to fill the liner openings 145, 147 to form a first lower bonding pad 151 and a second lower bonding pad 153, respectively. In some embodiments, the conductive material can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination of the foregoing. In some embodiments, the liner openings 145, 147 can be sequentially filled with the conductive material by sputtering or electroless plating. For example, when the liner openings 145, 147 are filled by sputtering using an aluminum copper material as a source, a process temperature of the sputtering can be between about 100 °C and about 400 °C. A process pressure of the sputtering can be between about 1 mTorr and about 100 mTorr. For another example, the liner openings 145, 147 can be filled by an electroplating process using an electroplating solution. The electroplating solution can include copper sulfate, copper methanesulfonate, copper gluconate, copper aminosulfonate, copper nitrate, copper phosphate, or copper chloride. A pH of the electroplating solution can be between about 2 and about 6 or between about 3 and about 5. A process temperature of the electroplating process can be maintained between about 40 °C and about 75 °C or between about 50 °C and about 70 °C.

[0165] Referring to Figure 6 The first lower bonding pad 151 can be formed in the liner opening 145 and can be electrically connected to the first redistribution layer 131. It is noted that the first lower bonding pad 151 is not electrically connected to any functional units in the first substrate 111. The second lower bonding pad 153 can be formed in the liner opening 147 and can be electrically connected to the top plug 127. That is, the second lower bonding pad 153 can be coupled with functional units in the first substrate 111 through the plug structure 121.

[0166] Referring to Figure 6 The first substrate 111, the first intermediate dielectric layer 113, the plug structure 121, the first redistribution layer 131, the first bottom passivation layer 141, the first top passivation layer 143, the first lower bonding pad 151, and the second lower bonding pad 153 together constitute a first chip 100. In some embodiments, the first chip 100 can be configured as a logic chip. The first chip 100 can include a front surface 100FS. It is noted that the term “front” surface is a terminology used in the present technology, implying a major surface of a structure on which element members and conductive components are formed. In the present embodiment, the front surface 100FS of the first chip 100 can be a top surface of the first top passivation layer 143.

[0167] Referring to Figure 1 and Figure 7At step S15, a second chip 200 can be provided, which includes a plurality of memory cells 221, a first higher bonding pad 241, and a second higher bonding pad 243.

[0168] Referring to Figure 7 The second chip 200 can include a second substrate 211, a plurality of second element structures (not shown for clarity), a second intermediate dielectric layer 213, a plurality of second conductive components (not shown for clarity), the memory cells 221, a second top passivation layer 231, the first higher bonding pad 241, and the second higher bonding pad 243.

[0169] Referring to Figure 7 In some embodiments, the second substrate 211 can include a bulk semiconductor substrate composed entirely of at least one semiconductor material; the bulk semiconductor substrate does not include any dielectric, insulating layer, or conductive component. The bulk semiconductor substrate can include, for example, an elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other Group III-V compound semiconductor or Group II-VI compound semiconductor; or a combination of the foregoing.

[0170] In some embodiments, the second substrate 211 can include a semiconductor-on-insulator structure that includes, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer can include the same materials as the bulk semiconductor substrate described above. The insulating layer can be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer can be a dielectric oxide, such as silicon oxide. For another example, the insulating layer can be a dielectric nitride, such as silicon nitride or boron nitride. For yet another example, the insulating layer can include a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer can have a thickness of between about 10 nm and about 200 nm.

[0171] The second element structures can be formed on the second substrate 211. Some portions of the element structures can be formed in the second substrate 211. The second element structures can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, the like, or a combination of the foregoing.

[0172] Referring to Figure 7A second intermediate dielectric layer 213 can be formed on the second substrate 211 and cover the second element members. The second intermediate dielectric layer 213 can be a laminate structure. The second intermediate dielectric layer 213 can include a plurality of insulating sub-layers (not shown for clarity). Each of the insulating sub-layers can have a thickness between about 0.5 microns and about 3.0 microns. The insulating sub-layers can include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant dielectric materials, similar materials thereof, or combinations of the foregoing. The insulating sub-layers can include different materials, but are not limited thereto.

[0173] The second conductive components can include interconnect layers, conductive vias, and conductive pads. The interconnect layers can be separated from each other and can be horizontally disposed in the second intermediate dielectric layer 213 along the direction Z. In the present embodiment, the topmost interconnect layer can be designated as a conductive pad. The conductive vias can connect adjacent interconnect layers along the direction Z, adjacent second element members and interconnect layers, and adjacent conductive pads and interconnect layers. In some embodiments, the conductive vias can improve heat dissipation and can provide structural support. In some embodiments, the second conductive components can include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations of the foregoing. The second conductive components can be formed during formation of the second intermediate dielectric layer 213.

[0174] Referring to Figure 7 The memory cells 221 can be formed in the second intermediate dielectric layer 213 and can be electrically coupled to the second conductive components. In some embodiments, the memory cells 221 can be configured as a capacitor array. In some embodiments, the memory cells 221 can be configured as a floating array.

[0175] Referring to Figure 7A second top passivation layer 231 can be formed on the second intermediate dielectric layer 213. In some embodiments, the second top passivation layer 231 may include materials such as polybenzoxazole, polyimide, benzocyclobutene, ajinomoto reinforcing film, solder photoresist film, or similar materials. Polymer materials (e.g., polyimide) can have many attractive properties, such as the ability to fill high aspect ratio openings, relatively low dielectric constant (approximately 3.2), simple deposition process, reduced sharp parts or steps in the underlying layer, and high temperature resistance after curing. In some embodiments, the fabrication techniques for the second top passivation layer 231 may include, for example, spin coating, lamination, deposition, or similar techniques. Deposition may include chemical vapor deposition, such as plasma-assisted chemical vapor deposition. The process temperature for plasma-assisted chemical vapor deposition may be between approximately 350°C and approximately 450°C. The process pressure for plasma-assisted chemical vapor deposition may be between approximately 2.0 Torr and approximately 2.8 Torr. The process duration of plasma-assisted chemical vapor deposition can be between approximately 8 seconds and approximately 12 seconds.

[0176] Reference Figure 7 A first higher bonding pad 241 and a second higher bonding pad 243 can be formed in the second top passivation layer 231. In some embodiments, a pad opening can be formed ( Figure 7 (Not shown) A conductive material can be formed in the second top passivation layer 231 to fill the pad openings, forming the first higher bonding pad 241 and the second higher bonding pad 243. The fabrication technique for the pad openings can include a lithography process and a subsequent etching process. In some embodiments, the etching process can be an anisotropic dry etching process using argon and tetrafluoromethane as etchants. The etching process temperature can be between approximately 120°C and approximately 160°C. The etching process pressure is between approximately 0.3 Torr and approximately 0.4 Torr. The etching process duration can be between approximately 33 seconds and approximately 39 seconds. Alternatively, in some embodiments, the etching process can be an anisotropic dry etching process using helium and nitrogen trifluoride as etchants. The etching process temperature can be between approximately 80°C and approximately 100°C. The etching process pressure is between approximately 1.2 Torr and approximately 1.3 Torr. The etching process can last between approximately 20 seconds and approximately 30 seconds. In some embodiments, the conductive material may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0177] In some embodiments, the liner openings can be sequentially filled with a conductive material by sputtering or electroless plating. For example, when filling the liner openings by sputtering using aluminum copper material as a source, the sputtering process temperature can be between about 100 °C to about 400 °C. The sputtering process pressure can be between about 1 mTorr to about 100 mTorr. For another example, the liner openings can be filled by an electroplating process using an electroplating solution. The electroplating solution can include copper sulfate, copper methanesulfonate, copper gluconate, copper aminosulfonate, copper nitrate, copper phosphate, or copper chloride. The pH value of the electroplating solution can be between about 2 to about 6 or between about 3 to about 5. The electroplating process temperature can be maintained between about 40 °C to about 75 °C or between about 50 °C to about 70 °C.

[0178] In some embodiments, the second chip 200 can be configured as a memory chip. The first higher bonding pad 241 and the second higher bonding pad 243 can be configured to serve as input / output of the memory chip. The second chip 200 can include a front surface 200FS. In the present embodiment, the front surface 200FS of the second chip 200 can be a top surface of the second top passivation layer 231.

[0179] Referring to Figure 1 and Figure 8 At step S17, the second chip 200 can be bonded to the first chip 100 to form a semiconductor element 1A.

[0180] Referring to Figure 8 The second chip 200 can be bonded to the first chip 100 in a face-to-face configuration by a hybrid bonding process. The front surface 200FS of the second chip 200 can be bonded to the front surface 100FS of the first chip 100. After the hybrid bonding process, the second chip 200 (configured as a memory chip) and the first chip 100 (configured as a logic chip) can together constitute an integrated circuit package. For example, the second higher bonding pad 243 can be disposed on the second lower bonding pad 153. That is, the second higher bonding pad 243 can be coupled with the functional unit of the first chip 100 through the plug structure 121. Signals (such as control signals) can be transmitted from the first chip 100 to the memory unit 221 through the plug structure 121, the second lower bonding pad 153, and the second higher bonding pad 243. The first higher bonding pad 241 can be disposed on the first lower bonding pad 151. Signals (such as data signals) can be transmitted from the memory unit 221 to an external read unit without passing through the conductive components, the plug structure 121, and the functional unit of the first chip 100 through the first higher bonding pad 241, the first lower bonding pad 151, and the first redistribution layer 131.

[0181] In some embodiments, the hybrid bonding process can be, for example, thermo-compression bonding, passivation-capping-layer assisted bonding, or surface activated bonding. For example, the hybrid bonding process can include activating exposed surfaces of the second top passivation layer 231 and the first top passivation layer 143 (e.g., in a plasma process), cleaning the activated second top passivation layer 231 and the first top passivation layer 143, contacting the activated surface of the second top passivation layer 231 and the activated surface of the first top passivation layer 143, and performing a thermal anneal process to strengthen the bonding between the second top passivation layer 231 and the first top passivation layer 143.

[0182] In some embodiments, the process pressure of the hybrid bonding process can be between about 100 MPa and about 150 MPa. In some embodiments, the process temperature of the hybrid bonding process can be between about room temperature (e.g., 25 °C) and about 400 °C. In some embodiments, surface treatments such as wet chemical cleaning and gas / gas-phase thermal treatment can be used to reduce the process temperature or shorten the time consumption of the hybrid bonding process.

[0183] In some embodiments, the hybrid bonding process can include dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. The dielectric-to-dielectric bonding can result from the bonding between the second top passivation layer 231 and the first top passivation layer 143. The metal-to-metal bonding can result from the bonding between the first higher bonding pads 241 and the first lower bonding pads 151, and between the second higher bonding pads 243 and the second lower bonding pads 153. The metal-to-dielectric bonding can result from the bonding between the first top passivation layer 143 and the first higher bonding pads 241 and the second higher bonding pads 243, and between the second top passivation layer 231 and the first lower bonding pads 151 and the second lower bonding pads 153.

[0184] In some embodiments, when the first top passivation layer 143 and the second top passivation layer 231 include, for example, silicon oxide or silicon nitride, the bonding between the first top passivation layer 143 and the second top passivation layer 231 can be based on a hydrophilic bonding mechanism. A hydrophilic surface modification can be applied to the first top passivation layer 143 and the second top passivation layer 231 prior to bonding.

[0185] In some embodiments, when the first top passivation layer 143 and the second top passivation layer 231 comprise a polymeric adhesive such as polyimide, benzocyclobutene, and polybenzoxazole, the bonding between the first top passivation layer 143 and the second top passivation layer 231 can be based on thermal compression bonding.

[0186] In some embodiments, a thermal annealing process can be performed after the bonding process to enhance the dielectric-to-dielectric bonding and cause thermal expansion of the metal-to-metal bonding, thereby further improving the bonding quality.

[0187] Referring to Figure 8 In some embodiments, the width W4 of the first chip 100 and the width W5 of the second chip 200 can be substantially the same.

[0188] Figures 9 to 11 According to some embodiments of the present disclosure, semiconductor devices IB, 1C, and ID are shown in cross-sectional schematic views.

[0189] Referring to Figure 9 The semiconductor device IB can include a first barrier layer 161 disposed between the first top passivation layer 143 and the second lower bonding pad 153, between the top plug 127 and the second lower bonding pad 153, and between the second lower bonding pad 153 and the first bottom passivation layer 141. The first barrier layer 161 can include, for example, titanium, titanium nitride, or a combination of the foregoing. The fabrication techniques of the first barrier layer 161 can include, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other applicable deposition processes.

[0190] Referring to Figure 10 The semiconductor device 1C can include a second barrier layer 163 disposed between the first bottom passivation layer 141 and the top plug 127, between the top dielectric layer 117 and the top plug 127, and between the landing pad 125 and the top plug 127. The second barrier layer 163 can include the same materials as the first barrier layer 161, the description of which is not repeated here.

[0191] Referring to Figure 11In the semiconductor element 1D, the second barrier layer 163 can be disposed between the first bottom passivation layer 141 and the top plug 127, between the top dielectric layer 117 and the top plug 127, and between the landing pad 125 and the top plug 127. In some embodiments, the second barrier layer 163 can have a U-shaped cross-sectional profile extending toward the landing pad 125. A top surface of the second barrier layer 163 and a top surface of the top plug 127 can be recessed to the vertical level VL1 between the top surface 131TS and the bottom surface 131BS of the first redistribution layer 131. The third barrier layer 165 can be conformally disposed between the second lower bonding pad 153 and the top plug 127. In some embodiments, the third barrier layer 165 can further include a U-shaped protrusion 165-1 extending toward the top plug 127 and disposed on a top surface of the top plug 127. In other words, a bottom surface 165BS of the U-shaped protrusion 165-1 (i.e., a bottom surface of the third barrier layer 165) can be lower than the top surface 131TS of the first redistribution layer 131 and higher than the bottom surface 131BS of the first redistribution layer 131. Thus, the second lower bonding pad 153 can further include a protrusion 155 extending toward the top plug 127 and disposed in a recess formed by the U-shaped protrusion 165-1. In some embodiments, the bottom surface 165BS of the U-shaped protrusion 165-1 can be circular. In some embodiments, the bottom surface 165BS of the U-shaped protrusion 165-1 can be substantially flat. The fourth barrier layer 167 can be conformally disposed between the first lower bonding pad 151 and the first redistribution layer 131. The third barrier layer 165 and the fourth barrier layer 167 can include the same material as the first barrier layer 161, which is not repeated here.

[0192] Figure 12 According to another embodiment of the disclosure, a method 20 of fabricating a semiconductor element 1E is shown in a flow chart. Figure 13 According to another embodiment of the disclosure, a portion of a fabrication flow of the semiconductor element 1E is shown in a top view schematic diagram. Figure 14 is a cross-sectional schematic diagram taken along Figure 13 the centerline A-A’.

[0193] Referring to Figures 12 to 14 At step S21, a third substrate 311 including a central region CR1 and a peripheral region PL1 can be provided, a plurality of memory cells 321 can be formed over the third substrate 311, and a plurality of central lower bonding pads 341 can be formed over the memory cells 321 and located in the central region CR1.

[0194] Referring to Figure 13 and Figure 14A third substrate 311 can be provided. The third substrate 311 can include a central region CR1 and a peripheral region PL1 surrounding the central region CR1. A third bottom intermediate dielectric layer 313 can be formed on the third substrate 311. The memory cells 321 can be formed in the third bottom intermediate dielectric layer 313. In some embodiments, the memory cells 321 can be configured as a capacitor array. In some embodiments, the memory cells 321 can be configured as a floating body array. A plurality of interconnect layers 315 can be formed in the third bottom intermediate dielectric layer 313 and can be electrically coupled to the memory cells 321. A third bottom passivation layer 331 can be formed on the third bottom intermediate dielectric layer 313. The central lower bonding pads 341 can be respectively and correspondingly formed on the interconnect layers 315. The central lower bonding pads 341 can be located in the central region CR1.

[0195] The third substrate 311, the third bottom intermediate dielectric layer 313, the memory cells 321, the interconnect layers 315, the third bottom passivation layer 331, and the central lower bonding pads 341 can be respectively and correspondingly formed by steps similar to the second substrate 211, the second intermediate dielectric layer 213, the memory cells 221, the second conductive components, the second top passivation layer 231, and the first higher bonding pads 241, the description of which will not be repeated here.

[0196] Figure 15 According to another embodiment of the disclosure, a portion of a fabrication flow of a semiconductor device 1E is shown in a top view schematic diagram. Figure 16 is a cross-sectional schematic diagram taken along Figure 15 the centerline A-A’.

[0197] Referring to Figure 12 , Figure 15 , Figure 16 , at step S23, a plurality of redistribution plugs 353 can be formed on the central lower bonding pads 341, a plurality of first support plugs 361 and a plurality of second support plugs 363 can be formed above the third substrate 311.

[0198] Referring to Figure 15 and Figure 16 , a third top intermediate dielectric layer 317 can be formed on the third bottom passivation layer 331. The redistribution plugs 353 can be respectively and correspondingly formed on the central lower bonding pads 341. The redistribution plugs 353 can be formed in the third top intermediate dielectric layer 317 and can be located in the central region CR1. The first support plugs 361 and the second support plugs 363 can be formed in the third top intermediate dielectric layer 317.

[0199] For simplicity, clarity and ease of understanding, only one redistribution plug 353, one first support plug 361, and one second support plug 363 are described. The distance Dl between an adjacent pair of redistribution plug 353 and first support plug 361 is about the same as the distance D2 between an adjacent pair of first support plug 361 and second support plug 363.

[0200] The third top intermediate dielectric layer 317, redistribution plug 353, first support plug 361, and second support plug 363 can be formed respectively and correspondingly by similar steps as the third bottom passivation layer 331 and top plug 127, the description of which is not repeated here.

[0201] Figure 17 According to another embodiment of the disclosure, a portion of the fabrication flow of semiconductor device 1E is shown in a top view schematic diagram. Figure 18 is a cross-sectional schematic diagram taken along Figure 17 the centerline A-A'.

[0202] Referring to Figure 12 , Figure 17 , and Figure 18 , at step S25, a plurality of second redistribution layers 355 can be formed on the redistribution plug 353, the first support plug 361, and the second support plug 363, wherein the redistribution plug 353 and the second redistribution layer 355 together constitute a plurality of redistribution structures 351.

[0203] Referring to Figure 17 and Figure 18 , the second redistribution layer 355 can be formed on the third top intermediate dielectric layer 317. For simplicity, clarity and ease of understanding, only one second redistribution layer 355 is described. The second redistribution layer 355 can be formed on the redistribution plug 353, first support plug 361, and second support plug 363. The redistribution plug 353 and the second redistribution layer 355 can together constitute a redistribution structure 351. The first support plug 361 and the second support plug 363 can be floating. The first support plug 361 and the second support plug 363 can provide additional support during subsequent bonding processes, as will be explained later. The second redistribution layer 355 can be formed by similar steps as the first redistribution layer 131, the description of which is not repeated here.

[0204] Figure 19 According to another embodiment of the disclosure, a portion of the fabrication flow of semiconductor device 1E is shown in a top view schematic diagram. Figure 20 is a cross-sectional schematic diagram taken along Figure 19 the centerline A-A'.

[0205] Referring to Figure 12 , Figure 19, and Figure 20 At step S27, a plurality of peripheral higher bonding pads 343 can be formed on the second redistribution layer 355 to constitute a third chip 300.

[0206] Referring to Figure 19 and Figure 20 A third top passivation layer 333 can be formed on the third top intermediate dielectric layer 317 to cover the second redistribution layer 355. The peripheral higher bonding pads 343 can be formed on the second redistribution layer 355 respectively and correspondingly. The peripheral higher bonding pads 343 can be formed in the third top passivation layer 333 and can be located in the peripheral region PL1.

[0207] The third substrate 311, the third bottom intermediate dielectric layer 313, the interconnect layers 315, the third top intermediate dielectric layer 317, the memory cells 321, the third bottom passivation layer 331, the central lower bonding pads 341, the redistribution structures 351, the first support plugs 361, the second support plugs 363, the third top passivation layer 333, and the peripheral higher bonding pads 343 together constitute the third chip 300. In some embodiments, the third chip 300 can be configured as a memory chip. The peripheral higher bonding pads 343 can be configured as input / output of the third chip 300. The redistribution structures 351 can combine with the central lower bonding pads 341 to transmit signals of the memory cells 321 from the central region CR2 to the peripheral higher bonding pads 343 located in the peripheral region PL1 of the third chip 300.

[0208] Figures 21 to 23 According to another embodiment of the disclosure, a part of a fabrication flow of a semiconductor device 1E is shown in a cross-sectional schematic view.

[0209] Referring to Figure 12 and Figure 21 At step S29, a fifth chip 500 can be provided.

[0210] Referring to Figure 21A fifth chip 500 can be provided. The fifth chip 500 can include a fifth substrate 511, a fifth intermediate dielectric layer 513, a fifth top passivation layer 533, a plurality of fifth center bonding pads 541, and a plurality of fifth peripheral bonding pads 543. The fifth substrate 511 can include a center region CR2 and a peripheral region PL2 surrounding the center region CR2. The fifth intermediate dielectric layer 513 can be formed on the fifth substrate 511. The fifth top passivation layer 533 can be formed on the fifth intermediate dielectric layer 513. The fifth center bonding pads 541 and the fifth peripheral bonding pads 543 can be formed in the fifth top passivation layer 533. The fifth center bonding pads 541 can be located in the center region CR2, and the fifth peripheral bonding pads 543 can be located in the peripheral region PL2.

[0211] The fifth substrate 511, the fifth intermediate dielectric layer 513, the fifth top passivation layer 533, the fifth center bonding pads 541, and the fifth peripheral bonding pads 543 can be formed by similar steps as the first substrate 111, the first intermediate dielectric layer 113, the first top passivation layer 143, the first lower bonding pads 151, respectively and correspondingly, the description of which is not repeated here. In some embodiments, the fifth chip 500 can be configured as a logic chip.

[0212] Referring to Figure 12 , Figure 22 , and Figure 23 , at step S31, the third chip 300 can be bonded to the fifth chip 500, and a molding layer 611 can be formed to cover the third chip 300.

[0213] Referring to Figure 22 , the fourth chip 400 can be formed by similar steps as the third chip 300, the description of which is not repeated here. The third chip 300 can be bonded to the fifth chip 500 by a hybrid bonding process similar to that shown in Figure 8 , the description of which is not repeated here. In some embodiments, the width W6 of the third chip 300 is smaller than the width W7 of the fifth chip 500. After the bonding process, the peripheral higher bonding pads 343 can be bonded to the fifth center bonding pads 541 and the fifth center bonding pads 543, respectively and correspondingly. The fourth chip 400 can be bonded to the fifth chip 500 by similar steps as the third chip 300, the description of which is not repeated here.

[0214] Referring to Figure 23A molding layer 611 can be formed on the fifth chip 500 to cover the third chip 300 and the fourth chip 400. In some embodiments, the molding layer 611 can include a molding compound such as polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate, or ammonium bifluoride. The fabrication technique of the molding layer 611 can include compressive molding, transfer molding, liquid encapsulant molding, or the like. For example, the molding compound can be dispensed in a liquid form. Subsequently, a curing process is performed to solidify the molding compound. The formation of the molding compound can overflow the third chip 300 and the fourth chip 400 Figure 22 The intermediate semiconductor element shown in FIG. 6A is such that the molding compound can completely cover the third chip 300 and the fourth chip 400. The third chip 300, the fourth chip 400, the fifth chip 500, and the molding layer 611 together constitute the semiconductor element 1E.

[0215] One aspect of the present disclosure provides a semiconductor element, comprising: a first chip comprising: a first intermediate dielectric layer on a first substrate; a plug structure in the first intermediate dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer on the first intermediate dielectric layer and away from the plug structure; a first lower bonding pad on the first redistribution layer; and a second lower bonding pad on the plug structure. The semiconductor element further comprises a second chip on the first chip, comprising: a first higher bonding pad on the first lower bonding pad; a second higher bonding pad on the second lower bonding pad; and a plurality of memory cells electrically coupled to the first higher bonding pad and the second higher bonding pad.

[0216] Another aspect of the present disclosure provides a semiconductor element, comprising: a first chip comprising: a first substrate comprising a central region and a surrounding region surrounding the central region; a first central bonding pad above the central region of the first substrate; and a first surrounding bonding pad above the surrounding region of the first substrate. The semiconductor element further comprises a second chip on the first chip, comprising: a plurality of surrounding higher bonding pads on a surrounding region of the second chip and respectively on the first central bonding pad and the first surrounding bonding pad; a plurality of redistribution structures respectively on the surrounding higher bonding pads and extending toward a central region of the second chip; a plurality of central lower bonding pads on the central region of the second chip and respectively on the redistribution structures; and a plurality of memory cells electrically coupled to the central lower bonding pads.

[0217] Another aspect of the present disclosure provides a method of fabricating a semiconductor device, comprising: providing a first substrate including a functional unit; forming a plug structure on the first substrate and electrically coupled to the functional unit; forming a first redistribution layer over the first substrate; forming a first lower bonding pad on the first redistribution layer; forming a second lower bonding pad on the plug structure, wherein the first substrate, the plug structure, the first redistribution layer, the first lower bonding pad, and the second lower bonding pad together form a first chip; and bonding a second chip to the first chip. The second chip includes a first upper bonding pad bonded to the first lower bonding pad, a second upper bonding pad bonded to the second lower bonding pad, and a plurality of memory units electrically coupled to the first upper bonding pad and the second upper bonding pad.

[0218] Due to the design of the semiconductor device of the present disclosure, data signals can be transmitted through the first upper bonding pad 241, the first lower bonding pad 151, and the first redistribution layer 131 without passing through the conductive components of the first chip 100, the plug structure 121, and the functional unit. As a result, the transmission distance can be reduced, and thus the performance of the semiconductor device 1A can be improved. In addition, since the transmission distance is short, the power consumption of the semiconductor device 1A can be reduced.

[0219] While the present disclosure and the best mode thereof have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above can be implemented differently, and many of the described processes can be implemented as other processes or combinations of processes.

[0220] Further, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized. Accordingly, the appended claims are intended to cover all processes, machines, manufacture, compositions of matter, means, methods, or steps, substantially as set forth in the disclosure and including such alternative embodiments in the present disclosure.

Claims

1. A semiconductor device, comprising: a first chip, comprising: a first substrate, comprising a central region and a surrounding region surrounding the central region; a first central bonding pad over the central region of the first substrate; and a first surrounding bonding pad over the surrounding region of the first substrate; and a second chip over the first chip, and comprising: a plurality of surrounding higher bonding pads over a surrounding region of the second chip, and respectively over the first central bonding pad and the first surrounding bonding pad; a plurality of redistribution structures respectively over the surrounding higher bonding pads and extending toward a central region of the second chip; a plurality of central lower bonding pads over the central region of the second chip, and respectively over the redistribution structures; and a plurality of memory cells electrically coupled to the central lower bonding pads.

2. The semiconductor device of claim 1, wherein the redistribution structures comprise: a plurality of redistribution layers respectively over the surrounding higher bonding pads, and respectively extending from the surrounding region of the second chip toward the central region of the second chip; and a plurality of redistribution plugs over the central region of the second chip, and respectively and correspondingly between the central lower bonding pads and the redistribution layers.

3. The semiconductor device of claim 2, further comprising a plurality of first support plugs respectively over the redistribution layers, wherein the first support plugs are distanced from the redistribution plugs and the first support plugs are floating.

4. The semiconductor device of claim 3, further comprising a plurality of second support plugs respectively over the redistribution layers, wherein the second support plugs are distanced from the first support plugs and the second support plugs are floating.

5. The semiconductor device of claim 4, wherein a distance between an adjacent pair of the redistribution plugs and the first support plugs is substantially the same as a distance between an adjacent pair of the first support plugs and the second support plugs.

6. The semiconductor device of claim 2, further comprising a molding layer over the first chip and covering the second chip. ​

Images