Silicon controlled rectifier and method of manufacturing the same

Abstract

The application provides a thyristor and a preparation method thereof. The first low-resistance region and the second low-resistance region are respectively arranged in the first well region and the second well region of the thyristor. The overall resistance of the first well region and the second well region is reduced due to the low resistance of the first low-resistance region and the second low-resistance region, so that the on-voltage of the device is reduced, and the ability of the thyristor to discharge current is improved. The first low-resistance region is arranged below the first doped region, and the second low-resistance region is arranged below the fourth doped region. Therefore, the first low-resistance region does not affect the conduction of the transistor formed by the second doped region, the first well region and the second well region; and the second low-resistance region does not affect the conduction of the transistor formed by the first well region, the second well region and the third doped region. Therefore, the thyristor and the preparation method thereof can reduce the on-voltage of the thyristor without affecting the response speed of the thyristor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a thyristor rectifier and its preparation method. Background Technology

[0002] Silicon controlled rectifiers (SCRs) are widely used in power devices. Because they can switch between high and low resistance states, they can be used as power switches and are also commonly used for electrostatic discharge (ESD) protection, possessing excellent static discharge capabilities. Compared to diodes, transistors, and field-effect transistors, their positive feedback mechanism gives SCRs advantages such as strong current discharge capability, high discharge efficiency per unit area, low on-resistance, strong robustness, and high protection levels. This allows for high ESD protection levels to be achieved with a relatively small chip area on a semiconductor planar process.

[0003] Therefore, SCRs are commonly used for ESD protection of high-speed ports. Currently, high-speed ports such as USB 3.x, HDMI 2.x, and Thunderbolt 4.0 have transmission rates exceeding 5GHz. While the speed is increasing, the port withstand voltage is decreasing. SCR-based protection devices can better meet ESD and signal integrity requirements, but the performance of SCR devices still needs further improvement. A key parameter of SCR is its on-state voltage Vc, tested under transmission line pulse signal conditions and a read current of 16A. To balance response speed requirements, the capacitance of the N-well and P-well regions in the SCR should be as low as possible, which requires that the doping concentration of the N-well and P-well regions not be too high. However, reducing the doping concentration of the N-well and P-well regions leads to a higher resistance in the N-well and P-well regions after the SCR is turned on, resulting in a higher on-state voltage Vc and reducing the SCR's discharge current capability, making it difficult to meet the ESD protection requirements of high-speed ports. Clearly, improving the response speed of the SCR and reducing its on-state voltage Vc are contradictory and cannot be achieved simultaneously. Summary of the Invention

[0004] The purpose of this invention is to provide a thyristor rectifier and its manufacturing method, so as to solve the problem of how to reduce the turn-on voltage of the thyristor rectifier without affecting its response speed.

[0005] To solve the above-mentioned technical problems, the present invention provides a silicon controlled rectifier, comprising:

[0006] Substrate structure;

[0007] A first well region is located in the substrate structure, and the first well region includes a first doped region and a second doped region;

[0008] The second well region is located in the substrate structure, and the second well region includes a third doped region and a fourth doped region;

[0009] A first low-resistivity region is located in the first well region, and the first low-resistivity region is disposed below the first doped region;

[0010] The second low-resistivity region is located in the second well region and is disposed below the fourth doped region;

[0011] An isolation structure is located on the surface of the substrate structure, and the isolation structure has a plurality of conductive interconnect structures.

[0012] Optionally, in the thyristor rectifier, the resistivity of the first low-resistivity region is less than the resistivity of the first well region, and the resistivity of the second low-resistivity region is less than the resistivity of the second well region.

[0013] Optionally, in the aforementioned silicon controlled rectifier, the first low-resistance region and the first well region have a first conductivity type; the second low-resistance region and the second well region have a second conductivity type.

[0014] Optionally, in the aforementioned silicon controlled rectifier, the ion doping concentration range in the first low-resistivity region and the second low-resistivity region is 1*10⁻⁶. 17 cm -3 ~1*10 18 cm -3 ; and / or, the ion doping concentration range in the first well region and the second well region is: 1*10 16 cm -3 ~1*10 17 cm -3 .

[0015] Optionally, in the aforementioned silicon controlled rectifier, the silicon controlled rectifier further includes a fifth doped region; wherein the first well region and the second well region are adjacent to each other and both extend downward from the surface of the substrate structure, and the fifth doped region is disposed at the junction of the first well region and the second well region.

[0016] Optionally, in the aforementioned silicon controlled rectifier, the first doped region and the third doped region have a first conductivity type; the second doped region, the fourth doped region, and the fifth doped region have a second conductivity type.

[0017] Wherein, the ion doping concentration in the first doped region, the second doped region, the third doped region, the fourth doped region, and the fifth doped region is greater than or equal to 1*10⁻⁶. 19 cm -3 .

[0018] Optionally, in the aforementioned silicon controlled rectifier, the plurality of conductive interconnect structures include: multiple metal lines and multiple metal interconnect layers;

[0019] The isolation structure includes at least two dielectric layers stacked on the surface of the substrate structure; wherein, each dielectric layer contains multiple metal lines, and multiple metal interconnect layers are spaced apart at the junction of two adjacent dielectric layers and are electrically connected to the multiple metal lines in the two adjacent dielectric layers respectively.

[0020] Optionally, in the aforementioned silicon controlled rectifier, the silicon controlled rectifier further includes:

[0021] A first conductive layer is located on the isolation structure, and the first conductive layer is electrically connected to the first doped region and the second doped region via the conductive interconnect structure;

[0022] The second conductive layer is located on the isolation structure and spaced apart from the first conductive layer. The second conductive layer is electrically connected to the third doped region and the fourth doped region via the conductive interconnect structure.

[0023] Optionally, in the aforementioned silicon controlled rectifier, the substrate structure includes a substrate and an epitaxial layer located on the surface of the substrate; wherein the ion doping concentration in the epitaxial layer is less than the ion doping concentration in the substrate.

[0024] Based on the same inventive concept, the present invention also provides a method for manufacturing a silicon controlled rectifier, comprising:

[0025] Provide a base structure;

[0026] A first low-resistivity region, a second low-resistivity region, a first well region, and a second well region are formed in the substrate structure; wherein the first low-resistivity region is located in the first well region, and the second low-resistivity region is located in the second well region;

[0027] A first doped region and a second doped region are formed in the first well region, and a third doped region and a fourth doped region are formed in the second well region; wherein, the first low-resistivity region is located below the first doped region, and the second low-resistivity region is located below the fourth doped region;

[0028] An isolation structure is formed on the surface of the substrate structure, and a plurality of conductive interconnect structures are formed in the isolation structure.

[0029] Optionally, in the method for fabricating the thyristor rectifier, a substrate structure is provided; a first low-resistivity region, a second low-resistivity region, a first well region, and a second well region are formed in the substrate structure, including:

[0030] Provide a substrate;

[0031] A first epitaxial layer is formed on the surface of the substrate.

[0032] A first low-resistivity region, a second low-resistivity region, a first well region, and a second well region are formed in the first epitaxial layer.

[0033] Optionally, in the method for fabricating the thyristor rectifier, a substrate structure is provided; a first low-resistivity region, a second low-resistivity region, a first well region, and a second well region are formed in the substrate structure, including:

[0034] Provide a substrate;

[0035] A first epitaxial layer is formed on the surface of the substrate;

[0036] A first low-resistivity region and a second low-resistivity region are formed in the first epitaxial layer;

[0037] A second epitaxial layer is formed on the surface of the first epitaxial layer;

[0038] A first well region and a second well region are formed in the first epitaxial layer and the second epitaxial layer.

[0039] Optionally, in the method for fabricating the silicon controlled rectifier, a fifth doped region is formed at the junction of the first well region and the second well region before forming the isolation structure and the conductive interconnect structure.

[0040] In summary, this invention provides a silicon controlled rectifier (SCR) and its fabrication method. The SCR includes a first low-resistance region and a second low-resistance region in the first well region and the second well region, respectively. Because the resistance values ​​of the first and second low-resistance regions are low, the overall resistance of both the first and second well regions decreases, thereby reducing the on-state voltage of the device and improving the discharge current capability of the SCR. Furthermore, the first low-resistance region is located below the first doped region, and the second low-resistance region is located below the fourth doped region. Therefore, the first low-resistance region does not affect the conduction of the transistor formed by the second doped region, the first well region, and the second well region; the second low-resistance region does not affect the conduction of the transistor formed by the first well region, the second well region, and the third doped region. Therefore, the SCR provided by this invention can reduce the on-state voltage of the SCR without affecting its response speed. Attached Figure Description

[0041] Figure 1-15 This is a schematic diagram of the semiconductor structure in each step of the fabrication method of a silicon controlled rectifier in one embodiment;

[0042] The attached figures are labeled as follows:

[0043] 100 - Substrate; 101 - Epitaxial layer; 101a - First epitaxial layer; 101b - Second epitaxial layer; 102 - First mask layer; 103 - First low-resistivity region; 104 - Second mask layer; 105 - Second low-resistivity region; 106 - Third mask layer; 107 - First well region; 108 - Fourth mask layer; 109 - Second well region; 110 - Fifth mask layer; 111 - First doped region; 112 - Third mask layer; 113 - Sixth mask layer; 114 - Second doped region; 115 - Fourth doped region; 116 - Fifth doped region; 117 - First dielectric layer; 118 - Metal line; 119 - Metal interconnect layer; 120 - Second dielectric layer; 121 - First conductive layer; 122 - Second conductive layer. Detailed Implementation

[0044] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0045] To address the aforementioned technical problems, this embodiment provides a silicon controlled rectifier (SCR). Please refer to [link / reference]. Figure 15 include:

[0046] Substrate structure;

[0047] A first well region 107 is located in the substrate structure, and the first well region 107 includes a first doped region 111 and a second doped region 114.

[0048] The second well region 109 is located in the substrate structure, and the second well region 109 includes a third doped region 112 and a fourth doped region 115.

[0049] The first low-resistivity region 103 is located in the first well region 107, and the first low-resistivity region 103 is disposed below the first doped region 111.

[0050] The second low-resistivity region 105 is located in the second well region 109, and the second low-resistivity region 105 is disposed below the fourth doped region 115.

[0051] An isolation structure (117, 120) is located on the surface of the substrate structure, and the isolation structure (117, 120) is provided with a plurality of conductive interconnect structures (118, 119).

[0052] The first well region 107, the first doped region 111, the third doped region 112, and the first low-resistivity region 103 all have a first conductivity type. The second well region 109, the second doped region 114, the fourth doped region 115, and the second low-resistivity region 105 all have a second conductivity type. In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0053] As can be seen, in this embodiment, a first low-resistance region 103 and a second low-resistance region 105 are respectively added to the first well region 107 and the second well region 108 of the silicon controlled rectifier. Because the resistance values ​​of the first low-resistance region 103 and the second low-resistance region 105 are low, the overall resistance of the first well region 107 and the second well region 108 decreases, thereby reducing the on-state voltage of the device and improving the discharge current capability of the silicon controlled rectifier. Furthermore, the first low-resistance region 103 is located below the first doped region 111, and the second low-resistance region 105 is located below the fourth doped region 115. Therefore, the first low-resistance region 103 does not affect the conduction of the transistor formed by the second doped region 114, the first well region 107, and the second well region 109; the second low-resistance region 105 does not affect the conduction of the transistor formed by the first well region 107, the second well region 109, and the third doped region 112. Therefore, the thyristor rectifier provided in this embodiment can reduce the on-state voltage of the thyristor rectifier without affecting its response speed.

[0054] In one embodiment of this application, a first conductive layer 121 is located on the isolation structure 120, and the first conductive layer 121 is electrically connected to the first doped region 111 and the second doped region 114 via the conductive interconnect structure (118, 119).

[0055] In one embodiment of this application, a second conductive layer 122 is located on the isolation structure 120 and spaced apart from the first conductive layer 121. The second conductive layer 122 is electrically connected to the third doped region 111 and the fourth doped region 114 via the conductive interconnect structure (118, 119).

[0056] The following describes the fabrication process of the thyristor rectifier and its attachments. Figure 1-15Specifically, the thyristor rectifier is described. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0057] Step 1: Please refer to Figure 1 , 3 And 6, provide a base structure.

[0058] The substrate structure includes a substrate 100, which may be a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. The substrate 100 can serve as an operational platform for subsequent device fabrication. However, to improve device performance, the substrate structure may also include an epitaxial layer 101. Both the substrate 100 and the epitaxial layer 101 have a second conductivity type.

[0059] In one embodiment of this application, the epitaxial layer 101 is grown on the surface of the substrate 100 using a chemical vapor deposition process. Furthermore, P-type ions are doped into both the epitaxial layer 101 and the substrate 100 using an ion doping process, so that both the substrate 100 and the epitaxial layer 101 possess a second conductivity type. The ion doping concentration in the epitaxial layer 101 is lower than the ion doping concentration in the substrate 100, which facilitates the formation of a low-doped first low-resistivity region and a low-resistivity region, thereby reducing the PN junction capacitance.

[0060] In one embodiment of this application, the epitaxial layer 101 can be formed into a film layer in a single preparation. For example... Figure 1 As shown, the first epitaxial layer 101a is formed on the surface of the substrate 100 in a single fabrication process, and the first epitaxial layer 101a serves as the epitaxial layer 101 in the substrate structure. In other embodiments of this application, the epitaxial layer 101 may also be formed into two layers through two fabrication processes. For example... Figure 3 and 6 As shown, the first epitaxial layer 101a is first formed on the surface of the substrate 100, followed by the formation of the second epitaxial layer 101b. The first epitaxial layer 101a and the second epitaxial layer 101b together serve as the epitaxial layer 101 in the substrate structure. Fabricating the epitaxial film in two stages allows for better control of the doping concentration in the first and second low-resistivity regions, thereby reducing the PN junction capacitance.

[0061] Step Two: Please refer to Figure 2 and 4-8, a first low-resistivity region 103, a second low-resistivity region 105, a first well region 107, and a second well region 109 are formed in the substrate structure; wherein, the first low-resistivity region 103 is located in the first well region 107, and the second low-resistivity region 105 is located in the second well region 109.

[0062] In one embodiment of this application, only one epitaxial film layer is formed in the substrate structure. For example... Figure 2 As shown, an epitaxial layer 101 is formed on the substrate 100. An ion-doping process is used to form a first low-resistivity region 103, a second low-resistivity region 105, a first well region 107, and a second well region 109 in the epitaxial layer 101. In this embodiment, the order in which the first low-resistivity region 103, the second low-resistivity region 105, the first well region 107, and the second well region 109 are formed is not limited. The first low-resistivity region 103 and the second low-resistivity region 105 can be formed first, followed by the first well region 107 and the second well region 109. Alternatively, the first well region 107 and the second well region 109 can be formed first, followed by the first low-resistivity region 103 and the second low-resistivity region 105. In this embodiment, both the first well region 107 and the first low-resistivity region 103 have a first conductivity type, i.e., N-type ions are doped into the first well region 107 and the first low-resistivity region 103. Both the second well region 109 and the second low-resistivity region 105 have a second conductivity type, that is, P-type ions are doped in the second well region 109 and the second low-resistivity region 105.

[0063] In other embodiments of this application, the substrate structure is provided with two epitaxial film layers, such as... Figure 4-8 As shown, a first low-resistivity region 103, a second low-resistivity region 105, a first well region 107, and a second well region 109 are formed in the epitaxial layer 101, which is jointly composed of the first epitaxial layer 101a and the second epitaxial layer 101b. The processes for forming the first low-resistivity region 103 and the second low-resistivity region 105 are similar, and the formation order is not fixed; the first low-resistivity region 103 can be formed first, or the second low-resistivity region 105 can be formed first. In this embodiment, the formation of the first low-resistivity region 103 is taken as an example.

[0064] In one embodiment of this application, such as Figure 4As shown, a first mask layer 102 is formed on the surface of the first epitaxial layer 101a. The first mask layer 102 exposes a portion of the surface of the first epitaxial layer 101a, and an ion doping process is performed using the first mask layer 102 as a barrier to form a first low-resistivity region 103 in the first epitaxial layer 101a. In this embodiment, the first low-resistivity region 103 has a first conductivity type, and the doped ion type is an N-type ion, such as a phosphorus ion, antimony ion, or arsenic ion. The ion doping concentration range in the first low-resistivity region 103 is 1*10⁻⁶. 17 cm -3 ~1*10 18 cm -3 The optional value is 1*10 17 cm -3 Or 1*10 18 cm -3 .

[0065] Then, as Figure 5 As shown, the first mask layer 102 is removed, and a second mask layer 104 is formed on the surface of the first epitaxial layer 101a. The second mask layer 104 exposes a portion of the surface of the first epitaxial layer 101a, and an ion implantation process is performed using the second mask layer 104 as a barrier to form a second low-resistivity region 105 in the first epitaxial layer 101a. In this embodiment, the second low-resistivity region 105 has a second conductivity type, and the doped ions are P-type ions, such as boron ions, gallium ions, or indium ions. The ion doping concentration in the second low-resistivity region 105 is the same as the ion doping concentration in the first low-resistivity region 103, and its range is 1*10⁻⁶. 17 cm -3 ~1*10 18 cm -3 The optional value is 1*10 17 cm -3 Or 1*10 18 cm -3 Because during ion implantation, the epitaxial layer is not obstructed on the top surfaces of the first low-resistivity region 103 and the second low-resistivity region 105, compared to... Figure 2 The structure shown makes it easier to control the concentration and doping range of the first low-resistivity region 103 and the second low-resistivity region.

[0066] Subsequently, such as Figure 6 As shown, the second mask layer 104 on the surface of the first epitaxial layer 101a is removed, and a second epitaxial layer 101b is grown on the surface of the first epitaxial layer 101a using a chemical vapor deposition process. Then, the first epitaxial layer 101a and the second epitaxial layer 101b constitute the epitaxial layer 101 in the silicon controlled rectifier.

[0067] Similarly, since the processes for forming the first well region 107 and the second well region 109 are similar, this embodiment does not limit the order in which the first well region 107 and the second well region 109 are prepared. Therefore, this embodiment takes the preparation of the first well region 107 as an example. Figure 7 As shown, a third mask layer 106 is formed on the surface of the epitaxial layer 101. The third mask layer 106 exposes a portion of the surface of the epitaxial layer 101. Using the third mask layer 106 as a barrier, an ion implantation process is performed to form a first well region 107 in the epitaxial layer 101. The first well region 107 encompasses the first low-resistivity region 103, meaning the first low-resistivity region 103 is located within the first well region 107.

[0068] Then, remove the third mask layer 106, as follows: Figure 8 As shown, a fourth mask layer 108 is formed on the surface of the epitaxial layer 101. The fourth mask layer 108 shields the first well region 107 and exposes a portion of the surface of the epitaxial layer 101. Subsequently, using the fourth mask layer 108 as a barrier, an ion implantation process is performed to form a second well region 109 in the epitaxial layer 101. The second well region 109 encompasses the second low-resistivity region 105, meaning the second low-resistivity region 105 is located within the second well region 109.

[0069] In one embodiment of this application, the first well region 107 and the second well region 104 are adjacent to each other and both extend downward from the surface of the epitaxial layer 101 by a predetermined thickness.

[0070] In one embodiment of this application, the first well region 107 has a first conductivity type, that is, the first well region 107 is doped with N-type ions, and the second well region 109 has a second conductivity type, that is, the second well region 109 is doped with P-type ions. Furthermore, the ion doping concentration range in the first well region 107 and the second well region 104 is 1*10⁴. 16 cm -3 ~1*10 17 cm -3 The optional value is 1*10 16 cm -3 Or 1*10 17 cm -3 .

[0071] In one embodiment of this application, in order to reduce the resistance of the first well region 107 after conduction, the resistivity of the first low-resistivity region 103 is less than that of the first well region 107. That is, the ion doping concentration of the first low-resistivity region 103 is greater than that of the first well region 107. Similarly, in order to reduce the resistance of the second well region 109 after conduction, the resistivity of the second low-resistivity region 105 is less than that of the second well region 109. That is, the ion doping concentration of the second low-resistivity region 105 is greater than that of the second well region 109.

[0072] As can be seen, this application places a buried layer (first low-resistivity region 103 and second low-resistivity region 105) inside the well regions (first well region 107 and second well region 109). Compared with setting a buried layer at the bottom of the well region, since the ion doping concentration of the first well region 107 and the second well region 109 is higher than the ion doping concentration of the corresponding first low-resistivity region 103 and the second low-resistivity region 105, the setting method of this application can avoid excessive increase in the bottom junction capacitance and avoid excessive increase in the capacitance of the entire device, which would lead to a decrease in the conduction response speed.

[0073] Step 3: Referring to Figures 9-10, a first doped region 111 and a second doped region 114 are formed in the first well region 107, and a third doped region 112 and a fourth doped region 115 are formed in the second well region 109; wherein, the first low-resistivity region 103 is located below the first doped region 111, and the second low-resistivity region 105 is located below the fourth doped region 115.

[0074] To form the basic components of the silicon controlled rectifier, NPN and PNP transistors need to be fabricated. In one embodiment of this application, the first doped region 111 and the third doped region 112 are both doped with N-type ions, and the second doped region 114 and the fourth doped region 115 are both doped with P-type ions. Then, the second doped region 114, the first well region 107, and the second well region 109 constitute a PNP transistor; the first well region 107, the second well region 109, and the third doped region 112 constitute an NPN transistor. The first doped region 111 and the fourth doped region 115 serve as lead-out interfaces.

[0075] Furthermore, this embodiment does not limit the positions of the first doped region 111 and the second doped region 114 in the first well region 107, nor does it limit the positions of the third doped region 112 and the fourth doped region 115 in the second well region 109. Also, since the first doped region 111 and the third doped region 112 both have a first conductivity type, i.e., the doped ions are both N-type ions, and the second doped region 114 and the fourth doped region 115 both have a second conductivity type, i.e., the doped ions are both P-type ions, the first doped region 111 and the third doped region 112 can be formed in the same step, as can the second doped region 114 and the fourth doped region 115. This embodiment does not limit the formation order; the following description uses the order of forming the first doped region 111 and the third doped region 112 first:

[0076] like Figure 9 As shown, after removing the fourth mask layer 108, a fifth mask layer 110 is formed on the surface of the epitaxial layer 101. The fifth mask layer 110 acts as an ion implantation barrier layer, covering a portion of the surface of the epitaxial layer 101 and exposing a portion of the first well region 107 and a portion of the second well region 109. The position of the first well region 107 exposed by the fifth mask layer 110 is the same vertical position of the epitaxial layer 101 exposed by the first mask layer 102 when forming the first low-resistivity region 103. However, the position of the second well region 109 exposed by the fifth mask layer 110 is different from the vertical position of the epitaxial layer 101 exposed by the second mask layer 104 when forming the second low-resistivity region 105, and there is no overlap.

[0077] Therefore, after the ion doping process, the first doped region 111 is located above the first low-resistivity region 103 and overlaps with a portion of the upper region perpendicular to the first low-resistivity region 103; the third doped region 112 is located above the second low-resistivity region 105 and does not overlap with the upper region perpendicular to the second low-resistivity region 105. In other words, the first low-resistivity region 103 is located below the first doped region 107, and the second low-resistivity region 105 is far below the third doped region 112. In one embodiment of this application, since the second doped region 114 is the emitter region of the PNP transistor and the first well region 107 is the base region of the PNP transistor, the second doped region 114 and the first well region 107 need to break down when conducting. If the first low-resistivity region 103 is located vertically below the second doped region 114, it will cause difficulties in conducting the PNP transistor, resulting in difficulties in conducting the silicon controlled rectifier. Similarly, if the second low-resistance region 105 is located vertically below the third doped region 112, it will also cause difficulties in turning on the NPN transistor, which will also lead to difficulties in turning on the silicon controlled rectifier.

[0078] Please see Figure 10 After forming the first doped region 111 and the third doped region 112, the fifth mask layer 110 is removed, and then a sixth mask layer 113 is formed. The sixth mask layer 113 exposes a portion of the first well region 107 and a portion of the second well region 109.

[0079] In one embodiment of this application, to reduce the breakdown voltage between the first well region 107 and the second well region 109, thereby lowering the device's on-state voltage, a fifth doped region 116 is provided at the boundary between the first well region 107 and the second well region 109. The fifth doped region 116 has a second conductivity type, meaning it is doped with P-type ions. Therefore, the second doped region 114, the fourth doped region 115, and the fifth doped region 116 can be simultaneously formed using the sixth mask layer 113 as a barrier layer and undergoing ion doping processes.

[0080] The second doped region 114 is located within the first well region 107, and the first low-resistivity region 103 is located below and away from the second doped region 114. The fourth doped region 115 is located within the second well region 109, and the second low-resistivity region 105 is located below the fourth doped region 115. The fifth doped region 116 is located at the boundary between the first well region 107 and the second well region 109.

[0081] Therefore, after forming the first doped region 111, the second doped region 114, the third doped region 112, the fourth doped region 115, and the fifth doped region 116, the first low-resistivity region 103 is disposed below the first doped region 111 and away from the second doped region 114; the second low-resistivity region 105 is disposed below the fourth doped region 115 and away from the third doped region 112. Therefore, in one embodiment of this application, the first low-resistivity region 103 does not affect the conduction of the PNP transistor formed by the second doped region 114, the first well region 107, and the second well region 109, and the second low-resistivity region 105 does not affect the conduction of the NPN transistor formed by the first well region 107, the second well region 109, and the third doped region 112.

[0082] In one embodiment of this application, the first doped region 111, the second doped region 114, the third doped region 112, the fourth doped region 115, and the fifth doped region 116 are all heavily doped, and the ion doping concentration therein is greater than or equal to 1*10⁻⁶. 19 cm -3 .

[0083] Step 4: Please refer to Figure 11-15 An isolation structure is formed on the surface of the epitaxial layer 101, and a conductive interconnect structure is formed in the isolation structure.

[0084] To bring out the first doped region 111, the second doped region 114, the third doped region 112, and the fourth doped region 115, an isolation structure and a conductive interconnect structure need to be formed on the surface of the epitaxial layer 101. The isolation structure, used for electrical isolation, is generally formed of an insulating material. Depending on the device requirements, the isolation structure includes at least two dielectric layers (117, 120). The specific number of layers is not limited in this embodiment and can be two, three, or four layers, etc. This embodiment uses two dielectric layers (117, 120) as an example, which are respectively the first dielectric layer 117 and the second dielectric layer 120. Furthermore, the conductive interconnect structure includes multiple metal lines 118 and multiple metal interconnect layers 119 for electrical lead-out.

[0085] Please see Figure 11-12 After removing the sixth mask layer 113, a first dielectric layer 117 is formed on the surface of the epitaxial layer 101. A plurality of first metal contact holes T1 are formed by dry or wet etching, and the plurality of first metal contact holes T1 penetrate the first dielectric layer 117. Figure 12Four first metal contact holes T1 are provided in the epitaxial layer 101. The number of first metal contact holes T1 is not limited in this embodiment. When the first doped region 111, the second doped region 114, the third doped region 112, and the fourth doped region 115 extend downwards along the top surface of the epitaxial layer 101, the plurality of first metal contact holes T1 expose portions of the first doped region 111, the second doped region 114, the third doped region 112, and the fourth doped region 115, respectively. If there is a gap between the top surfaces of the first doped region 111, the second doped region 114, the third doped region 112, and the fourth doped region 115 and the top surface of the epitaxial layer 101, the plurality of first metal contact holes T1 extend into the epitaxial layer 101 to expose the first doped region 111, the second doped region 114, the third doped region 112, and the fourth doped region 115.

[0086] After forming multiple first metal contact holes T1, please refer to Figure 13 An adhesion layer (not shown) is formed in the first metal contact hole T1 to enhance the connection stability between the subsequently formed metal line and each doped region. Optionally, the adhesion layer may be made of titanium or titanium nitride. Further, a metal material layer (not shown) is formed, filling all the first metal contact holes T1. Optionally, the metal material layer is formed using processes such as chemical vapor deposition or sputtering, and the material of the metal material layer is preferably tungsten. Therefore, the first metal contact holes T1 filled with the metal material layer constitute the metal line 118.

[0087] In one embodiment of this application, to reduce the resistance of the conductive interconnect structure, improve the overcurrent capability of the metal interconnect structure, and enhance process compatibility with other semiconductor devices, a plurality of metal interconnect layers 119 may be formed at the interface between two adjacent dielectric layers before forming another adjacent dielectric layer, and the metal interconnect layers 119 are spaced apart from each other. Figure 13 As shown, a metal interconnect material layer (not shown) is first formed on the surface of the first dielectric layer 117. Then, a portion of the metal interconnect material layer is removed using a dry etching or wet etching process, and the remaining portion constitutes the metal interconnect layer 119. Alternatively, a mask layer can be formed on the surface of the first dielectric layer 117, and multiple openings can be formed in the mask layer. Metal interconnect material layers are then filled into these openings to form the metal interconnect layer 119. The multiple metal interconnect layers 119 are connected to the metal lines 118 in the first dielectric layer 117. Figure 13As shown, the two metal interconnect layers 119 are respectively connected to the two metal lines 118 to bring out the first doped region 111 and the second doped region 114 together, and to bring out the third doped region 112 and the fourth doped region 115 together.

[0088] After forming the metal interconnect layer 119, as Figure 14-15 As shown, a second dielectric layer 120 is formed adjacent to the first dielectric layer 117. The second dielectric layer 120 covers the exposed portion of the first dielectric layer 117 and the metal interconnect layer 119. A plurality of second metal contact holes T2 are formed in the second dielectric layer 120. The plurality of second metal contact holes T2 penetrate the second dielectric layer 120 and are respectively connected to the plurality of metal interconnect layers 119. Then, a metal material layer is used to fill the plurality of second metal contact holes T2 to form a plurality of metal lines 118. Figure 15 As shown, each of the metal interconnect layers 119 is connected to the metal lines 118 in the adjacent dielectric layers (117, 120). If more dielectric layers are required, the process method in step five above can be referred to, and the attached... Figure 11-15 Continue to prepare the dielectric layer (117, 120), the metal line 118 and the metal interconnect layer 119.

[0089] After forming the isolation structure and several conductive interconnect structures, the method for fabricating the thyristor rectifier further includes: as follows: Figure 15 As shown, a first conductive layer 121 and a second conductive layer 122 are formed on the surface of the isolation structure, and the first conductive layer 121 is electrically connected to the first doped region 111 and the second doped region 114 via the conductive interconnect structure; the second conductive layer 122 is electrically connected to the third doped region 112 and the fourth doped region 115 via the conductive interconnect structure.

[0090] In one embodiment of this application, the first conductive layer 121 and the second conductive layer 122 are formed using a chemical vapor deposition process or sputtering. The first conductive layer 121 is the anode of the device, and the second conductive layer 122 is the cathode of the device. The anode is connected to the first doped region 111 and the second doped region 114 via a conductive interconnect structure, and the cathode is connected to the third doped region 112 and the fourth doped region 115 via a conductive interconnect structure.

[0091] In one embodiment of this application, when the silicon controlled rectifier is operating, the cathode is grounded. When an ESD positive pulse occurs at the anode, the junctions between the first well region 107 and the second well region 109, and between the first well region 107 and the epitaxial layer 101, are reverse-biased. Because the ion doping concentration of the second well region 109 is higher than that of the epitaxial layer 101, the critical electric fields of the first well region 107 and the second well region 109 are lower. The ESD pulse energy first causes the PN junction to undergo avalanche breakdown. Then, the avalanche current passes through the first doped region 111, the first well region 107, the second well region 109, and the fourth doped region 115, and reaches the cathode through the conductive interconnect structure. Subsequently, a voltage drop is generated across the first well region 107 and the second well region 109. When the voltage drop reaches a set value, such as 0.7 volts, the PNP transistor formed by the second doped region 114, the first well region 107, and the second well region 109 turns on, or the NPN transistor formed by the first well region 107, the second well region 109, and the third doped region 112 turns on. When one transistor turns on, the ESD pulse increases, making it easier for the other transistor to turn on, thus causing both the PNP and NPN transistors to turn on, forming a positive feedback loop that turns on the entire thyristor rectifier. The first low-resistance region 103 and the second low-resistance region 105 reduce the on-resistance of the thyristor rectifier, thereby reducing the on-voltage and achieving a low-resistance path for ESD current discharge.

[0092] In summary, this embodiment provides a silicon controlled rectifier (SCR) and its fabrication method. By adding a first low-resistance region 103 and a second low-resistance region 105 to the SCR, and by placing the first low-resistance region 103 and the second low-resistance region 105 within the first well region 107 and the second well region 109 respectively, the junction capacitance of the first well region 107 and the second well region 109 is not affected. Furthermore, when the SCR is turned on, the first low-resistance region 103 and the second low-resistance region 105, due to their low resistance, reduce the overall resistance of the first well region 107 and the second well region 109, thereby reducing the on-state voltage of the device and improving the discharge current capability of the SCR. Moreover, the first low-resistance region 103 is located below the first doped region 111 and away from the second doped region 114; the second low-resistance region 105 is located below the fourth doped region 115 and away from the third doped region 112. Therefore, the first low-resistance region 103 does not affect the conduction of the transistor formed by the second doped region 114, the first well region 107, and the second well region 109, and the second low-resistance region 105 does not affect the conduction of the transistor formed by the first well region 107, the second well region 109, and the third doped region 112. Thus, the thyristor rectifier and its fabrication method provided in this application can reduce the on-state voltage of the thyristor rectifier without affecting its response speed.

[0093] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A silicon controlled rectifier, characterized in that, include: Substrate structure; A first well region is located in the substrate structure, and the first well region includes a first doped region and a second doped region; The second well region is located in the substrate structure, and the second well region includes a third doped region and a fourth doped region; A first low-resistivity region is located in the first well region, and the first low-resistivity region is disposed below the first doped region and away from the second doped region; The second low-resistivity region is located in the second well region and is disposed below the fourth doped region and away from the third doped region. An isolation structure is located on the surface of the substrate structure, and the isolation structure has a plurality of conductive interconnect structures.

2. The thyristor rectifier according to claim 1, characterized in that, The resistivity of the first low-resistivity region is less than that of the first well region, and the resistivity of the second low-resistivity region is less than that of the second well region.

3. The thyristor rectifier according to claim 1, characterized in that, The first low-resistivity region and the first well region have a first conductivity type; the second low-resistivity region and the second well region have a second conductivity type.

4. The thyristor rectifier according to claim 1 or 3, characterized in that, The ion doping concentration range in the first low-resistivity region and the second low-resistivity region is 1*10. 17 cm -3 ~1*10 18 cm -3 ; and / or, The ion doping concentration range in the first well region and the second well region is 1*10. 16 cm -3 ~1*10 17 cm -3 .

5. The thyristor rectifier according to claim 1, characterized in that, The thyristor rectifier further includes a fifth doped region; wherein the first well region and the second well region are adjacent to each other and both extend downward from the surface of the substrate structure, and the fifth doped region is disposed at the junction of the first well region and the second well region.

6. The thyristor rectifier according to claim 5, characterized in that, The first doped region and the third doped region have a first conductivity type; the second doped region, the fourth doped region and the fifth doped region have a second conductivity type; Wherein, the ion doping concentration in the first doped region, the second doped region, the third doped region, the fourth doped region, and the fifth doped region is greater than or equal to 1*10⁻⁶. 19 cm -3 .

7. The thyristor rectifier according to claim 1, characterized in that, The plurality of conductive interconnect structures include: multiple metal lines and multiple metal interconnect layers; The isolation structure includes at least two dielectric layers stacked on the surface of the substrate structure; wherein, each dielectric layer contains multiple metal lines, and multiple metal interconnect layers are spaced apart at the junction of two adjacent dielectric layers and are electrically connected to the multiple metal lines in the two adjacent dielectric layers respectively.

8. The thyristor rectifier according to claim 1, characterized in that, The thyristor rectifier also includes: A first conductive layer is located on the isolation structure, and the first conductive layer is electrically connected to the first doped region and the second doped region via the conductive interconnect structure; The second conductive layer is located on the isolation structure and spaced apart from the first conductive layer. The second conductive layer is electrically connected to the third doped region and the fourth doped region via the conductive interconnect structure.

9. The thyristor rectifier according to claim 1, characterized in that, The substrate structure includes a substrate and an epitaxial layer located on the surface of the substrate; wherein the ion doping concentration in the epitaxial layer is less than the ion doping concentration in the substrate.

10. A method for fabricating a silicon controlled rectifier, characterized in that, include: Provide a base structure; A first low-resistivity region, a second low-resistivity region, a first well region, and a second well region are formed in the substrate structure; wherein the first low-resistivity region is located in the first well region, and the second low-resistivity region is located in the second well region; A first doped region and a second doped region are formed in the first well region, and a third doped region and a fourth doped region are formed in the second well region; wherein, the first low-resistivity region is located below the first doped region and away from the second doped region; the second low-resistivity region is located below the fourth doped region and away from the third doped region; An isolation structure is formed on the surface of the substrate structure, and a plurality of conductive interconnect structures are formed in the isolation structure.

11. The method for preparing a thyristor rectifier according to claim 10, characterized in that, The provided structure is a substrate structure; The substrate structure includes a first low-resistivity region, a second low-resistivity region, a first well region, and a second well region, comprising: Provide a substrate; A first epitaxial layer is formed on the surface of the substrate; A first low-resistivity region, a second low-resistivity region, a first well region, and a second well region are formed in the first epitaxial layer.

12. The method for preparing a thyristor rectifier according to claim 10, characterized in that, The provided structure is a substrate structure; The substrate structure includes a first low-resistivity region, a second low-resistivity region, a first well region, and a second well region, comprising: Provide a substrate; A first epitaxial layer is formed on the surface of the substrate; A first low-resistivity region and a second low-resistivity region are formed in the first epitaxial layer; A second epitaxial layer is formed on the surface of the first epitaxial layer; A first well region and a second well region are formed in the first epitaxial layer and the second epitaxial layer.

13. The method for preparing a thyristor rectifier according to claim 10, characterized in that, Before forming the isolation structure and the conductive interconnect structure, a fifth doped region is formed at the junction of the first well region and the second well region.

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