Memory device crossbar matrix parity check

Abstract

The present application relates to cross-matrix parity checking in a memory device. Methods, devices, and systems related to cross-matrix parity checking in a memory device are described. In an example, a first set of parity data sets may be generated, each of which protects data stored in a row of memory cells in an array. Furthermore, a second set of parity data sets may be generated, each of which protects data stored in a column of memory cells in the array. The first and second parity data sets may be sent to a host for further ECC processing. The host may provide ECC data to the memory device based on the first and second parity data sets. The memory device may repair memory cells, disable memory cells, and the like based on the provided ECC data.

Description

Technical Field

[0001] The present disclosure generally relates to memory device crossbar matrix parity checking. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes random access memory (RAM), DRAM, and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory may provide permanent data by retaining stored data when power is not supplied, and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.

[0003] Memory is also used in a wide range of electronic applications as both volatile and nonvolatile data storage devices. For example, nonvolatile memory can be used in personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in arrays, where the arrays are used in memory devices.

[0004] The memory may be part of a memory module, such as a dual in-line memory module (DIMM), used in a computing device. For example, the memory module may include volatile memory, such as DRAM, and / or non-volatile memory, such as flash memory or RRAM. The DIMM may be used as main memory in a computing system. Summary of the Invention

[0005] Aspects of the present disclosure provide a memory device using cross-matrix parity, wherein the memory device includes: an array of memory cells; a control circuit system coupled to the array, wherein the control circuit system is configured to: generate a first plurality of parity data sets, each of which protects data stored in a row of memory cells in the array; generate a second plurality of parity data sets, each of which protects data stored in a column of memory cells in the array; send the first plurality of parity sets and the second plurality of parity sets to a host; and receive ECC data from the host based on the first plurality of parity data sets and the second plurality of parity data sets.

[0006] Another aspect of the present disclosure provides a method for using a memory device for cross-matrix parity checking, wherein the method includes: performing a parity check operation on a first data set of a plurality of memory cells via a control circuit system, the plurality of memory cells being coupled to access lines of an array that generate a first parity data set, the first parity data set corresponding to each of the access lines that generate access line parity data; performing an additional parity check operation on a second data set of a plurality of memory cells via the control circuit system, the plurality of memory cells being coupled to sense lines of the array that generate a second parity data set, the second parity data set corresponding to each of the sense lines that generate sense line parity data; sending the access line parity data and the sense line parity data to a host; receiving an instruction to perform an error correction operation on at least a portion of the plurality of memory cells based on the access line parity data set and the sense line parity data; and performing the error correction operation on the at least a portion of the plurality of memory cells.

[0007] Another aspect of the present disclosure provides a system using crossbar parity checking, wherein the system includes: a host; and a memory device coupled to the host, the memory device including: an array of memory cells; and control circuitry coupled to the array, wherein the control circuitry is configured to: perform a parity check operation on a first data set of a plurality of memory cells, the plurality of memory cells being coupled to access lines of the array that generate a first parity data set, the first parity data set corresponding to each of the access lines that generate access line parity data; perform an additional parity check operation on a second data set of the plurality of memory cells; The invention further comprises a method for storing an access line parity data set in a memory device, wherein the plurality of memory cells are coupled to sense lines of the array that generate a second parity data set, the second parity data set corresponding to each of the sense lines that generate sense line parity data; and sending the access line parity data and the sense line parity data to the host; wherein the host is configured to: receive the access line parity data and the sense line parity data; and generate an instruction to perform an error correction operation on at least a portion of the plurality of memory cells based on the access line parity data set and the sense line parity data; and send the instruction to the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a device in the form of a computing system including a memory system according to various embodiments of the present disclosure.

[0009] Figure 2A Schematic diagram illustrating a portion of a memory array according to various embodiments of the present disclosure.

[0010] Figure 2B Schematic diagram illustrating a portion of a memory array for crossbar matrix parity checking according to various embodiments of the present disclosure.

[0011] Figure 3 is a flow chart of a method for cross-matrix parity check in a memory device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] The present disclosure relates to methods, devices, and systems related to cross-matrix parity checking of memory devices. In an example, a first set of parity data sets may be generated, each of which protects data stored in a row of memory cells (e.g., memory cells coupled to access lines) in an array. A second set of parity data sets may be generated, each of which protects data stored in a column of memory cells (e.g., memory cells coupled to sense lines) in an array. The first and second parity data sets may be sent to a host for further ECC processing. The host may provide ECC data to the memory device based on the first and second parity data sets. The memory device may repair memory cells, disable memory cells, etc. based on the provided ECC data.

[0013] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device (also known as flash memory technology). Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. A block refers to a unit of a memory device for storing data hereinafter and may include a group of memory cells, a word line group, a word line, or an individual memory cell. For some memory devices, a block (also referred to as a "memory block" hereinafter) is the smallest erasable area. Pages cannot be erased individually, and only the entire block can be erased.

[0014] Each of the memory devices may include one or more memory cell arrays. Depending on the cell type, a cell may store one or more bits of binary information and have various logical states related to the number of bits stored. The logical state may be represented by a binary value, such as "0" and "1," or a combination of such values. There are various types of cells, such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC may store one bit of information and have two logical states.

[0015] Some NAND memory devices employ a floating gate architecture, in which memory access is controlled based on relative voltage changes between a bit line and a word line. Other examples of NAND memory devices may employ a replacement gate architecture, which may include the use of a word line layout that allows charge corresponding to the data value to be trapped within the memory cell based on the properties of the material used to construct the word line.

[0016] When a memory device is accessed a high number of times, memory cells storing data may experience failures (e.g., cells coupled to an access line) due to these repeated accesses to a particular row of memory cells. These intermittent failures caused by data errors can affect the reading of data and can be reduced by repairing the data, reading and writing the data additional times, changing the timing and / or voltage associated with the memory cells, disabling damaged memory cells, and the like. The number of errors in a row of memory cells can be determined by using parity data that protects both the row of memory cells (e.g., horizontal parity data) and the column of memory cells (e.g., vertical parity data). By doing so, the rows of memory cells experiencing errors, or the data stored in those rows of memory cells containing errors, can be located within the memory device because the cross-matrix parity data can help pinpoint the more precise location of the error stored in the memory cell. Analysis of the horizontal and vertical parity data can be performed by the host, allowing various memory devices to be used with cross-matrix parity settings without modifying or altering the memory device beyond some setup and / or software changes. Additionally, performing error correction on the data can reduce the bit error rate (BER) and improve the reliability of the data.

[0017] By performing these methods on memory cells storing data with a threshold number (or numbers) of errors, the number of errors in the data stored in the memory cells can be maintained below a level at which the memory can no longer be corrected. For example, an error correction method and / or system can be limited to the number of correctable data bits and / or portions that the method or system can correct. Once a memory array or a single row of cells exceeds these limits, the memory array can become uncorrectable. By maintaining the error rate below the threshold, the memory array can remain correctable.

[0018] ECC operations may include generating parity data, for example, by performing XOR and / or RAID operations on data stored in memory cells of an array. The parity data may be stored in (e.g., written to) volatile and / or non-volatile memory devices. In some examples, the parity data may be embedded in the data in the volatile and / or non-volatile memory devices.

[0019] Data stored in volatile and / or nonvolatile memory devices can be reconstructed using parity data. A host and / or a controller of the memory device can receive (e.g., read) parity data from the memory device and reconstruct the data in response to a read failure. The read failure can be due to memory corruption in the memory device.

[0020] In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part of the present disclosure, and the drawings show in an illustrative manner how to practice multiple embodiments of the present disclosure. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of the present disclosure, and it should be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators "M", "N", "X", and "Y" indicate that multiple specific features so specified may be included with multiple embodiments of the present disclosure.

[0021] As used herein, "a plurality of" something may refer to one or more of such things. For example, a plurality of memory cells may refer to one or more memory cells. Additionally, as used herein, designators such as "M," "P," and "J," particularly with respect to reference numerals in the drawings, indicate that a plurality of the particular feature so designated may be included with various embodiments of the present disclosure.

[0022] The figures herein follow a numbering convention in which the first digit or the first few digits correspond to the figure number of the diagram and the remaining digits identify the elements or components in the diagram. Similar elements or components between different figures can be identified by using similar digits. As will be appreciated, the elements shown in the various embodiments herein can be added, exchanged, and / or eliminated to provide multiple additional embodiments of the present disclosure. In addition, the proportions and relative scales of the elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not intended to be limiting.

[0023] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120, according to various embodiments of the present disclosure. As used herein, the memory device 120, the memory array 130, and / or the logic 140 (e.g., control logic), and / or the read / latch circuitry 150 may also be individually considered to be a "device."

[0024] System 100 includes a memory controller 102 coupled (e.g., connected) to a memory device 120, which includes a memory array 130. An example of memory device 120 includes a NAND device. In various embodiments, the NAND device includes an error correction code (ECC) capability implemented by an ECC component 115 of memory device 120. ECC component 115 may include error correction circuitry and / or components to perform multiple error corrections. An ECC engine (not illustrated) may be coupled to memory array 130 to correct errors when data is read from memory array 130 through an output buffer.

[0025] Memory controller 102 may be coupled to host 102. Host 102 may be a host system, such as a personal laptop computer, desktop computer, digital camera, smartphone, or memory card reader, among various other types of hosts. Host 102 may include a host controller external to memory device 120. Host controller 113 may include control circuitry, such as hardware, firmware, and / or software. In one or more embodiments, host controller 113 may be an application-specific integrated circuit (ASIC) coupled to a printed circuit board that includes a physical interface. Host 102 may include a system motherboard and / or backplane, and may include multiple processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry).

[0026] Host 102 may include an ECC component 117 configured to perform ECC operations and / or process parity data to determine locations or cells storing data containing errors. ECC component 117 may receive parity data for protecting both vertical and horizontal data and utilize this cross-matrix parity method to more effectively manage errors in memory array 130 of memory device 120.

[0027] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory array 130 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines. Although Figure 1 A single array 130 is shown in FIG, but embodiments are not limited thereto. For example, the memory device 120 may include multiple arrays 130 (e.g., multiple NAND cell rows or pages). The memory array 130 may include a row parity portion 145 toward the end of the row to store row parity data, as will be described below in conjunction with FIG. Figures 2A to 2BFurthermore, the memory array 130 can include a column parity portion 147 toward the bottom of a column of the array (as illustrated) to store column parity data, as will be further described below.

[0028] The memory device 120 may include control logic 140, such as hardware, firmware, and / or software. In one or more embodiments, the control logic 140 may be an application-specific integrated circuit (ASIC) coupled to a printed circuit board that includes the physical interface. In some embodiments, the control logic 140 may be a media controller, such as a DRAM memory controller or a non-volatile memory express (NVMe) controller. For example, the control logic 140 may be configured to perform operations such as copying, writing, reading, and error correction on the memory device 130. In addition, the controller 123 may include dedicated circuitry and / or instructions for performing the various operations described herein. That is, in certain embodiments, the control logic 140 may include circuitry and / or instructions that are executable to store the address (or location) of a row of memory cells that contains a specific number (or number) of errors. In some embodiments, the error correction code (ECC) circuitry 115 and / or instructions provided to the control logic 140 may control the execution of repair operations on a row of memory cells that contains a specific number (or number) of errors.

[0029] The memory array 130 may include additional rows or row portions or registers (e.g., "column parity" 147 or "row parity" 145) for storing parity data for a particular row or column of memory cells. A particular row of memory cells may be associated with parity data corresponding to the row of memory cells. As an example, an ECC operation may be performed and a parity value may be indicated to protect the row of cells. The parity data may be sent to the host 102 and in response to a message from the host to perform a repair operation based on the parity data, the address of the particular row may be accessed and the data in the memory cells in the row at the address may be repaired. In addition, the particular address of the row to be repaired may be added to a list for performing repair operations.

[0030] Memory device 120 includes address circuitry 142 for latching address signals provided via bus 154 (e.g., a data bus) via I / O circuitry 144. Address signals may also be sent by memory controller 102 and received by control logic 140 (e.g., via address circuitry 142 and / or via bus 154). Address signals are received and decoded by row decoder 146 and column decoder 152 to access memory array 130. Data may be read from memory array 130 by sensing voltage and / or current changes on data lines using read / latch circuitry 150. Read / latch circuitry 150 may read and latch a page (e.g., a row) of data from memory array 130. I / O circuitry 144 may be used for bidirectional data communication with host 110 via bus 154. Write circuitry 148 may be used to write data to memory array 130. Control logic 140 includes non-volatile memory ("NVM") 149, which can be used to store data from volatile memory in the event of a power outage or power cycle of memory device 120. While the example illustrates non-volatile memory 149 within control logic 140, examples are not limited thereto. Non-volatile memory 149 can be located at other addresses within memory device 120. In another such example, non-volatile memory 149 can be stored in a portion of memory array 130.

[0031] In some embodiments, control logic 140 decodes signals provided by memory controller 102 via bus 154. Although bus 154 is illustrated as a single bus that transmits address signals, bidirectional communications, decoded signals, and the like, embodiments are not limited thereto. For example, bus 154 may be divided into more than one bus, each designated for specific signals (e.g., a bus for address signals and / or commands, a bus for bidirectional communications, and the like). These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory array 130, including data read, data write, and data erase operations. In various embodiments, logic 140 is responsible for executing instructions from host 110. Logic 140 may be a state machine, a sequencer, or some other type of control circuitry. Logic 140 may be implemented in hardware, firmware, and / or software. Although logic 140 is illustrated as being coupled to specific components (e.g., memory array 130 and address circuitry 142), the controller may be coupled to any of the components within memory device 120.

[0032] Figure 2AA schematic diagram illustrating a portion of a memory array 219 according to various embodiments of the present disclosure. Array 219 includes memory cells (generally referred to as memory cells 203, and more specifically, 203-0 through 203-J) coupled to a plurality of rows of access lines 204-0, 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, ..., 204-P (generally referred to as access lines 204) and a plurality of columns of sense lines 205-0, 205-1, 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, ..., 205-D (generally referred to as sense lines 205). Each row of cells coupled to an access line is illustrated as ROW 0 221-0, indicating the first row of cells along access line 204-0, through ROW P 221-P. Furthermore, the memory array 219 is not limited to a particular number of access lines and / or sense lines, and the use of the terms "row" and "column" does not imply a particular physical structure and / or orientation of the access lines and / or sense lines. Although not shown, in some examples, each column of memory cells can be associated with a corresponding pair of complementary sense lines.

[0033] Each memory cell column (e.g., columns 223-0 to 223-11) can be coupled to sensing circuitry, such as sense amplifiers. In this example, the sensing circuitry can include a plurality of sense amplifiers (not illustrated) coupled to respective sense lines 205-0, 205-1, 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, ..., 205-D. The sense amplifiers can be coupled to input / output (I / O) lines (e.g., local I / O lines, not illustrated) via access devices (e.g., transistors, not illustrated).

[0034] If we combine the following Figure 2BFurther describing, the memory cell rows "ROW P-3" 221-8, "ROW P-2" 221-9, "ROW P-1" 221-10, and "ROW P" 221-P coupled to access lines 204-8, 204-9, 204-10, and 204-P can be used to store multiple parity data, wherein the parity data protects vertical data stored in the memory array 219. For example, data stored in the memory cell coupled to sense line 205-0 and access lines 204-0 through 204-7 (e.g., the first byte stored in the first cell column 223-0) can be vertically protected by the parity data stored in the memory cell coupled to sense line 205-0 and access lines 204-8 through 204-P (e.g., four vertically stored parity bits can protect eight vertically stored data bits). Although 8 bits of data and 4 bits of parity are described in this example, other examples are not limited to this. The number of data bits may exceed 8 bits, as indicated by the point between ROW 7 221-7 and ROWP-3 221-8.

[0035] Similarly, row parity bits can be stored in memory cells coupled to access lines 204-0 through 204-7 (in ROW 0 221-0 through ROW 7 221-7) and coupled to sense lines 205-A, 205-B, 205-C, and 205-D. In this way, data stored horizontally along the cells coupled to a particular access line 204 can be protected. For example, data stored in a memory cell coupled to access line 204-0 and coupled to sense lines 205-0 through 205-7 can be protected by parity data stored in memory cells coupled to access line 204-0 and coupled to sense lines 205-A, 205-B, 205-C, and 205-D (e.g., four horizontally stored parity bits stored at the end of a cell row will protect eight horizontally stored data bits stored in the same cell row). In this way, the vertical parity bits and the horizontal parity bits can together provide additional ECC protection.As an example, the data bits stored in cell 203-0 can be protected by two vertical parity bits and a horizontal parity bit.

[0036] Figure 2B A schematic diagram illustrating a portion of the memory array 219 - 2 for crossbar matrix parity checking according to various embodiments of the present disclosure. Figure 2B for Figure 2A1-1. Further description of the memory cell diagram is provided, wherein ROW 0 221-0 through P 221-P and COL 0 223-0 through COL 11 223-11 are illustrated, without individual memory cells for ease of reference and explanation. Each cell 221-0 through 221-7 stores a row of data (illustrated horizontally), such as DATA 0 227-0 through DATA 7 227-7. Each horizontally stored data set is protected by row parity data. For example, DATA 0 227-0 is horizontally protected by R0 Parity 231-0 stored in cells ROW 0 221-0 and COLUMNs 8 223-8 through 11 223-11. Each of the rows DATA 0 225-0 through DATA7 225-7 is protected by corresponding row parity data R0 231-0 through R7 231-7.

[0037] Similarly, each cell 223-0 through 223-7 stores data in columns (illustrated vertically), such as data 225-0 in "COL 0" 223-0 through data 225-7 in "COL 7" 223-7. Each vertically stored data set is protected by vertical parity data. For example, data 225-0 in "COL 0" 223-0 is vertically protected by Column 0 Group Parity ("C0 GP") 229-0, stored in cells "COL 0" 223-0 and ROWs "P-3" 221-8 through "P" 221-P. Similarly, vertical data is protected by each of C0 GP 229-0 through C7 GP 229-7, respectively.

[0038] Using multiple sets of horizontal parity data (R0 Parity 231-0 to R7 Parity 231-7) along with multiple sets of vertical parity data (C0 GP 229-0 to C7 GP 229-7) provides cross-matrix parity checking to more closely pinpoint the location of errors in memory cells. Additionally, when a threshold number of bit errors is reached or exceeded, a single horizontal parity value may not provide sufficient parity protection to recover the data. By adding in the vertical parity value, additional errors that would otherwise prevent the cell's data from being recovered can be corrected.

[0039] While processing memory devices (e.g. Figure 1While cross-matrix parity check values ​​in memory devices 120 (e.g., a memory device 120 in a host) can be advantageous, processing cross-matrix parity check values ​​can be prevented from being interchangeable using different memory devices without changing the memory device controller and other internal hardware and / or firmware components. By offloading the determination of cross-matrix parity check values ​​to the host, multiple different memory devices can be used without changing the memory controller and other components. For example, changing the memory device can use updated software or firmware, while the host still provides cross-matrix parity check functionality.

[0040] Figure 3 3 is a flow chart of a method 351 for cross-matrix parity checking in a memory device according to an embodiment of the present disclosure. In this example, the memory device is a NAND device. The method 351 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 351 is performed by Figure 1 The control logic 140 in the memory device 120 is executed in conjunction with the ECC component 115 in the host computer 117. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0041] At block 353, method 351 may include performing a parity operation on a first data set of a plurality of memory cells via the control circuitry. The plurality of memory cells may be coupled to access lines of an array that generate a first parity data set corresponding to each of the access lines that generate access line parity data. The plurality of memory cells may be located in a memory array (e.g., Figure 1 A parity operation may refer to an operation in which a parity value is determined by a data set.

[0042] At block 355, method 351 may include performing, via the control circuitry, an additional parity operation on a second set of data for the plurality of memory cells. The plurality of memory cells may be coupled to sense lines of the array that generate a second set of parity data corresponding to each of the sense lines that generate sense line parity data.

[0043] At block 357, method 351 may include sending the access line parity data and the sense line parity data to a host. The host may analyze the access line parity data and the sense line parity data to determine which error correction to perform. The host may use the access line parity data set to determine which memory cell coupled to a particular access line is storing data to be error corrected. The host may use the sense line parity data set to determine which memory cell coupled to a particular sense line is storing data to be error corrected. Based on the parity data corresponding to each of the access lines, the number of errors associated with the first data set may exceed a threshold error number. It may be determined that the first data set exceeds the threshold number. Based on the parity data corresponding to each of the sense lines, the number of errors associated with the second data set may exceed a threshold error number. It may be determined that the second data set exceeds the threshold number. The number of errors in the memory cells of a particular cell row may be determined using both the first parity data set and the second parity data set.

[0044] At block 359, method 351 may include receiving an instruction to perform an error correction operation on at least a portion of the plurality of memory cells based on the access line parity data and the sense line parity data. The instruction may be received by the memory device and sent by the host. The error correction operation may be performed on the memory cells corresponding to at least one of the stored row addresses. The repair operation may include correcting a certain number of errors. In some examples, the repair operation may include changing a voltage of a cell associated with the address or changing an access time of the cell associated with the address.

[0045] At block 361, the method may include performing an error correction operation on at least a portion of a plurality of memory cells. The error correction operation may be performed by an ECC component of the memory device. For example, a host may send a command indicating which row of memory to correct and / or retire (e.g., no longer use). In response, the memory device may correct the data stored in the indicated row of memory cells.

[0046] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that arrangements intended to achieve the same results may be substituted for the specific embodiments shown. The present invention is intended to cover modifications or variations of the various embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative manner and not a restrictive manner. After reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will become immediately apparent to those skilled in the art. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined by reference to the appended claims together with the entire scope of equivalents to which such claims are entitled.

[0047] In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure must utilize more features than are expressly recited in each claim. Rather, as the appended claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. The appended claims are therefore hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A memory device comprising: memory cell array; control circuitry coupled to the array, wherein the control circuitry is configured to: generating a first plurality of parity data sets, each of the first plurality of parity data sets protecting data stored in a row of memory cells of the array; generating a second plurality of parity data sets, each of the second plurality of parity data sets protecting data stored in a column of memory cells of the array; sending the first plurality of parity sets and the second plurality of parity sets to a host; and receiving ECC data from the host based on the first plurality of parity data sets and the second plurality of parity data sets; The host generates the ECC data using a cross-matrix parity value, and generates the cross-matrix parity value using the first plurality of parity data sets and the second plurality of parity data sets.

2. The memory device of claim 1, wherein the first plurality of parity data sets are used to determine that a row of memory cells of the array includes a number of errors exceeding a threshold number of errors.

3. The memory device of claim 1, wherein the second plurality of parity data sets are used to determine whether a column of memory cells of the array includes a number of errors exceeding a threshold number of errors.

4. The memory device of claim 1 , wherein the control circuitry is further configured to: A request is received from a host to perform a repair operation on at least a portion of the memory cells of the array using the second plurality of parity data sets.

5. The memory device of claim 4, wherein the control circuitry is configured to perform the repair operation independent of receiving data from ECC components within the memory device.

6. A method for operating a memory device, comprising: performing, via control circuitry, a parity check operation on a first data set of a plurality of memory cells coupled to access lines of an array that generate a first data set of parity data, the first parity data set corresponding to each of the access lines that generate access line parity data; performing, via a host, an additional parity operation on a second set of data for a plurality of memory cells coupled to sense lines of the array that generate a second set of parity data, the second set of parity data corresponding to each of the sense lines that generate sense line parity data; sending the access line parity data and the sense line parity data to the host; generating, by the host, a cross-matrix parity value using the access line parity data and the sense line parity data, and generating a command using the cross-matrix parity value; receiving, at the control circuitry, from the host, the instruction to perform an error correction operation on at least a portion of the plurality of memory cells based on the cross-matrix parity value; and The error correction operation is performed on the at least a portion of the plurality of memory cells.

7. The method of claim 6, further comprising performing analysis on the access line parity data and the sense line parity data to determine which error correction to perform.

8. The method of claim 7, further comprising using the access line parity data to determine which memory cells coupled to which particular access lines are storing data to be error corrected.

9. The method of claim 7, further comprising using the sense line parity data to determine which memory cells coupled to which particular sense lines are storing data to be error corrected.

10. The method of claim 6, further comprising determining, based on the access line parity data corresponding to each of the access lines, that a number of errors associated with the first data set exceeds a threshold number of errors. 11 . The method of claim 6 , further comprising determining, based on the sense line parity data corresponding to each of the sense lines, that a number of errors associated with the second data set exceeds a threshold number of errors.

12. The method of claim 6, further comprising determining a number of errors by using both the first set of parity data and the second set of parity data.

13. The method of claim 10, further comprising performing the error correction operation in response to receiving the instruction from a host.

14. The method of claim 6, wherein the array is an array of flash memory cells.

15. A memory system comprising: Host; and a memory device coupled to the host, the memory device comprising: a memory cell array; and control circuitry coupled to the array, wherein the control circuitry is configured to: performing a parity operation on a first data set of a plurality of memory cells coupled to access lines of an array that generate a first data set of parity data, the first parity data set corresponding to each of the access lines that generate access line parity data; performing an additional parity operation on a second set of data for a plurality of memory cells coupled to sense lines of the array that generate a second set of parity data, the second set of parity data corresponding to each of the sense lines that generate sense line parity data; and sending the access line parity data and the sense line parity data to the host; The host is configured to: receiving the access line parity data and the sensing line parity data; generating a cross-matrix parity value using a plurality of said first parity data sets and a plurality of said second parity data sets; generating instructions to perform an error correction operation on at least a portion of the plurality of memory cells based on the access line parity data set and the sense line parity data using the cross-matrix parity value; and The instructions are sent to the memory device.

16. The memory system of claim 15, wherein the host is further configured to determine a number of memory cells of the array that store errors.

17. The memory system of claim 16, wherein the host is further configured to locate the number of memory cells of the array storing errors by combining results from the first and second parity data sets.

18. The memory system of claim 16, wherein the host is further configured to: The first set of parity data and the second set of parity data are used to determine that data stored in memory cells of the array contains errors.

19. The memory system of claim 18, wherein the host is further configured to send a message to the memory device to disable a row of memory cells storing data that includes an error.

20. The memory system of claim 15, wherein the memory device is configured to: receiving a request from the host to perform the error correction operation; retrieving an address of a row of memory cells associated with an error count exceeding a threshold error count; and The error correction operation is performed on the memory cell at the address of the row of memory cells.

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