A signal detection circuit and a signal detection method

Abstract

Embodiments of the present application provide a signal detection circuit and a signal detection method. The signal detection circuit comprises a comparator and a voltage clamping module, a first input end of the comparator is electrically connected to a reference voltage, a second input end of the comparator is electrically connected to an output end of the voltage clamping module, and an input end of the voltage clamping module is electrically connected to a to-be-detected voltage signal. The voltage clamping module can generate a target detection voltage signal based on the to-be-detected voltage signal, and the comparator can compare the target detection voltage signal with the reference voltage with a voltage value change to obtain a comparison result. Since different voltage values of different to-be-detected voltage signals correspond to different application scenarios of the to-be-detected voltage signals, the application scenario of the to-be-detected voltage signal can be determined through the voltage value of the to-be-detected voltage signal, so that the detection of the application scenario of the to-be-detected voltage signal can be realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a signal detection circuit and a signal detection method. Background Technology

[0002] In integrated circuit applications, periodic voltage signals are frequently generated. Typically, the voltage value of these signals changes depending on the application scenario; for example, the voltage value may be positive or negative in different applications. However, the specific application scenario of the voltage signal cannot be determined using current technology. Therefore, it is necessary to design a technical solution that can detect the application scenario of the voltage signal. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide a signal detection circuit and signal detection method capable of detecting voltage signals in application scenarios.

[0004] In a first aspect of this application, a signal detection circuit is provided, comprising: a comparator and a voltage clamping module, wherein a first input terminal of the comparator is electrically connected to a reference voltage, a second input terminal of the comparator is electrically connected to the output terminal of the voltage clamping module, and an input terminal of the voltage clamping module is electrically connected to the voltage signal to be detected.

[0005] A voltage clamping module is used to generate a target detection voltage signal based on the voltage signal to be detected.

[0006] The comparator is used to compare the target detection voltage signal with a reference voltage whose voltage value changes, and obtain a comparison result. When the comparison result switches from a first signal to a second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected, and the comparison result is either the first signal or the second signal.

[0007] In one alternative embodiment, the comparator is further configured to generate a first signal if the reference voltage is greater than the target detection voltage signal, and to generate a second signal if the reference voltage is less than the target detection voltage signal.

[0008] In one alternative approach, if the voltage signal to be detected is a positive voltage signal, the target detection voltage signal is the voltage signal to be detected; if the voltage signal to be detected is a negative voltage signal, the target detection voltage signal is the product of the inverted signal of the voltage signal to be detected and the scaling factor of the voltage clamping module.

[0009] In one alternative embodiment, the voltage clamping module includes: a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a first resistor, a second resistor, a third resistor, and a current mirror unit;

[0010] The first terminal of the first field-effect transistor is grounded. The second terminal of the first field-effect transistor is electrically connected to the first terminal of the current mirror unit and the control terminal of the third field-effect transistor. The control terminal of the first field-effect transistor is electrically connected to the control terminal of the second field-effect transistor. The first terminal of the second field-effect transistor is electrically connected to the second terminal of the current mirror unit. The second terminal of the second field-effect transistor is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor. The second terminal of the first resistor is electrically connected to the voltage signal to be detected. The second terminal of the second resistor is electrically connected to the first terminal of the third field-effect transistor and the second input terminal of the comparator. The second terminal of the third field-effect transistor is electrically connected to the third terminal of the current mirror unit through the third resistor.

[0011] In one alternative embodiment, the current mirror unit includes a fourth field-effect transistor and a fifth field-effect transistor, wherein the first terminal of the fourth field-effect transistor is electrically connected to the second terminal of the first field-effect transistor, the control terminal of the fourth field-effect transistor is electrically connected to the control terminal of the fifth field-effect transistor, the first terminal of the fifth field-effect transistor, and the first terminal of the second field-effect transistor, respectively, and the second terminals of the fourth and fifth field-effect transistors are both electrically connected to a power supply.

[0012] In an alternative embodiment, the signal detection circuit further includes: a digital-to-analog converter, the output of which is electrically connected to the first input of a comparator, the first input of which is electrically connected to an input analog signal, and the second input of which is electrically connected to a digital signal;

[0013] A digital-to-analog converter is used to generate a reference voltage based on a digital signal and an input analog signal.

[0014] A second aspect of this application provides a signal detection method, which is applied to any signal detection circuit in the first aspect. The signal detection method includes:

[0015] Generate the target detection voltage signal based on the voltage signal to be detected;

[0016] The target detection voltage signal is compared with a reference voltage whose voltage value changes, and a comparison result is obtained. When the comparison result switches from the first signal to the second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected, and the comparison result is either the first signal or the second signal.

[0017] In one alternative approach, the comparison results are obtained, including:

[0018] If the reference voltage is greater than the target detection voltage signal, a first signal is generated;

[0019] If the reference voltage is less than the target detection voltage signal, a second signal is generated.

[0020] In one alternative approach, if the voltage signal to be detected is a positive voltage signal, the target detection voltage signal is the voltage signal to be detected; if the voltage signal to be detected is a negative voltage signal, the target detection voltage signal is the product of the inverted signal of the voltage signal to be detected and the scaling factor of the voltage clamping module.

[0021] In one alternative approach, before comparing the target detection voltage signal with a reference voltage of voltage change, the method further includes:

[0022] A reference voltage is generated based on the digital signal and the input analog signal.

[0023] This application provides a signal detection circuit and a signal detection method. The signal detection circuit includes a comparator and a voltage clamping module. The first input terminal of the comparator is electrically connected to a reference voltage, and the second input terminal of the comparator is electrically connected to the output terminal of the voltage clamping module. The input terminal of the voltage clamping module is electrically connected to the voltage signal to be detected. The voltage clamping module can generate a target detection voltage signal based on the voltage signal to be detected. The comparator can compare the target detection voltage signal with the reference voltage whose voltage value changes to obtain a comparison result. When the comparison result switches from the first signal to the second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected. Since different voltage values ​​of the voltage signals to be detected correspond to different application scenarios, the application scenario of the voltage signal to be detected can be determined by the voltage value of the voltage signal to be detected, thereby realizing the detection of the application scenario of the voltage signal.

[0024] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a signal detection circuit provided in an embodiment of this application;

[0027] Figure 2 A schematic diagram of a voltage signal to be detected provided in an embodiment of this application;

[0028] Figure 3A schematic diagram of another voltage signal to be detected provided in an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the structure of a voltage clamping module provided in an embodiment of this application;

[0030] Figure 5 A schematic diagram of a target detection voltage signal provided in an embodiment of this application;

[0031] Figure 6 A schematic diagram of another target detection voltage signal provided in an embodiment of this application;

[0032] Figure 7 This is a schematic diagram of another signal detection circuit provided in an embodiment of this application;

[0033] Figure 8 A schematic diagram of the reference voltage provided in the embodiments of this application;

[0034] Figure 9 A schematic flowchart of a signal detection method provided in an embodiment of this application;

[0035] Figure 10 This is a flowchart illustrating another signal detection method provided in an embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims and drawings of this application are intended to cover non-exclusive inclusion.

[0038] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0040] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0041] Furthermore, the terms "first," "second," etc., in the specification and claims of this application or in the aforementioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0042] In the description of this application, unless otherwise stated, "multiple" means two or more (including two), and similarly, "multiple groups" means two or more (including two groups).

[0043] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, "connection" or "linkage" in mechanical structures can refer to a physical connection, such as a fixed connection, for example, a connection fixed by fasteners, such as a connection fixed by screws, bolts, or other fasteners; a physical connection can also be a detachable connection, such as a snap-fit ​​or interlocking connection; a physical connection can also be an integral connection, such as a connection formed by welding, bonding, or integral molding. In circuit structures, "connection" or "linkage" can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is connected; it can also refer to the internal connection of two components. Signal connection can refer not only to signal connection through a circuit but also to signal connection through a media, such as radio waves. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0044] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0045] This application provides a signal detection circuit. (Refer to...) Figure 1 , Figure 1 This is a schematic diagram of a signal detection circuit provided in an embodiment of this application. Figure 1 As shown, the signal detection circuit includes a comparator and a voltage clamping module 20. The first input terminal of the comparator is electrically connected to the reference voltage VREFH, the second input terminal of the comparator is electrically connected to the output terminal of the voltage clamping module 20, and the input terminal of the voltage clamping module 20 is electrically connected to the voltage signal VDET to be detected.

[0046] The voltage clamping module 20 is used to generate a target detection voltage signal VDET_SNS based on the voltage signal to be detected VDET; the comparator is used to compare the target detection voltage signal VDET_SNS with the reference voltage VREFH whose voltage value changes, and obtain the comparison result VH_OUT; wherein, when the comparison result VH_OUT switches from the first signal to the second signal, the voltage value of the reference voltage VREFH is the voltage value of the voltage signal to be detected VDET, and the comparison result is the first signal or the second signal.

[0047] For example, Figure 2 This is a schematic diagram of a voltage signal to be detected, provided in an embodiment of this application. Figure 3 This is a schematic diagram of another voltage signal to be detected provided in an embodiment of this application. The voltage signal to be detected, VDET, may be as follows: Figure 2The positive voltage signal shown may also be, for example, Figure 3 the negative voltage signal shown.

[0048] For example, Figure 2 as shown, the voltage value of the voltage signal VDET to be detected can be V1, V2 or V3, where V1 < V2 < V3. The voltage value V1 corresponds to Application Scenario 1, the voltage value V2 corresponds to Application Scenario 2, and the voltage value V3 corresponds to Application Scenario 3, and Application Scenario 1, Application Scenario 2, and Application Scenario 3 are different application scenarios. Thus, when the voltage value of the voltage signal VDET to be detected is a positive voltage, different voltage values correspond to different application scenarios.

[0049] For example, Figure 3 as shown, the voltage value of the voltage signal VDET to be detected can be -V1, -V2 or -V3, where -V3 < -V2 < -V1. The voltage value -V1 corresponds to Application Scenario 4, the voltage value -V2 corresponds to Application Scenario 5, and the voltage value -V3 corresponds to Application Scenario 6, and Application Scenario 4, Application Scenario 5, and Application Scenario 6 are different application scenarios. Thus, when the voltage value of the voltage signal VDET to be detected is a negative voltage, different voltage values correspond to different application scenarios.

[0050] Thus, whether the voltage value of the voltage signal VDET to be detected is a positive voltage or a negative voltage, each voltage value of the voltage signal VDET to be detected corresponds to an application scenario of the voltage signal VDET to be detected. Therefore, based on the voltage value of the voltage signal VDET to be detected, the application scenario of the voltage signal VDET to be detected can be determined.

[0051] Exemplarily, Figure 4 FIG. Figure 4 is a schematic structural diagram of a voltage clamping module provided by an embodiment of the present application. As shown, the voltage clamping module 20 includes: a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a first resistor R1, a second resistor R2, a third resistor R3, and a current mirror unit 21.

[0052] The first terminal of the first field-effect transistor M1 is grounded. The second terminal of the first field-effect transistor M1 is electrically connected to the first terminal of the current mirror unit 21 and the control terminal of the third field-effect transistor M3. The control terminal of the first field-effect transistor M1 is electrically connected to the control terminal of the second field-effect transistor M2. The first terminal of the second field-effect transistor M2 is electrically connected to the second terminal of the current mirror unit 21. The second terminal of the second field-effect transistor M2 is electrically connected to the first terminal of the first resistor R1 and the first terminal of the second resistor R2. The second terminal of the first resistor R1 is electrically connected to the voltage signal to be detected, VDET. The second terminal of the second resistor R2 is electrically connected to the first terminal of the third field-effect transistor M3 and the second input terminal of the comparator. The second terminal of the third field-effect transistor M3 is electrically connected to the third terminal of the current mirror unit 21 through the third resistor R3. For example, the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are all NMOS transistors.

[0053] Among them, the current mirror unit 21 is as follows Figure 4 As shown, it includes a fourth field-effect transistor (FET) M4 and a fifth field-effect transistor (FET) M5. The first terminal of the fourth FET M4 is electrically connected to the second terminal of the first FET M1. The control terminal of the fourth FET M4 is electrically connected to the control terminal of the fifth FET M5, the first terminal of the fifth FET M5, and the first terminal of the second FET M2. The second terminals of both the fourth FET M4 and the fifth FET M5 are electrically connected to the power supply VDD. For example, both the fourth FET M4 and the fifth FET M5 are PMOS transistors.

[0054] Since the drain of the fourth field-effect transistor M4 is electrically connected to the drain of the first field-effect transistor M1, and the gate of the fourth field-effect transistor M4 is electrically connected to the gate and drain of the fifth field-effect transistor M5 respectively, the current mirror unit 21 can mirror the current of the second field-effect transistor M2 to the fourth field-effect transistor M4.

[0055] When the voltage signal to be detected, VDET, is a positive voltage signal, the voltage across the first terminal of the first resistor R1 is positive, meaning the source voltage of the second field-effect transistor M2 is positive, and the first terminal of the first field-effect transistor M1 is grounded, meaning the source voltage of the first field-effect transistor M1 is zero. Since the gate voltage of the first field-effect transistor M1 is the same as the gate voltage of the second field-effect transistor M2, the voltage difference VGS2 between the gate and source of the second field-effect transistor M2 is less than the voltage difference VGS1 between the gate and source of the first field-effect transistor M1. At this time, the current in the second field-effect transistor M2 is less than the current in the first field-effect transistor M1.

[0056] The current mirror unit 21 can mirror the current of the second field-effect transistor M2 to the fourth field-effect transistor M4, causing the drain voltage of the first field-effect transistor M1 to drop to 0V, which means the gate voltage of the third field-effect transistor M3 will drop to 0V, thus putting the third field-effect transistor M3 in an off state. At this time, the power supply VDD and the voltage signal to be detected VDET are not connected, and the second end of the second resistor R2 is at the same potential as the second end of the first resistor R1. Therefore, the target detection voltage signal VDET_SNS output from the second end of the second resistor R2 is the voltage signal to be detected VDET, that is, VDET_SNS = VDET.

[0057] When the voltage signal to be detected, VDET, is negative, the voltage across the first terminal of the first resistor R1 is negative, meaning the source voltage of the second field-effect transistor M2 is negative. The first terminal of the first field-effect transistor M1 is grounded, meaning its source voltage is zero. Therefore, the voltage difference VGS2 between the gate and source of the second field-effect transistor M2 is greater than the voltage difference VGS1 between the gate and source of the first field-effect transistor M1. At this time, the current in the second field-effect transistor M2 is greater than the current in the first field-effect transistor M1.

[0058] The current mirror unit 21 can mirror the current of the second field-effect transistor M2 to the fourth field-effect transistor M4, causing the drain voltage of the first field-effect transistor M1 to rise, which in turn raises the gate voltage of the third field-effect transistor M3, thus turning on the third field-effect transistor M3. At this time, the power supply VDD and the voltage signal to be detected VDET are connected, and the current output by the power supply VDD flows through the third field-effect transistor M3 to the first terminal of the first resistor R1, raising the voltage at the first terminal of the first resistor R1 until the voltage at the first terminal of the first resistor R1 rises to 0V, clamping the voltage at the first terminal of the first resistor R1.

[0059] The current in the second resistor R2 is VDET_SNS / R2, where R2 is the resistance of the second resistor. The current in the first resistor R1 is (0-VDET) / R1, where R1 is the resistance of the first resistor. Since the first resistor R1 and the second resistor R2 are connected in series, the current in the second resistor R2 is equal to the current in the first resistor R1, i.e., VDET_SNS / R2 = (0-VDET) / R1. Therefore, VDET_SNS = -VDET*R2 / R1, where -R2 / R1 can be understood as the scaling factor of the voltage clamping module 20. Thus, the target detection voltage signal VDET_SNS is the product of the inverted signal -VDET of the target voltage signal VDET and the scaling factor of the voltage clamping module 20.

[0060] Thus, if the voltage signal to be detected, VDET, is a positive voltage signal, such as Figure 5 As shown, Figure 5This is a schematic diagram of a target detection voltage signal provided in an embodiment of this application. The target detection voltage signal VDET_SNS is the voltage signal VDET to be detected. If the voltage signal VDET to be detected is a negative voltage signal, such as... Figure 6 As shown, Figure 6 This is a schematic diagram of another target detection voltage signal provided in an embodiment of this application. The target detection voltage signal VDET_SNS is the product of the inverted signal VDET (VDET) of the voltage signal to be detected and the scaling factor of the voltage clamping module 20. That is, regardless of whether the voltage signal VDET to be detected is a positive or negative voltage signal, the voltage clamping module 20 can convert the voltage signal VDET to be detected into a positive voltage signal adapted to the reference voltage VREFH, i.e., the target detection voltage signal VDET_SNS, so that the voltage signal VDET to be detected can be compared with the reference voltage VREFH.

[0061] For example, the reference voltage VREFH is variable, gradually decreasing from the initial voltage value vref to 0V in a stepwise manner. The difference between any two adjacent voltage values ​​of VREFH can be equal, and the duration of each voltage value can be equal. For instance, with an initial voltage value of 4V, the reference voltage VREFH values ​​are successively 4V, 3V, 2V, 1V, and 0V, with each voltage value maintained for 10ms.

[0062] Each time the reference voltage VREFH decreases, the comparator compares VREFH with the target detection voltage signal VDET_SNS and obtains the comparison result VH_OUT. The first input of the comparator is inverting, and the second input is non-inverting. When the reference voltage VREFH is at its initial value vref, it is greater than the target detection voltage signal VDET_SNS. The comparison result VH_OUT obtained by the comparator is the first signal, for example, a low-level signal. Figure 5 and Figure 6 As shown. The reference voltage VREFH is gradually decreased until it is less than the target detection voltage signal VDET_SNS. The comparison result VH_OUT obtained by the comparator is then the second signal. For example, the second signal is a high-level signal, such as... Figure 5 and Figure 6 As shown.

[0063] In summary, based on the reference voltage VREFH with its voltage change, the comparison result VH_OUT could be either the first signal or the second signal. At the moment the first signal transitions to the second signal, the voltage value of the reference voltage VREFH is equal to the voltage value of the target detection voltage signal VDET_SNS. The target detection voltage signal VDET_SNS can be understood as the detectable voltage signal VDET that can be compared and matched with the reference voltage VREFH. Therefore, the voltage value of the target detection voltage signal VDET_SNS is the same as the voltage value of the detectable voltage signal VDET.

[0064] In this embodiment, the signal detection circuit includes a comparator and a voltage clamping module. The first input terminal of the comparator is electrically connected to a reference voltage, and the second input terminal of the comparator is electrically connected to the output terminal of the voltage clamping module. The input terminal of the voltage clamping module is electrically connected to the voltage signal to be detected. The voltage clamping module can generate a target detection voltage signal based on the voltage signal to be detected. The comparator can compare the target detection voltage signal with the reference voltage whose voltage value changes to obtain a comparison result. When the detection result switches from the first signal to the second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected. Since different voltage values ​​of the voltage signals to be detected correspond to different application scenarios, the application scenario of the voltage signal to be detected can be determined by the voltage value of the voltage signal to be detected, thereby realizing the detection of the application scenario of the voltage signal.

[0065] In some embodiments, see Figure 7 As shown, Figure 7 This is a schematic diagram of another signal detection circuit provided in an embodiment of this application. The signal detection circuit further includes: a digital-to-analog converter 10, the output terminal of which is electrically connected to the first input terminal of a comparator, the first input terminal of which is electrically connected to the input analog signal VREF, and the second input terminal of which is electrically connected to the digital signal HDAC_IN. <n-1:0>.

[0066] Digital-to-analog converter 10, used for digital signal HDAC_IN <n-1:0>The input analog signal VREF is used to generate a reference voltage VREFH.

[0067] Digital signal HDAC_IN <n-1:0>It is a binary digital signal with a width of n, where n is a positive integer. The digital-to-analog converter 10 receives the digital signal HDAC_IN. <n-1:0>After inputting the analog signal VREF, the reference voltage VREFH can be calculated based on formula (1):

[0068] VREFH=O[HDAC_IN<n-1:0>]×VREF / 2 n (1)

[0069] Where O[HDAC_IN<n-1:0>] is the digital signal HDAC_IN <n-1:0>The result after converting to decimal.

[0070] Digital signal HDAC_IN <n-1:0>Subtract 1 from 1111...1111 (a total of n ones and 0 zeros) to get 1111...1110 (a total of n-1 ones and 1 zero), and continue subtracting 1 until the digital signal HDAC_IN is reached. <n-1:0>Decreasing to 0000...0000 (a total of 0 ones and n zeros). Figure 8 A schematic diagram of the reference voltage provided in the embodiments of this application, as shown below. Figure 8 As shown, the reference voltage VREFH is calculated by subtracting vref / 2 from the initial voltage value vref. n This continues until the reference voltage VREFH decreases to 0V.

[0071] Specifically, the i-th voltage value vref of the reference voltage VREFH i It can be calculated using formula (2):

[0072]

[0073] Where i∈(0~2 n ).

[0074] In summary, the digital-to-analog converter generates a reference voltage based on the digital signal and the input analog signal, thereby enabling the comparator to compare the reference voltage with the target detection voltage signal, making the operation simple and convenient.

[0075] Based on the same inventive concept, this application also provides a signal detection method applied to the signal detection circuit mentioned above. The solution provided by this method is similar to the implementation described in the signal circuit above. Therefore, the specific limitations in one or more signal detection method embodiments provided below can be found in the limitations of the signal detection circuit described above, and will not be repeated here.

[0076] In some embodiments, such as Figure 9 As shown, Figure 9 This is a flowchart illustrating a signal detection method provided in an embodiment of this application. This signal detection method can be applied to, for example... Figure 1 The specific steps in the signal detection circuit shown include:

[0077] S101. Generate a target detection voltage signal based on the voltage signal to be detected.

[0078] Wherein, if the voltage signal to be detected VDET is a positive voltage signal, the target detection voltage signal VDET_SNS is the voltage signal to be detected VDET. If the voltage signal to be detected VDET is a negative voltage signal, the target detection voltage signal VDET_SNS is the product of the inverted signal of the voltage signal to be detected VDET -VDET and the scaling factor of the voltage clamping module 20.

[0079] Thus, regardless of whether the voltage signal VDET to be detected is a positive or negative voltage signal, the generated target detection voltage signal VDET_SNS is a positive voltage signal, and the target detection voltage signal VDET_SNS can be adapted and compared with the reference voltage VREFH, so that the voltage signal VDET to be detected can be compared with the reference voltage VREFH.

[0080] S102. Compare the target detection voltage signal with the reference voltage that changes voltage value to obtain the comparison result.

[0081] When the comparison result VH_OUT switches from the first signal to the second signal, the voltage value of the reference voltage VREFH is the voltage value of the voltage signal VDET to be detected, and the comparison result VH_OUT is either the first signal or the second signal.

[0082] A possible implementation of S102 is described as follows: if the reference voltage VREFH is greater than the target detection voltage signal VDET_SNS, a first signal is generated; if the reference voltage VREFH is less than the target detection voltage signal VDET_SNS, a second signal is generated.

[0083] The reference voltage VREFH changes gradually, decreasing from its initial value vref to 0V in a stepwise manner. Each time VREFH decreases, the comparator compares VREFH with the target detection voltage signal VDET_SNS and obtains the comparison result VH_OUT. The comparator's first input is inverting, and its second input is non-inverting. When VREFH is at its initial value vref, it is greater than the target detection voltage signal VDET_SNS, and the comparison result VH_OUT is the first signal, for example, a low-level signal. As VREFH gradually decreases until it becomes less than the target detection voltage signal VDET_SNS, the comparison result VH_OUT is the second signal, for example, a high-level signal.

[0084] Thus, the comparison result VH_OUT obtained based on the reference voltage VREFH, which changes in voltage value, may be either the first signal or the second signal. At the moment when the first signal transitions to the second signal, the voltage value of the reference voltage VREFH is equal to the voltage value of the target detection voltage signal VDET_SNS. Since the target detection voltage signal VDET_SNS is the detectable voltage signal VDET that can be compared with the reference voltage VREFH, the voltage value of the target detection voltage signal VDET_SNS is the same as the voltage value of the detectable voltage signal VDET.

[0085] The signal detection method provided in this application generates a target detection voltage signal based on the voltage signal to be detected, and then compares the target detection voltage signal with a reference voltage whose voltage value changes to obtain a comparison result. When the comparison result switches from a first signal to a second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected. Since different voltage values ​​of the voltage signal to be detected correspond to different application scenarios, the application scenario of the voltage signal to be detected can be determined by its voltage value, thereby enabling the detection of the application scenario of the voltage signal.

[0086] Based on the above embodiments, Figure 10 A flowchart illustrating another signal detection method provided in this application embodiment is shown below. Figure 10 As shown, before executing S102 and comparing the reference voltage VREFH and the target detection voltage signal VDET_SNS, the following steps are also included:

[0087] S201, Based on digital signal HDAC_IN <n-1:0>The input analog signal VREF is used to generate a reference voltage VREFH.

[0088] Among them, the digital signal HDAC_IN <n-1:0>It is a binary digital signal with a width of n, where n is a positive integer. The digital signal HDAC_IN <n-1:0>The input is 1111...1111 (n ones and zeros in total). After determining the reference voltage VREFH based on 1111...1111 (n ones and zeros in total), the digital signal HDAC_IN... <n-1:0>Subtracting 1 from 1111...1111 (a total of n ones and 0 zeros) results in 1111...1110 (a total of n-1 ones and 1 zero), and the reference voltage VREFH is determined again. Based on this, the digital signal HDAC_IN... <n-1:0>You can decrease the value by 1 each time until you reach the digital signal HDAC_IN. <n-1:0>Decreasing to 0000...0000 (a total of 0 ones and n zeros), the reference voltage VREFH can be obtained by subtracting vref / 2 from the initial voltage value vref. n This continues until the reference voltage VREFH decreases to 0V.

[0089] The embodiments of this application can be applied to, for example... Figure 6 In the signal detection circuit shown, the digital-to-analog converter in the signal detection circuit can execute S201, making the generation of the reference voltage VREFH simple and quick.

[0090] It should be noted that S201 can be executed before S101, such as... Figure 10 As shown, it can also be executed after S101, and this application embodiment does not impose specific restrictions on this.

[0091] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" as described in this application does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims listing several means, several units of these means may be embodied by the same item of hardware. The use of "first," "second," and "third," etc., does not indicate any order and these words should be interpreted as names. Unless otherwise specified, the steps in the above embodiments should not be construed as limiting the order of execution.

[0092] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A signal detection circuit, characterized in that, include: A comparator and a voltage clamping module are provided. The first input terminal of the comparator is electrically connected to a reference voltage, the second input terminal of the comparator is electrically connected to the output terminal of the voltage clamping module, and the input terminal of the voltage clamping module is electrically connected to the voltage signal to be detected. The voltage clamping module is used to generate a target detection voltage signal based on the voltage signal to be detected; wherein, if the voltage signal to be detected is a positive voltage signal, the target detection voltage signal is the voltage signal to be detected; if the voltage signal to be detected is a negative voltage signal, the target detection voltage signal is the product of the inverted signal of the voltage signal to be detected and the scaling factor of the voltage clamping module. The comparator is used to compare the target detection voltage signal with the reference voltage whose voltage value changes, and obtain a comparison result; wherein, when the comparison result switches from a first signal to a second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected, and the comparison result is either the first signal or the second signal.

2. The signal detection circuit according to claim 1, characterized in that, The comparator is further configured to generate the first signal if the reference voltage is greater than the target detection voltage signal, and to generate the second signal if the reference voltage is less than the target detection voltage signal.

3. The signal detection circuit according to claim 1, characterized in that, The voltage clamping module includes: a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a first resistor, a second resistor, a third resistor, and a current mirror unit; The first terminal of the first field-effect transistor is grounded. The second terminal of the first field-effect transistor is electrically connected to the first terminal of the current mirror unit and the control terminal of the third field-effect transistor. The control terminal of the first field-effect transistor is electrically connected to the control terminal of the second field-effect transistor. The first terminal of the second field-effect transistor is electrically connected to the second terminal of the current mirror unit. The second terminal of the second field-effect transistor is electrically connected to the first terminal of the first resistor and the first terminal of the second resistor. The second terminal of the first resistor is electrically connected to the voltage signal to be detected. The second terminal of the second resistor is electrically connected to the first terminal of the third field-effect transistor and the second input terminal of the comparator. The second terminal of the third field-effect transistor is electrically connected to the third terminal of the current mirror unit through the third resistor.

4. The signal detection circuit according to claim 3, characterized in that, The current mirror unit includes a fourth field-effect transistor and a fifth field-effect transistor. The first end of the fourth field-effect transistor is electrically connected to the second end of the first field-effect transistor. The control end of the fourth field-effect transistor is electrically connected to the control end of the fifth field-effect transistor, the first end of the fifth field-effect transistor, and the first end of the second field-effect transistor. The second ends of the fourth and fifth field-effect transistors are both electrically connected to a power supply.

5. The signal detection circuit according to any one of claims 1-4, characterized in that, Also includes: A digital-to-analog converter (DAC), wherein the output terminal of the DAC is electrically connected to the first input terminal of the comparator, the first input terminal of the DAC is electrically connected to an input analog signal, and the second input terminal of the DAC is electrically connected to a digital signal; The digital-to-analog converter is used to generate the reference voltage based on the digital signal and the input analog signal.

6. A signal detection method, characterized in that, The method is applied to the signal detection circuit as described in any one of claims 1-5, and the method includes: The target detection voltage signal is generated based on the voltage signal to be detected; wherein, if the voltage signal to be detected is a positive voltage signal, the target detection voltage signal is the voltage signal to be detected; if the voltage signal to be detected is a negative voltage signal, the target detection voltage signal is the product of the inverted signal of the voltage signal to be detected and the scaling factor of the voltage clamping module; The target detection voltage signal and the reference voltage with voltage value change are compared to obtain the comparison result; wherein, when the comparison result switches from the first signal to the second signal, the voltage value of the reference voltage is the voltage value of the voltage signal to be detected, and the comparison result is the first signal or the second signal.

7. The signal detection method according to claim 6, characterized in that, The comparison results obtained include: If the reference voltage is greater than the target detection voltage signal, the first signal is generated; If the reference voltage is less than the target detection voltage signal, the second signal is generated.

8. The signal detection method according to claim 6, characterized in that, Before comparing the target detection voltage signal with a reference voltage of voltage value change, the method further includes: The reference voltage is generated based on the digital signal and the input analog signal.

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