A coherent multichannel transceiver system and method based on RFSoC

Abstract

This invention relates to a coherent multichannel transceiver system and method based on RFSoC, belonging to the field of electronic information technology. Specifically, it is a coherent multichannel transceiver channel based on RFSoC, which can be used in radar system design and multichannel communication system design. This invention comprises a multichannel system consisting of multiple RFSoC boards. Each board uses an RFSoC chip to generate and receive multiple channels of signals. The multiple boards are interconnected through a main control timing module and a clock reference module, which provide clock reference signals and synchronization timing pulse signals. Within each board, the combination of the clock signal and the clock reference signal, along with a calibration and compensation module, achieves high-precision phase coherence and timing synchronization between the multiple boards. Each RFSoC internally achieves phase coherence of multiple transceiver channels through measurement and adjustment mechanisms.

Description

Technical Field

[0001] This invention relates to a coherent multichannel transceiver system and method based on RFSoC, belonging to the field of electronic information technology. Specifically, it is a coherent multichannel transceiver channel based on RFSoC, which can be used in radar system design and multichannel communication system design. Background Technology

[0002] In a typical data acquisition system, there are generally two parts: transmitting and receiving signals, to complete the transmission and acquisition of signals. However, with the continuous advancement of technology, system applications have become increasingly complex, and the single-transmitter-single-receiver system is no longer sufficient. This leads to the application of multi-channel systems. Multi-channel systems often contain multiple transmit and receive channels, and the required technologies become increasingly complex as the number of channels increases.

[0003] Traditional data acquisition often employs a DSP+FPGA solution, which complicates the system and increases design difficulty. As engineering applications become increasingly complex, this approach consumes significant resources and results in a large system size. Furthermore, storing large amounts of data requires additional interfaces to export the raw data for processing, which is inconvenient in practical use. With the continuous development of System-on-Chip (SoC), data converter modules are integrated into SoC chips to form RFSoCs, allowing direct sampling and reconstruction of analog signals at the RF level. This creates a complete and comprehensive analog-to-digital signal chain, effectively addressing the aforementioned problems.

[0004] Currently, in the application of multi-channel acquisition systems across various fields, ensuring data synchronization and consistency between each data converter, while minimizing system size and increasing reliability while maintaining consistency, is a pressing issue. Achieving data consistency and synchronization between multiple RFSoCs, and combining multiple RFSoC chips to increase the number of channels, are challenges faced by multi-channel acquisition systems in aerospace, military communications, electronic warfare, and mobile communications. Summary of the Invention

[0005] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a coherent multichannel transceiver system and method based on RFSoC, which can realize coherent synchronous processing of multichannel signal transmission and reception functions.

[0006] The technical solution of the present invention is as follows:

[0007] A coherent multichannel transceiver system based on RFSoC, the multichannel transceiver system includes a clock reference module, a main control timing module and N RFSoC boards;

[0008] Each RFSoC board includes a clock module, a first calibration compensation module, an embedded software module, and an RF data communication module.

[0009] The embedded software module includes a state control module, a second calibration compensation module, and a waveform data generation module;

[0010] The radio frequency data communication module includes an ADC module and a DAC module, which mainly perform the functions of digital-to-analog conversion and analog-to-digital conversion of signals;

[0011] The clock reference module is used to generate the coherent clock reference signal required by the system and output the generated coherent clock reference signal to the clock module of the RFSoC board.

[0012] The main control timing module is used to generate synchronous timing pulse signals and output the generated synchronous timing pulse signals to the first calibration compensation module of the RFSoC board.

[0013] The clock module is used to receive the coherent clock reference signal output by the clock reference module. The clock module is also used to receive the first control signal output by the state control module, and generate a working clock signal, a working reference signal, a sampling clock signal and a sampling reference signal according to the received coherent clock reference signal and the first control signal. The generated working clock signal, working reference signal, sampling clock signal and sampling reference signal are all output to the first calibration compensation module.

[0014] The first calibration compensation module is used to receive the working clock signal, working reference signal, sampling clock signal and sampling reference signal output by the clock module, and is also used to receive the synchronous timing pulse signal output by the main control timing module, the second control signal output by the state control module, and the calibration compensation signal output by the second calibration compensation module. After calibrating and compensating the received working clock signal, working reference signal, sampling clock signal, sampling reference signal, synchronous timing pulse signal and calibration compensation signal according to the received second control signal, it generates synchronous AD sampling clock, synchronous DA sampling clock and synchronous timing pulse signal, and outputs the generated synchronous AD sampling clock and synchronous timing pulse signal to the ADC module, and outputs the generated synchronous DA sampling clock and synchronous timing pulse signal to the DAC module.

[0015] The ADC module is used to receive the synchronous AD sampling clock and synchronous timing pulse signal output by the first calibration compensation module, and is also used to receive the third control signal output by the state control module, and to receive the analog signal after digital-to-analog conversion generated by the DAC module. Based on the third control signal, the received analog signal is converted into analog-to-digital signal and then outputs the waveform data after analog-to-digital conversion.

[0016] The DAC module is used to receive the synchronous AD sampling clock and synchronous timing pulse signal output by the first calibration compensation module, and is also used to receive the raw waveform data output by the wavelength data generation module, and to receive the third control signal output by the state control module. Based on the third control signal, the received raw waveform data is converted from digital to analog and then the converted analog signal is output to the ADC module.

[0017] The state control module is used to generate a first control signal to the clock module, a second control signal to the first calibration compensation module, and a third control signal to the DAC module and the ADC module.

[0018] The second calibration compensation module is used to generate a calibration compensation signal and output the generated calibration compensation signal to the first calibration compensation module.

[0019] The waveform data generation module is used to generate raw waveform data and output the generated raw waveform data to the DAC module.

[0020] A coherent multichannel transceiver method based on RFSoC, the method comprising the following steps:

[0021] The first step is to use a clock reference module to generate a coherent clock reference signal and output the generated coherent clock reference signal to the clock module of the RFSoC board;

[0022] The second step is to use the main control timing module to generate a synchronous timing pulse signal and output the generated synchronous timing pulse signal to the first calibration compensation module.

[0023] The third step involves using a clock module to receive the coherent clock reference signal output by the clock reference module and the first control signal output by the state control module. Based on the received coherent clock reference signal and the first control signal, a working clock signal, a working reference signal, a sampling clock signal, and a sampling reference signal are generated. The generated working clock signal, working reference signal, sampling clock signal, and sampling reference signal are all output to the first calibration compensation module.

[0024] The fourth step involves using the first calibration compensation module to receive the working clock signal, working reference signal, sampling clock signal, and sampling reference signal output by the clock module, as well as the synchronous timing pulse signal output by the main control timing module, the second control signal output by the status control module, and the calibration compensation signal output by the second calibration compensation module. Based on the received second control signal, the module calibrates and compensates the received working clock signal, working reference signal, sampling clock signal, sampling reference signal, synchronous timing pulse signal, and calibration compensation signal to generate synchronous AD sampling clock, synchronous DA sampling clock, and synchronous timing pulse signal. The generated synchronous AD sampling clock and synchronous timing pulse signal are then output to the ADC module, and the generated synchronous DA sampling clock and synchronous timing pulse signal are output to the DAC module.

[0025] The fifth step involves using the DAC module to receive the synchronous AD sampling clock and synchronous timing pulse signal output from the first calibration compensation module, as well as the raw waveform data output from the wavelength data generation module and the third control signal output from the state control module. Based on the third control signal, the received raw waveform data is converted from digital to analog and then the converted analog signal is output to the ADC module.

[0026] The sixth step involves using the ADC module to receive the synchronous AD sampling clock and synchronous timing pulse signal output from the first calibration compensation module, as well as the third control signal output from the state control module and the analog signal after digital-to-analog conversion generated by the DAC module. Based on the third control signal, the received analog signal is converted from analog to digital and then the waveform data after analog-to-digital conversion is output, thus completing the coherent multichannel transceiver function based on RFSoC.

[0027] Beneficial effects

[0028] This invention proposes a coherent multichannel transceiver channel technology based on RFSoC, which realizes the timing synchronization and phase coherence problems in multichannel systems. It solves the problem that as the number of channels increases, the system size and hardware design complexity increase, and the difficulty of signal synchronization and timing design also increases. It is easy to apply to the system, has a high degree of integration, high flexibility, strong versatility, miniaturization, and low power consumption, and has high engineering application value.

[0029] This invention discloses a coherent multichannel transceiver channel technology based on RFSoC, which is a coherent synchronization processing technology for realizing multichannel signal transmission and reception functions.

[0030] This invention discloses a coherent multichannel transceiver channel technology based on RFSoC, belonging to the field of electronic information technology. This invention consists of a multichannel system composed of multiple RFSoC boards. Each board realizes multichannel signal generation and multichannel signal reception through an RFSoC chip. The multiple boards provide clock reference signals and synchronization timing pulse signals through a main control timing module and a clock reference module. The boards use a combination of clock signals and clock reference signals, and a calibration compensation module to achieve high-precision phase coherence and timing synchronization between multiple boards. Each RFSoC achieves phase coherence of multiple transceiver channels through measurement and adjustment mechanisms. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the composition of the coherent multichannel transceiver channel system of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0033] A multi-channel system is composed of multiple RFSoC boards. In the multi-channel system, the main control timing module generates multiple synchronous timing pulse signals, and the clock reference module generates multiple coherent clock signals. Each synchronous timing pulse signal and each coherent clock signal are input to an RFSoC board.

[0034] In a multi-channel system, the main control timing module generates multiple synchronous timing pulse signals, which are then input to each RFSoC board. Since it's impossible to guarantee that all synchronous timing pulse signals are phase-synchronized upon power-up, a calibration and compensation module is used to achieve high-precision timing synchronization. This involves using the RFSoC's operating clock to capture a timing synchronization reference signal. Upon capturing the rising edge of the timing synchronization signal, the time difference between the timing reference signal and the timing synchronization signal is calculated, and the error is compensated into the timing synchronization signal to ensure synchronized timing processing.

[0035] In a multi-channel system, the clock signal output by the clock module and the reference signal are used to synchronize the operating clocks of multiple RF subsystems, and the operating clocks are frequency-locked and phase-aligned. The calibration and compensation module uses the MTS (Multi-tile Synchronization) algorithm to align the propagation delay from the RF data communication (RFDC) subsystem to the programmable logic (PL), calibrating and defining the time difference between channels. This quantitatively characterizes the difference in time at the same sampling point across different measurement channels, completing the calibration, compensation, and correction of inter-channel delays, and ensuring phase coherence processing across multiple channels.

[0036] This invention provides a coherent multichannel transceiver channel method based on RFSoC, comprising the following steps:

[0037] Step 1: System Architecture Design

[0038] The coherent multichannel transceiver channel technology based on RFSoC adopts an architecture design of hardware logic + embedded software co-processing. It utilizes the complete analog-to-digital signal links inside RFSoC and realizes the multichannel hardware architecture design through modular design, including a main control timing module, a clock reference module, a clock module, a calibration and compensation module, and a radio frequency data communication (RFDC) module. The software architecture is mainly applied on the embedded processor inside RFSoC and can be divided into waveform data generation module, state control module, and calibration and compensation module according to functional requirements.

[0039] Hardware architecture design

[0040] The coherent multichannel transceiver channel technology based on RFSOC achieves direct sampling of radio frequency through an integrated RFSoC chip, realizing multichannel waveform generation and acquisition functions based on RFSoC. The system hardware architecture consists of a main control timing module, a clock reference module, a clock module, a calibration and compensation module, and a radio frequency data communication (RFDC) module. First, the coherent multichannel technology based on RFSOC requires that the clock signal of the entire system originates from the same clock signal source. This signal source is generated by the clock reference module and input to the clock module, providing the system clock signal and reference signal. The generated signal undergoes synchronization and coherent processing by the calibration and compensation module, and is provided to the RF data communication module for transmitting and receiving multichannel data. The main control timing module provides timing signals to control the operation of each channel's ADC and DAC.

[0041] Software architecture design

[0042] The RFSOC-based coherent multichannel technology software architecture consists of three parts: a waveform data generation module, a state control module, and a calibration compensation module. These modules are primarily responsible for updating and calculating waveform data, controlling the operating state, and driving calibration compensation applications. The waveform data generation module generates waveform data and calculates the waveform data for each channel. The state control module provides auxiliary control for various tasks of the multichannel system. The calibration compensation module provides the calibration compensation algorithm driver to work in conjunction with the calibration compensation module in the hardware architecture, thereby achieving system synchronization and coherent processing.

[0043] Step 2: Timing synchronization technology for each board

[0044] The clock reference module uses a unified clock reference to generate coherent clock reference signals, which are used to generate the operating clock signal and reference reference signal of the RF on-chip system. These clocks are frequency-stable and are input from the clock reference module.

[0045] In a multi-channel system, the main control timing module generates multiple synchronous timing pulse signals, which are then input to each RFSoC board. Since it's impossible to guarantee that all synchronous timing pulse signals are phase-synchronized upon power-up, a calibration compensation mechanism is used to achieve high-precision timing synchronization. This involves using the RFSoC's operating clock to capture a timing synchronization reference signal. Upon capturing the rising edge of the timing synchronization signal, the time difference between the timing reference signal and the timing synchronization signal is calculated, and the error is compensated into the timing synchronization signal to ensure synchronized processing.

[0046] Step 3: Phase coherence technology between channels

[0047] Coherent multichannel transceiver channel technology requires phase coherence processing between channels and system synchronization of multiple radio frequency subsystems, which necessitates the synchronization of operating clock signals for each subsystem. When providing a clock for a radio frequency data communication (RFDC) subsystem, clock signal synchronization must be guaranteed; otherwise, random frequency drift from different sources will become unpredictable. Sampling clocks from different clock unit outputs can be accepted, but these clock signals must be frequency-locked and phase-aligned.

[0048] After ensuring the operating clock signal is frequency locked and phase aligned, the MTS (Mutil-tile Synchronization) algorithm is used to complete the propagation delay alignment from the RF data communication (RFDC) subsystem to the programmable logic (PL). Alignment across multiple RFDC module subsystems is achieved from one or more RFSoCs using a calibration compensation module.

[0049] The calibration compensation mechanism relies on the operating clock signal and the reference reference signal. The MTS aligns all synchronization blocks within the block and then adjusts the dual-clock FIFO interface between the alignment PL and the RF data communication (RFDC) subsystem via pointers. However, the use of the MTS requires not only the operating clock signals in both clock domains but also the reference reference signals in both regions to perform alignment.

[0050] The MTS transmits the rising edge of the reference clock signal from the RF Data Communication Module (RFDC) block to the PL via a FIFO. Once this rising edge is detected in the PL, the counter stops. The counter is reset by each rising edge of the reference clock signal in the PL and incremented by each word in the FIFO. Once the counter stops, the counter value represents the relative propagation delay (relative value) of the FIFO.

[0051] Running the same measurement on all selected blocks in the device, MTS finds that all FIFO blocks do not match, and then aligns them by adding an extra delay to ensure that the delay through each FIFO matches the maximum measured delay. When the system contains multiple RFSoCs, the system only needs to use MTS for each device to complete the phase coherence processing between channels.

[0052] Example

[0053] like Figure 1 As shown, a coherent multichannel transceiver system based on RFSoC is disclosed. The multichannel transceiver system includes a clock reference module, a main control timing module, and two RFSoC boards.

[0054] Each RFSoC board includes a clock module, a first calibration compensation module, an embedded software module, and an RF data communication module.

[0055] The embedded software module includes a state control module, a second calibration compensation module, and a waveform data generation module;

[0056] The radio frequency data communication module includes an ADC module and a DAC module, which mainly perform the functions of digital-to-analog conversion and analog-to-digital conversion of signals;

[0057] The clock reference module is used to generate the coherent clock reference signal required by the system and output the generated coherent clock reference signal to the clock module of the RFSoC board.

[0058] The main control timing module is used to generate synchronous timing pulse signals and output the generated synchronous timing pulse signals to the first calibration compensation module of the RFSoC board.

[0059] The clock module is used to receive the coherent clock reference signal output by the clock reference module. The clock module is also used to receive the first control signal output by the state control module, and generate a working clock signal, a working reference signal, a sampling clock signal and a sampling reference signal according to the received coherent clock reference signal and the first control signal. The generated working clock signal, working reference signal, sampling clock signal and sampling reference signal are all output to the first calibration compensation module.

[0060] The first calibration compensation module is used to receive the working clock signal, working reference signal, sampling clock signal and sampling reference signal output by the clock module, and is also used to receive the synchronous timing pulse signal output by the main control timing module, the second control signal output by the state control module, and the calibration compensation signal output by the second calibration compensation module. After calibrating and compensating the received working clock signal, working reference signal, sampling clock signal, sampling reference signal, synchronous timing pulse signal and calibration compensation signal according to the received second control signal, it generates synchronous AD sampling clock, synchronous DA sampling clock and synchronous timing pulse signal, and outputs the generated synchronous AD sampling clock and synchronous timing pulse signal to the ADC module, and outputs the generated synchronous DA sampling clock and synchronous timing pulse signal to the DAC module.

[0061] The ADC module is used to receive the synchronous AD sampling clock and synchronous timing pulse signal output by the first calibration compensation module, and is also used to receive the third control signal output by the state control module, and to receive the analog signal after digital-to-analog conversion generated by the DAC module. Based on the third control signal, the received analog signal is converted into analog-to-digital signal and then outputs the waveform data after analog-to-digital conversion.

[0062] The DAC module is used to receive the synchronous AD sampling clock and synchronous timing pulse signal output by the first calibration compensation module, and is also used to receive the raw waveform data output by the wavelength data generation module, and to receive the third control signal output by the state control module. Based on the third control signal, the received raw waveform data is converted from digital to analog and then the converted analog signal is output to the ADC module.

[0063] The state control module is used to generate a first control signal to the clock module, a second control signal to the first calibration compensation module, and a third control signal to the DAC module and the ADC module.

[0064] The second calibration compensation module is used to generate a calibration compensation signal and output the generated calibration compensation signal to the first calibration compensation module.

[0065] The waveform data generation module is used to generate raw waveform data and output the generated raw waveform data to the DAC module.

[0066] A coherent multichannel transceiver method based on RFSoC, the method comprising the following steps:

[0067] The first step is to use a clock reference module to generate a coherent clock reference signal and output the generated coherent clock reference signal to the clock module of the RFSoC board;

[0068] The second step is to use the main control timing module to generate a synchronous timing pulse signal and output the generated synchronous timing pulse signal to the first calibration compensation module.

[0069] The third step involves using a clock module to receive the coherent clock reference signal output by the clock reference module and the first control signal output by the state control module. Based on the received coherent clock reference signal and the first control signal, a working clock signal, a working reference signal, a sampling clock signal, and a sampling reference signal are generated. The generated working clock signal, working reference signal, sampling clock signal, and sampling reference signal are all output to the first calibration compensation module.

[0070] The fourth step involves using the first calibration compensation module to receive the working clock signal, working reference signal, sampling clock signal, and sampling reference signal output by the clock module, as well as the synchronous timing pulse signal output by the main control timing module, the second control signal output by the status control module, and the calibration compensation signal output by the second calibration compensation module. Based on the received second control signal, the module calibrates and compensates the received working clock signal, working reference signal, sampling clock signal, sampling reference signal, synchronous timing pulse signal, and calibration compensation signal to generate synchronous AD sampling clock, synchronous DA sampling clock, and synchronous timing pulse signal. The generated synchronous AD sampling clock and synchronous timing pulse signal are then output to the ADC module, and the generated synchronous DA sampling clock and synchronous timing pulse signal are output to the DAC module.

[0071] The fifth step involves using the DAC module to receive the synchronous AD sampling clock and synchronous timing pulse signal output from the first calibration compensation module, as well as the raw waveform data output from the wavelength data generation module and the third control signal output from the state control module. Based on the third control signal, the received raw waveform data is converted from digital to analog and then the converted analog signal is output to the ADC module.

[0072] The sixth step involves using the ADC module to receive the synchronous AD sampling clock and synchronous timing pulse signal output from the first calibration compensation module, as well as the third control signal output from the state control module and the analog signal after digital-to-analog conversion generated by the DAC module. Based on the third control signal, the received analog signal is converted from analog to digital and then the waveform data after analog-to-digital conversion is output, thus completing the coherent multichannel transceiver function based on RFSoC.

[0073] The above description, in conjunction with specific embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered within the scope of protection of the present invention.

Claims

1. A coherent multichannel transceiver system based on RFSoC, characterized in that: This multi-channel transceiver system includes a clock reference module, a main control timing module, and N RFSoC boards; Each RFSoC board includes a clock module, a first calibration compensation module, an embedded software module, and an RF data communication module. The embedded software module includes a status control module, a second calibration compensation module, and a waveform data generation module. The RF data communication module includes an ADC module and a DAC module. The clock reference module is used to generate the coherent clock reference signal required by the system and output the generated coherent clock reference signal to the clock module of the RFSoC board. The main control timing module is used to generate synchronous timing pulse signals and output the generated synchronous timing pulse signals to the first calibration compensation module of the RFSoC board. The clock module is used to receive the coherent clock reference signal output by the clock reference module. The clock module is also used to receive the first control signal output by the state control module, and generate a working clock signal, a working reference signal, a sampling clock signal and a sampling reference signal according to the received coherent clock reference signal and the first control signal. The generated working clock signal, working reference signal, sampling clock signal and sampling reference signal are all output to the first calibration compensation module. The first calibration compensation module is used to receive the working clock signal, working reference signal, sampling clock signal, and sampling reference signal output by the clock module. It is also used to receive the synchronous timing pulse signal output by the main control timing module, the second control signal output by the state control module, and the calibration compensation signal output by the second calibration compensation module. Based on the received second control signal, it performs calibration compensation on the received working clock signal, working reference signal, sampling clock signal, sampling reference signal, synchronous timing pulse signal, and calibration compensation signal to generate synchronous AD sampling clock, synchronous DA sampling clock, and synchronous timing pulse signal. The generated synchronous AD sampling clock and synchronous timing pulse signal are output to the ADC module, and the generated synchronous DA sampling clock and synchronous timing pulse signal are output to the DAC module.

2. The coherent multichannel transceiver system based on RFSoC according to claim 1, characterized in that: The ADC module is used to receive the synchronous AD sampling clock and synchronous timing pulse signal output by the first calibration compensation module, and is also used to receive the third control signal output by the state control module, and to receive the analog signal after digital-to-analog conversion generated by the DAC module. Based on the third control signal, the received analog signal is converted into analog-to-digital signal and then outputs the waveform data after analog-to-digital conversion.

3. The coherent multichannel transceiver system based on RFSoC according to claim 2, characterized in that: The DAC module is used to receive the synchronous AD sampling clock and synchronous timing pulse signal output by the first calibration compensation module, and also to receive the raw waveform data output by the wavelength data generation module, and to receive the third control signal output by the state control module. Based on the third control signal, it performs digital-to-analog conversion on the received raw waveform data and outputs the digital-to-analog converted analog signal to the ADC module.

4. The coherent multichannel transceiver system based on RFSoC according to claim 1, characterized in that: The state control module is used to generate a first control signal to the clock module, a second control signal to the first calibration compensation module, and a third control signal to the DAC module and the ADC module.

5. A coherent multichannel transceiver system based on RFSoC according to claim 1, characterized in that: The second calibration compensation module is used to generate a calibration compensation signal and output the generated calibration compensation signal to the first calibration compensation module.

6. A coherent multichannel transceiver system based on RFSoC according to claim 1, characterized in that: The waveform data generation module is used to generate raw waveform data and output the generated raw waveform data to the DAC module.

7. A coherent multichannel transceiver method based on RFSoC, characterized in that... The steps of this method include: The first step is to use a clock reference module to generate a coherent clock reference signal and output the generated coherent clock reference signal to the clock module of the RFSoC board; The second step is to use the main control timing module to generate a synchronous timing pulse signal and output the generated synchronous timing pulse signal to the first calibration compensation module. The third step involves using a clock module to receive the coherent clock reference signal output by the clock reference module and the first control signal output by the state control module. Based on the received coherent clock reference signal and the first control signal, a working clock signal, a working reference signal, a sampling clock signal, and a sampling reference signal are generated. The generated working clock signal, working reference signal, sampling clock signal, and sampling reference signal are all output to the first calibration compensation module. The fourth step involves using the first calibration compensation module to receive the working clock signal, working reference signal, sampling clock signal, and sampling reference signal output by the clock module, as well as the synchronous timing pulse signal output by the main control timing module, the second control signal output by the status control module, and the calibration compensation signal output by the second calibration compensation module. Based on the received second control signal, the module calibrates and compensates the received working clock signal, working reference signal, sampling clock signal, sampling reference signal, synchronous timing pulse signal, and calibration compensation signal to generate synchronous AD sampling clock, synchronous DA sampling clock, and synchronous timing pulse signal. The generated synchronous AD sampling clock and synchronous timing pulse signal are then output to the ADC module, and the generated synchronous DA sampling clock and synchronous timing pulse signal are output to the DAC module. The fifth step involves using the DAC module to receive the synchronous AD sampling clock and synchronous timing pulse signal output from the first calibration compensation module, as well as the raw waveform data output from the wavelength data generation module and the third control signal output from the state control module. Based on the third control signal, the received raw waveform data is converted from digital to analog and then the converted analog signal is output to the ADC module. The sixth step involves using the ADC module to receive the synchronous AD sampling clock and synchronous timing pulse signal output from the first calibration compensation module, as well as the third control signal output from the state control module and the analog signal after digital-to-analog conversion generated by the DAC module. Based on the third control signal, the received analog signal is converted from analog to digital and then the waveform data after analog-to-digital conversion is output, thus completing the coherent multichannel transceiver based on RFSoC.

Images