Reference current source

Abstract

This disclosure provides a reference current source, including: a first current generating module, including a first start-up circuit, a first pre-adjustment circuit, and a first current generating circuit; a second current generating module, including a second start-up circuit, a second pre-adjustment circuit, and a second current generating circuit; and a temperature compensation module, configured to be connected to the first current generating module and the second current generating module respectively, wherein the temperature compensation module is configured to superimpose the first current and the second current to obtain a reference current independent of absolute temperature.

Description

Technical Field

[0001] This disclosure relates to the field of analog integrated circuit design technology, and in particular to a reference current source. Background Technology

[0002] In electronic devices, a reference current source is a fundamental module that provides a current that remains constant regardless of process technology, temperature, or power supply voltage, and biases other analog circuit modules. Therefore, the quality of the reference current source determines the performance of other modules.

[0003] In related technologies, the power consumption of the reference current source is crucial to the overall power consumption of the device. Although many current sources operate in the subthreshold region, they require particularly large resistors or high-threshold devices, which increase costs. Furthermore, the power supply rejection ratio (PSRR) of the reference current source is an important consideration. In portable electronic devices, analog and digital modules are often integrated, and the frequent switching of digital devices introduces noise into the power supply. This noise affects the output of the reference current source, thus impacting the accuracy of the entire electronic device. Common methods to improve the PSRR of the reference current source include using a cascode structure in the analog module or using an amplifier. However, adding a cascode structure increases the power supply voltage without significantly improving the PSRR. Using an amplifier introduces additional power consumption and stability issues. Currently, to make the current generated by the current source insensitive to temperature, resistors with different temperature coefficients are often used to compensate for current variations with temperature. However, using resistors introduces matching problems, requiring extensive adjustments to obtain a temperature-independent current. Therefore, reference current sources in related technologies suffer from at least the following technical problems: low PSRR, high power consumption, and poor temperature coefficient. Summary of the Invention

[0004] To address the aforementioned issues, this disclosure provides a reference current source.

[0005] This disclosure provides a reference current source, including:

[0006] The first current generating module includes a first start-up circuit, a first pre-adjustment circuit, and a first current generating circuit. The first start-up circuit is configured to provide a first start-up signal to the first pre-adjustment circuit and a second start-up signal to the first current generating circuit. The first pre-adjustment circuit is configured to provide a first reference signal to the first start-up circuit and a first pre-adjustment voltage to the first current generating circuit. The first current generating circuit is configured to generate a first current that is complementary to the absolute temperature.

[0007] The second current generating module includes a second start-up circuit, a second pre-adjustment circuit, and a second current generating circuit. The second start-up circuit is configured to provide a third start-up signal to the second pre-adjustment circuit and a fourth start-up signal to the second current generating circuit. The second pre-adjustment circuit is configured to provide a second reference signal to the second start-up circuit and a second pre-adjustment voltage to the second current generating circuit. The second current generating circuit is configured to generate a second current proportional to the absolute temperature.

[0008] The temperature compensation module is configured to connect to the first current generating module and the second current generating module respectively. The temperature compensation module is configured to superimpose the first current and the second current to obtain a reference current that is independent of the absolute temperature.

[0009] According to embodiments of this disclosure, by sequentially arranging a startup circuit, a pre-regulation circuit, and a current generation circuit in the current generation module, the startup circuit can generate a startup signal to ensure that the pre-regulation circuit and the current generation circuit operate in the correct state. The pre-regulation circuit can generate a pre-regulation voltage, which can isolate the influence of noise in the power supply voltage on the current generation circuit, thereby enabling the current generated by the current generation circuit under the pre-regulation voltage to have a high power supply rejection ratio and linear modulation rate. On the other hand, the symmetrical arrangement of the first current generation module and the second current generation module can ensure good process stability of the reference current source. Furthermore, by connecting the first current generation module and the second current generation module through a temperature compensation circuit, the change of current with temperature can be compensated, thereby reducing the temperature coefficient of the reference current source. Through the above solution, the technical problems of low power supply rejection ratio and poor temperature coefficient existing in related technologies can be overcome at least partially, thereby effectively improving the power supply rejection ratio and linear modulation rate of the reference current source and reducing the temperature coefficient of the reference current source. Attached Figure Description

[0010] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a schematic diagram of the structure of a reference current source according to an embodiment of the present disclosure.

[0012] Figure 2 This is a schematic diagram of a first startup circuit according to an embodiment of the present disclosure.

[0013] Figure 3 This is a schematic diagram of a first current generating circuit according to an embodiment of the present disclosure.

[0014] Figure 4This is a schematic diagram of a first pre-adjustment circuit according to an embodiment of the present disclosure.

[0015] Figure 5 This is a schematic diagram of a second startup circuit according to an embodiment of the present disclosure.

[0016] Figure 6 This is a schematic diagram of a second current generating circuit according to an embodiment of the present disclosure.

[0017] Figure 7 This is a schematic diagram of a second pre-adjustment circuit according to an embodiment of the present disclosure.

[0018] Figure 8 This is a schematic diagram of a temperature compensation circuit according to an embodiment of the present disclosure.

[0019] Figure 9 This is a schematic diagram of the linear regulation rate of a reference current source according to an embodiment of the present disclosure.

[0020] Figure 10 This is a schematic diagram of the power supply rejection ratio of a reference current source according to an embodiment of the present disclosure.

[0021] Figure 11 This is a schematic diagram of the curve of reference current versus temperature according to an embodiment of the present disclosure.

[0022] Figure 12 This is a performance comparison diagram between a reference current source according to an embodiment of the present disclosure and a conventional reference current source. Detailed Implementation

[0023] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). Similarly, when using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0027] Embodiments of this disclosure provide a reference current source, comprising: a first current generation module, including a first startup circuit, a first pre-adjustment circuit, and a first current generation circuit, wherein the first startup circuit is configured to provide a first startup signal to the first pre-adjustment circuit and a second startup signal to the first current generation circuit, the first pre-adjustment circuit is configured to provide a first reference signal to the first startup circuit and a first pre-adjustment voltage to the first current generation circuit, and the first current generation circuit is configured to generate a first current complementary to absolute temperature; a second current generation module, including a second startup circuit, a second pre-adjustment circuit, and a second current generation circuit, wherein the second startup circuit is configured to provide a third startup signal to the second pre-adjustment circuit and a fourth startup signal to the second current generation circuit, the second pre-adjustment circuit is configured to provide a second reference signal to the second startup circuit and a second pre-adjustment voltage to the second current generation circuit, and the second current generation circuit is configured to generate a second current proportional to absolute temperature; and a temperature compensation module, configured to be connected to the first current generation module and the second current generation module respectively, the temperature compensation module being configured to superimpose the first current and the second current to obtain a reference current independent of absolute temperature. This reference current source has the characteristics of high power supply rejection ratio, small temperature coefficient and symmetrical circuit structure, which can at least partially overcome the defects and deficiencies of reference current sources in related technologies.

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of the structure of a reference current source according to an embodiment of the present disclosure.

[0030] like Figure 1As shown, the reference current source includes a first current generation module 100, a second current generation module 200, and a temperature compensation module 300.

[0031] According to embodiments of the present disclosure, the first current generating module 100 may include a first start-up circuit 110, a first pre-adjustment circuit 120, and a first current generating circuit 130 connected in sequence.

[0032] According to an embodiment of this disclosure, one end of the first startup circuit 110 can be configured to receive a power supply voltage V. dd The other end can be configured to be grounded. The first startup circuit 110 can be configured to receive the first reference signal V. ref1 And in the first reference signal V refl When the preset conditions are met, a first start signal V is provided to the first pre-adjustment circuit 120. stal and provides a second start signal V to the first current generating circuit 130. sta2 This preset condition can be set according to specific application scenarios. For example, the preset condition can be set to the first reference signal V. ref1 Low-level signals, etc., are not specified here.

[0033] According to embodiments of this disclosure, the first start-up circuit 110 can provide a first start-up signal V to the first pre-adjustment circuit 120 and the first current generation circuit 130, respectively. stal Second start signal V sta2 This ensures that the first pre-adjustment circuit 120 and the first current generation circuit 130 operate in the correct state.

[0034] According to embodiments of this disclosure, one end of the first pre-conditioning circuit 120 can be configured to receive a power supply voltage V. dd The other end can be configured to be grounded. The first pre-adjustment circuit 120 can be configured to provide the first reference signal V to the first start-up circuit 110. ref1 And provide a first pre-regulated voltage V1 to the first current generating circuit 130.

[0035] According to embodiments of this disclosure, the first pre-regulation circuit 120 can isolate the power supply voltage V. dd To mitigate noise interference, the first pre-adjustment voltage V1 generated by the first pre-adjustment circuit 120 is used to power the first current generating circuit 130, thus isolating the power supply voltage V. dd The noise in the circuit affects the first current generation circuit 130, thereby improving the power supply rejection ratio and line regulation of the reference current source.

[0036] According to embodiments of this disclosure, one end of the first current generating circuit 130 can be configured to receive a first pre-adjusted voltage V1, and the other end can be configured to be grounded. The first current generating circuit 130 can be configured to generate a first current I1 that is complementary to absolute temperature, i.e., a CTAT (complementary to absolute temperature) current. The magnitude of the first current I1 may be independent of the magnitude of the first pre-adjusted voltage V1.

[0037] According to embodiments of the present disclosure, the second current generating module 200 may include a second start-up circuit 210, a second pre-adjustment circuit 220, and a second current generating circuit 230 connected in sequence.

[0038] According to an embodiment of this disclosure, one end of the second startup circuit 210 can be configured to receive a power supply voltage V. dd The other end can be configured to be grounded. The second startup circuit 210 can be configured to receive the second reference signal V. ref2 And in the second reference signal V ref2 When the preset conditions are met, a third start signal V is provided to the second pre-adjustment circuit 220. sta3 and provides a fourth start signal V to the second current generating circuit 230. sta4 This preset condition can be set according to specific application scenarios. For example, this preset condition can be set to the second reference signal V. ref2 Low-level signals, etc., are not specified here.

[0039] According to embodiments of this disclosure, the second start-up circuit 210 can provide a third start-up signal V to the second pre-adjustment circuit 220 and the second current generation circuit 230, respectively. sta3 and the fourth start signal V sta4 This ensures that the second pre-conditioning circuit 220 and the second current generating circuit 230 operate in the correct state.

[0040] According to embodiments of this disclosure, one end of the second pre-conditioning circuit 220 can be configured to receive a power supply voltage V. dd The other end can be configured to be grounded. The second pre-adjustment circuit 220 can be configured to provide the second reference signal V to the second start-up circuit 210. ref2 And provide a second pre-regulated voltage V2 to the second current generating circuit 230.

[0041] According to embodiments of this disclosure, the second pre-regulation circuit 220 can isolate the power supply voltage V. dd To mitigate noise interference, the second pre-regulation voltage V2 generated by the second pre-regulation circuit 220 is used to power the second current generating circuit 230, thus isolating the power supply voltage V. ddThe noise in the circuit affects the second current generation circuit 230, thereby improving the power supply rejection ratio and linear regulation of the reference current source.

[0042] According to embodiments of this disclosure, one end of the second current generating circuit 230 can be configured to receive a second pre-adjusted voltage V2, and the other end can be configured to be grounded. The second current generating circuit 230 can be configured to generate a second current I2 that is proportional to the absolute temperature, i.e., a PTAT (Proportional to absolute temperature) current. The magnitude of this second current I2 may be independent of the magnitude of the second pre-adjusted voltage V2.

[0043] According to embodiments of this disclosure, one end of the temperature compensation module 300 can be configured to receive a power supply voltage V. dd The other end can be configured to be grounded. The temperature compensation module 300 can be configured to connect to the first current generation module 100 and the second current generation module 200 respectively. The temperature compensation module 300 can be configured to superimpose the first current I1 and the second current I2 to obtain a reference current I independent of absolute temperature. REF And output it.

[0044] According to embodiments of this disclosure, by sequentially arranging a startup circuit, a pre-regulation circuit, and a current generation circuit in the current generation module, the startup circuit can generate a startup signal to ensure that the pre-regulation circuit and the current generation circuit operate in the correct state. The pre-regulation circuit can generate a pre-regulation voltage, which can isolate the influence of noise in the power supply voltage on the current generation circuit, thereby enabling the current generated by the current generation circuit under the pre-regulation voltage to have a high power supply rejection ratio and linear modulation rate. On the other hand, the symmetrical arrangement of the first current generation module 100 and the second current generation module 200 can enable the reference current source to have better process stability. Furthermore, by connecting the first current generation module 100 and the second current generation module 200 through a temperature compensation circuit, the change of current with temperature can be compensated, thereby reducing the temperature coefficient of the reference current source. Through the above solution, the technical problems of low power supply rejection ratio and poor temperature coefficient existing in the related art can be overcome at least partially, thereby effectively improving the power supply rejection ratio and linear modulation rate of the reference current source and reducing the temperature coefficient of the reference current source.

[0045] The following is for reference. Figures 2 to 12 In conjunction with specific embodiments, Figure 1 The reference current source shown will be further explained.

[0046] According to embodiments of this disclosure, the reference current source may be manufactured using a deep submicron process, which may refer to processes such as the TSMC65NMLP process, and is not limited thereto.

[0047] Figure 2 This is a schematic diagram of a first startup circuit 110 according to an embodiment of the present disclosure.

[0048] like Figure 2 As shown, the first startup circuit 110 includes P-type field-effect transistors CMP1, CMP2, and CMP3, and N-type field-effect transistors CMN1, CMN2, and CMN3.

[0049] According to an embodiment of this disclosure, the gate of CMP1 is configured to receive a first reference signal V. ref1 The source of CMP1 is configured to be connected to the drain of CMP2, and the drain of CMP1 is configured to be connected to the gates of CMN2 and CMN3, respectively; the gate of CMP2 is configured to be connected to the drain of CMP2, and the source of CMP2 is configured to be connected to the drain of CMP3; the gate of CMP3 is configured to be connected to the drain of CMP3, and the source of CMP3 is configured to receive the power supply voltage V. dd The gate of CMN1 is configured to receive the first reference signal V. ref1 The source of CMN1 is configured to be grounded, and the drain of CMN1 is configured to be connected to the gates of CMN2 and CMN3, respectively; the source of CMN2 is configured to be grounded, and the drain of CMN2 is configured to provide a first start signal V. stal The source of CMN3 is configured to be grounded, and the drain of CMN3 is configured to provide the second startup signal V. sta2 .

[0050] According to embodiments of this disclosure, CMN1 and CMP1 are configured to form an inverter, in response to a first reference signal V. ref1 When in a low-level state, the inverter is configured to provide a high-level signal to the gates of CMN2 and CMN3 to control CMN2 and CMN3 to be in a conducting state, thereby enabling the first start-up signal V at the drain of CMN2. stal and the second startup signal V at the drain of CMN3 sta2 Both are in a low-level state, and this low-level start signal can control the first pre-adjustment circuit 120 and the first current generation circuit 130 to start. After the first pre-adjustment circuit 120 starts, it can control the first reference signal V. ref1 It is in a high-level state. The first reference signal V... ref1 When in a high-level state, the inverter is configured to provide a low-level signal to the gates of CMN2 and CMN3 to control CMN2 and CMN3 to be in a cut-off state. At this time, the field-effect transistors in the first startup circuit 110 are all in a cut-off state, and their power consumption is zero, thereby reducing the power consumption of the reference current source.

[0051] Figure 3 This is a schematic diagram of a first current generating circuit 130 according to an embodiment of the present disclosure.

[0052] like Figure 3 As shown, the first current generating circuit 130 includes a first feedback adjustment unit, a first current source unit, and a first bias voltage generating unit.

[0053] According to embodiments of this disclosure, a first current source unit includes N-type field-effect transistors CMP9 and CMP10, P-type field-effect transistors CMN9, CMN10, and CMN11, and a first capacitor C1. The first current source unit is configured to generate a first current I1. A first feedback adjustment unit includes an N-type field-effect transistor CMP8 and a P-type field-effect transistor CMN8. The first feedback adjustment unit is configured to control the drain voltage of CMN9 to be equal to the drain voltage of CMN10. A first bias voltage generation unit includes N-type field-effect transistors CMP11 and CMP12, and P-type field-effect transistors CMN12, CMN13, and CMN14. The first bias voltage generation unit is configured to generate a first bias signal V. biasl .

[0054] According to embodiments of this disclosure, the gates of CMP8, CMP9, CMP10, CMP11, and CMP12 are all configured to receive a second start signal V. str2 The sources of CMP8, CMP9, CMP10, CMP11, and CMP12 are all configured to receive a first pre-adjusted voltage V1. The drain of CMP8 is configured to be connected to the drain of CMN8. The drain of CMP9 is configured to be grounded through a first capacitor C1. The drain of CMP10 is configured to be connected to the drain of CMN10. The drain of CMP11 is configured to be connected to the drain of CMN12. The drain of CMP12 is configured to be connected to C... The drain of MN13; the gate of CMN8 is configured to be connected to the drain of CMP9, and the source of CMN8 is configured to be connected to the drain of CMN11; the gate of CMN9 is configured to be connected to the gate of CMN10, the source of CMN9 is configured to be grounded, and the drain of CMN9 is configured to be connected to the drain of CMP9; the source of CMN10 is configured to be connected to the drain of CMN11; the gate of CMN11 is configured to be connected to the gate of CMN12 to receive the first bias signal V. bias1 The source of CMN11 is configured to be grounded; the gate of CMN12 is configured to be connected to the drain of CMN12, and the source of CMN12 is configured to be connected to the drain of CMN14; the gate of CMN13 is configured to be connected to the gate of CMN14, and the source of CMN13 is configured to be connected to the drain of CMN14; the source of CMN14 is configured to be grounded.

[0055] According to embodiments of this disclosure, the channel length modulation effect can refer to the phenomenon in a MOS transistor where, after the gate channel is pre-pinched off, if Vds continues to increase, the pinch-off point will move slightly towards the source. This results in a slight decrease in the channel length between the pinch-off point and the source, and a slight decrease in the effective channel resistance. Consequently, more electrons drift from the source to the pinch-off point, leading to an increase in drifting electrons in the depletion region and an increase in Id. In related technologies, if the channel length of the MOS transistor is long enough, the current change caused by the channel length modulation effect can be ignored. However, due to the short channel length of the MOS transistor under deep submicron process conditions, the channel length modulation effect can no longer be ignored. Therefore, in embodiments of this disclosure, by introducing the first feedback adjustment unit, the drain voltage of CMN9 and the drain voltage of CMN10 can be controlled to be equal, as shown in formula (1):

[0056] V DS，CMN9 =V DS，CMN10 (1)

[0057] V DS，CMN9 V is the voltage difference between the drain and source of CMN9. DS，CMN10 This represents the voltage difference between the drain and source of the CMN10.

[0058] According to embodiments of this disclosure, by setting the first feedback adjustment unit, the current change caused by the channel length modulation effect can be compensated, thereby improving the power supply rejection ratio and linear regulation of the reference current source.

[0059] According to an embodiment of this disclosure, the reference current source circuit includes two loops: a positive feedback loop consisting of CMN8, CMP8, CMP9, and CMN9, and a negative feedback loop consisting of CMN8, CMP8, CMP10, CMN10, and CMN9.

[0060] The positive feedback loop gain is:

[0061]

[0062] A V1 For the positive feedback loop gain, g CMP8 For the conductivity of CMP8, g CMN8 For the conductivity of CMN8, g CMP9 For the conductivity of CMP9, R CMN11 r is the output resistance of CMN11. CMP8 r is the output resistance of CMP8 CMP9 r is the output resistance of CMP9 CMN9 This is the output resistor of CMN9.

[0063] The loop gain of the negative feedback loop is:

[0064]

[0065] A V2 For the negative feedback loop gain, g CMN9 For the conductivity of CMN9, g CMP10 For the conductivity of CMP10, g CMN10 For the conductivity of CMN10, r CMN10 This is the output resistance of CMN10.

[0066] If g CMP9 =g CMN9 The overall loop gain is:

[0067]

[0068]

[0069] A V This represents the overall loop gain.

[0070] According to embodiments of this disclosure, the loop of the reference current source can be configured as positive feedback, and the overall loop gain A of the loop is... V It can be configured as |A V |<1, thus avoiding circuit oscillation.

[0071] According to embodiments of this disclosure, for integrated circuit design, to minimize circuit power consumption, the transistor needs to be located in the weak inversion region, while to achieve a balance between speed and power consumption, the transistor needs to be located in the medium inversion region. In embodiments of this disclosure, to minimize the power consumption of the reference current source, the transistor needs to be located in the weak inversion region. The iV characteristic of a MOS transistor located in the weak inversion region is:

[0072]

[0073] C represents the aspect ratio of the transistor. ox V is the unit gate oxide capacitance, μ is the carrier mobility, and V is the voltage. T V is the thermal voltage, η is the subthreshold slope factor, and V DS V is the voltage difference between the drain and source. GS V is the voltage from the gate to the source. TH This is the threshold voltage.

[0074] If V DS For values ​​>100mV, the formula simplifies to the following:

[0075]

[0076]

[0077] Differentiate the formula:

[0078]

[0079] The following relationship can be obtained:

[0080]

[0081] g m It represents electrical conductivity.

[0082] According to embodiments of this disclosure, the temperature-compensated reference current source based on a current-adding circuit, in order to ensure sufficiently low power consumption, requires that, in addition to CMN11 operating in the deep linear region, all other transistors should be located in the weak inversion region. Operating CMN11 in the deep linear region is equivalent to a resistor, reducing the area occupied by the circuit structure.

[0083] The current in the branch is:

[0084]

[0085] V DS，CMP11 This represents the voltage difference between the drain and source of CMN11.

[0086] Because CMN11 is located in the deep linear region, the resistance in the linear region is:

[0087]

[0088] CMN9 and CMN10 are both located in the weak inversion region, so

[0089]

[0090] The branch current is:

[0091]

[0092] V GS，CMN11 V is the voltage difference between the gate and source of CMN11. TH，CMN11 W is the threshold voltage of CMN11. CMN11 L is the width of CMN11. CMN11 K is the length of CMN11. CMN9 For the aspect ratio of CMN9, K CMN10 The aspect ratio of CMN10.

[0093] V GS，CMN11 Provided by the bias voltage generation module:

[0094]

[0095] V GS，CMN12 V is the voltage difference between the gate and source of CMN12.GS，CMN13 V is the voltage difference between the gate and source of CMN13. GS，CMN14 V is the voltage difference between the gate and source of CMN14. TH，CMN14 K is the threshold voltage of CMN14. CMN12 For the aspect ratio of CMN12, K CMN13 The aspect ratio of CMN13.

[0096] Setting the channel lengths of CMN11 and CMN14 to be the same can minimize the threshold voltage variation caused by the channel length, and their threshold voltages can be regarded as approximately equal.

[0097] Therefore, the branch current is:

[0098]

[0099] Where μ is the carrier mobility. The thermal voltage of CMN10, The thermal voltage of CMN12, K CMN14 Given the aspect ratio of CMN14, μ varies with temperature as follows:

[0100]

[0101] μ0 is the carrier mobility at temperature T0, and m is the temperature coefficient.

[0102] If CMN10 and CMN12 Take it as consistent,

[0103] (ηV T ) CMN10 =(ηV T ) CMN12 (17)

[0104] From branch current I D As can be seen from the formula, the current is independent of the voltage.

[0105] Both sides simultaneously on I D Differentiate:

[0106]

[0107] in C is greater than 0.

[0108]

[0109] Solve the differential equation:

[0110] I D =I D0 T C(2-m) (20)

[0111] I D0 This is a temperature-independent coefficient. In the TSMC 65NMLP process, the temperature coefficient of charge carriers for electrons is greater than 2, while the temperature coefficient of charge carriers for holes is less than 2. Therefore, temperature compensation is required to obtain a reference current.

[0112] Figure 4 This is a schematic diagram of a first pre-adjustment circuit 120 according to an embodiment of the present disclosure.

[0113] like Figure 4 As shown, the first pre-adjustment circuit 120 includes N-type field-effect transistors CMP4, CMP5, CMP6, and CMP7, P-type field-effect transistors CMN4, CMN5, CMN6, and CMN7, a first resistor R1, and a second capacitor C2.

[0114] According to an embodiment of this disclosure, the gate of CMP4 is configured to receive the first start signal V. stal The source of the CMP4 is configured to receive the power supply voltage V. dd The drain of CMP4 is configured to connect to the source of CMP6; the gate of CMP5 is configured to receive the first start signal V. stal The source of the CMP5 is configured to receive the supply voltage V. dd The drain of CMP5 is configured to be connected to the gate of CMP5; the gate of CMP6 is configured to be connected to the drain of CMN12, the source of CMP6 is configured to be connected to the source of CMP7, and the drain of CMP6 is configured to be connected to the drain of CMN6; the gate of CMP7 is configured to be connected to the gate of CMP8, the source of CMP7 is configured to provide a first pre-adjustment voltage V1, and the drain of CMP7 is configured to be connected to the drain of CMN7; the gate of CMN4 is configured to be connected to the drain of CMP6, and the source of CMN4 is configured to be connected to the drain of CMP6. The source of CMN4 is configured to be grounded, and the drain of CMN4 is configured to be connected to the drain of CMP4, and connected to the gate of CMN4 in sequence through the first resistor R1 and the second capacitor C2; the gate of CMN5 is configured to be connected to the gate of CMN6, the source of CMN5 is configured to be grounded, and the drain of CMN5 is configured to be connected to the drain of CMP5; the gate of CMN6 is configured to be connected to the gate of CMN7, and the source of CMN6 is configured to be grounded; the gate of CMN7 is configured to be connected to the drain of CMN7, and provides a first reference signal V. ref1 The source of CMN7 is configured to be grounded.

[0115] According to embodiments of this disclosure, the core of the first pre-adjustment circuit 120 consists of a common-gate amplifier composed of CMP6 and CMN6, and a common-source amplifier composed of CMP4 and CMN4. This loop is a negative feedback loop with two high-impedance nodes, therefore a Miller compensation capacitor, i.e., the second capacitor C2, is needed to stabilize the loop. Simultaneously, the first resistor R1 can cancel out the secondary poles and zeros, improving the phase margin of the feedback loop. By using this first pre-adjustment circuit 120, the power supply voltage V can be isolated. dd To mitigate noise interference, the first pre-adjustment voltage V1 generated by the first pre-adjustment circuit 120 is used to power the first current generating circuit 130, thus isolating the power supply voltage V. dd The noise in the circuit affects the first current generation circuit 130, thereby improving the power supply rejection ratio and line regulation of the reference current source.

[0116] Figure 5 This is a schematic diagram of a second startup circuit 210 according to an embodiment of the present disclosure.

[0117] like Figure 5 As shown, the second startup circuit 210 includes N-type field-effect transistors PMP1, PMP2, PMP3 and P-type field-effect transistors PMN1, PMN2, PMN3.

[0118] According to an embodiment of this disclosure, the gate of PMP1 is configured to receive a second reference signal V. ref2 The source of PMP1 is configured to be connected to the drain of PMP2, and the drain of PMP1 is configured to be connected to the gates of PMN2 and PMN3 respectively; the gate of PMP2 is configured to be connected to the drain of PMP2, and the source of PMP2 is configured to be connected to the drain of PMP3; the gate of PMP3 is configured to be connected to the drain of PMP3, and the source of PMP3 is configured to receive the power supply voltage V. dd The gate of PMN1 is configured to receive the second reference signal V. ref2 The source of PMN1 is configured to be grounded, and the drain of PMN1 is configured to be connected to the gates of PMN2 and PMN3, respectively; the source of PMN2 is configured to be grounded, and the drain of PMN2 is configured to provide a third start signal V. sta3 The source of PMN3 is configured to be grounded, and the drain of PMN3 is configured to provide the fourth start signal V. sta4 .

[0119] According to embodiments of this disclosure, PMN1 and PMP1 are configured to form an inverter, in response to the second reference signal V. ref2When in a low-level state, the inverter is configured to provide a high-level signal to the gates of PMN2 and PMN3 to control PMN2 and PMN3 to be in a conducting state, thereby enabling the third start-up signal V at the drain of PMN2. sta3 and the fourth start-up signal V at the drain of PMN3 sta4 Both are in a low-level state. This low-level start signal can control the second pre-adjustment circuit 220 and the second current generation circuit 230 to start. After the second pre-adjustment circuit 220 starts, it can control the second reference signal V. ref2 It is in a high-level state. (In the second reference signal V) ref2 When in a high-level state, the inverter is configured to provide a low-level signal to the gates of PMN2 and PMN3 to control PMN2 and PMN3 to be in a cut-off state. At this time, the field-effect transistors in the second startup circuit 210 are all in a cut-off state, and their power consumption is zero, thereby reducing the power consumption of the reference current source.

[0120] Figure 6 This is a schematic diagram of a second current generating circuit 230 according to an embodiment of the present disclosure.

[0121] like Figure 6 As shown, the second current generating circuit 230 includes a second feedback adjustment unit, a second current source unit, and a second bias voltage generating unit.

[0122] According to embodiments of this disclosure, the second current source unit includes N-type field-effect transistors PMP9, PMP10, and PMP11, P-type field-effect transistors PMN9 and PMN10, and a third capacitor C3. The second current source unit is configured to generate a second current I2. The second feedback adjustment unit includes N-type field-effect transistors PMP8 and P-type field-effect transistors PMN8. The second feedback adjustment unit is configured to control the drain voltage of PMP9 to be equal to the drain voltage of PMP10. The second bias voltage generation unit includes N-type field-effect transistors PMP12, PMP13, and PMP14, and P-type field-effect transistors PMN11 and PMN12. The second bias voltage generation unit is configured to generate a second bias signal V. bias2 .

[0123] According to embodiments of this disclosure, the gates of PMN8, PMN9, PMN10, PMN11, and PMN12 are configured to be interconnected. The sources of PMN8, PMN9, PMN10, PMN11, and PMN12 are all configured to be grounded. The drain of PMN8 is configured to be connected to the gate of PMN8. The drain of PMN9 is configured to be grounded through a third capacitor C3. The drain of PMN10 is configured to be connected to the drain of PMP10. The drain of PMN11 is configured to be connected to the drain of PMP13. The drain of PMN12 is configured to be connected to the drain of PMP14. The gate of PMP8 is configured to be connected to the drain of PMP9. The source of PMN8 is configured to receive a second pre-adjustment voltage V2. The drain of PMP8 is configured to be connected to the drain of PMN8. The gate of PMP9 is configured to receive a fourth start signal V. sta4 The source of PMP9 is configured to receive a second pre-adjusted voltage V2, and the drain of PMP9 is configured to be connected to the drain of PMN9; the gate of PMP10 is configured to be connected to the gate of PMP9, the source of PMP10 is configured to be connected to the drain of PMN11, and the drain of PMP10 is configured to be connected to the gate of PMP10; the gate of PMP11 is configured to be connected to the gate of PMP13 to receive a second bias signal V. bias2 The source of PMP11 is configured to receive the second pre-adjustment voltage V2; the gate of PMP12 is configured to be connected to the gate of PMP14; the source of PMP12 is configured to be connected to receive the second pre-adjustment voltage V2; the drain of PMP12 is configured to be connected to the source of PMP13 and the source of PMP14 respectively; the gate of PMP13 is configured to be connected to the drain of PMP13; and the gate of PMP14 is configured to be connected to the drain of PMP14.

[0124] Figure 7 This is a schematic diagram of a second pre-adjustment circuit 220 according to an embodiment of the present disclosure.

[0125] like Figure 7 As shown, the second pre-adjustment circuit 220 includes N-type field-effect transistors PMP4, PMP5, PMP6, and PMP7, P-type field-effect transistors PMN4, PMN5, PMN6, and PMN7, a second resistor R2, and a fourth capacitor C4.

[0126] According to an embodiment of this disclosure, the gate of the PMP4 is configured to receive a second start signal V. sta2 The source of the PMP4 is configured to receive the power supply voltage V. dd The drain of PMP4 is configured to connect to the source of PMP6; the gate of PMP5 is configured to receive the second start signal V. sta2 The source of the PMP5 is configured to receive the power supply voltage V.dd The drain of PMP5 is configured to be connected to the gate of PMP5; the gate of PMP6 is configured to be connected to the gate of PMN9, the source of PMP6 is configured to be connected to the source of PMP7, and the drain of PMP6 is configured to be connected to the drain of PMN6; the gate of PMP7 is configured to be connected to the gate of PMP9, the source of PMP7 is configured to provide a second pre-regulation voltage V2, and the drain of PMP7 is configured to be connected to the drain of PMN7; the gate of PMN4 is configured to be connected to the drain of PMP6, and the source of PMN4 is configured to be connected to the drain of PMN7. The gate of PMN4 is configured to be grounded, and the drain of PMN4 is configured to be the drain of PMP4, and connected to the gate of PMN4 in sequence through the second resistor R2 and the fourth capacitor C4; the gate of PMN5 is configured to be connected to the gate of PMN6, the source of PMN5 is configured to be grounded, and the drain of PMN5 is configured to be connected to the drain of PMP5; the gate of PMN6 is configured to be connected to the gate of PMN7, and the source of PMN6 is configured to be grounded; the gate of PMN7 is configured to be connected to the drain of PMN7, and provides the second reference signal V. ref2 The source of PMN7 is configured to be grounded.

[0127] Figure 8 This is a schematic diagram of a temperature compensation circuit according to an embodiment of the present disclosure.

[0128] like Figure 8 As shown, the temperature compensation module 300 includes P-type field-effect transistors MA1, MA2, MA3, MA4, and MA5.

[0129] According to an embodiment of this disclosure, the gate of MA1 is configured to connect to the second current generating module 200 and replicate the current of the second current generating module 200 to obtain a second current I2. The source of MA1 is configured to be grounded, and the drain of MA1 is configured to connect to the drain of MA4 to transfer the current of MA1 to MA4. The gate of MA2 is configured to connect to the first current generating module 100 and replicate the current of the first current generating module 100 to obtain a first current I1. The source of MA2 is configured to receive the power supply voltage V. dd The gate of MA3 is configured to be connected to the gate of MA4 to replicate the current of MA4. The source of MA3 is configured to be connected to the source of MA2, and the drain of MA3 is configured to be connected to the drain of MA2 to replicate the current of MA2. The currents are then summed as shown in formula (21). The drain of MA3 is configured to be connected to the drain of MA5 to output the reference current I. ref The gate of MA4 is configured to be connected to the drain of MA4, and the source of MA4 is configured to be connected to the source of MA3; the gate of MA5 is configured to be connected to the drain of MA5, and the source of MA5 is configured to be grounded.

[0130]

[0131] Where m p >2,m n <2 Choosing an appropriate amplification factor can make:

[0132]

[0133] Figure 9 This is a schematic diagram of the linear regulation rate of a reference current source according to an embodiment of the present disclosure.

[0134] like Figure 9 As shown, the linear regulation rate of the reference current source is improved by using the first pre-regulation circuit 120.

[0135] Figure 10 This is a schematic diagram of the power supply rejection ratio of a reference current source according to an embodiment of the present disclosure.

[0136] like Figure 10 As shown, the power supply rejection ratio of the reference current source is improved by using the first pre-adjustment circuit 120.

[0137] Figure 11 This is a schematic diagram of the current variation curve with temperature after temperature compensation according to an embodiment of the present disclosure.

[0138] like Figure 11 As shown, this disclosure sums the second current I2 and the first current I1 to obtain the reference current I. REF After temperature compensation is implemented, the reference current source circuit of this disclosure has an excellent temperature coefficient.

[0139] Figure 12 This is a performance comparison diagram of the embodiment of this disclosure and a conventional reference current source circuit at deep submicron depths.

[0140] like Figure 12 As shown, at the deep submicron scale, such as with the TSMC 65NMLP process disclosed herein, the current generated by the reference current source does not fluctuate significantly with changes in the power supply voltage, while the current generated by a traditional reference current source fluctuates significantly with changes in the power supply voltage. The power supply rejection ratio of the reference current source disclosed herein is also improved compared to traditional reference current sources. At the deep submicron scale, the circuit performance of this reference current source is superior to that of traditional reference current source circuits.

[0141] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and claims of this disclosure can be combined and combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and combinations fall within the scope of this disclosure.

[0142] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A reference current source, comprising: The first current generating module includes a first start-up circuit, a first pre-adjustment circuit, and a first current generating circuit. The first start-up circuit is configured to provide a first start-up signal to the first pre-adjustment circuit and a second start-up signal to the first current generating circuit. The first pre-adjustment circuit is configured to provide a first reference signal to the first start-up circuit and a first pre-adjustment voltage to the first current generating circuit. The first current generating circuit is configured to generate a first current that is complementary to the absolute temperature. The second current generating module includes a second startup circuit, a second pre-regulation circuit, and a second current generating circuit. The second startup circuit is configured to provide a third startup signal to the second pre-regulation circuit and a fourth startup signal to the second current generating circuit. The second pre-regulation circuit is configured to provide a second reference signal to the second startup circuit and a second pre-regulation voltage to the second current generating circuit. The second current generating circuit is configured to generate a second current proportional to the absolute temperature. A temperature compensation module is configured to be connected to the first current generation module and the second current generation module respectively. The temperature compensation module is configured to superimpose the first current and the second current to obtain a reference current that is independent of the absolute temperature. The first current generating circuit includes a first feedback adjustment unit, a first current source unit, and a first bias voltage generating unit. The first current source unit includes P-type field-effect transistors CMP9 and CMP10, N-type field-effect transistors CMN9, CMN10, and CMN11, and a first capacitor. The first current source unit is configured to generate the first current. The first feedback adjustment unit includes a P-type field-effect transistor CMP8 and an N-type field-effect transistor CMN8. The first feedback adjustment unit is configured to control the drain voltage of CMN9 to be equal to the drain voltage of CMN10. The first bias voltage generating unit includes P-type field-effect transistors CMP11 and CMP12 and N-type field-effect transistors CMN12, CMN13 and CMN14, and the first bias voltage generating unit is configured to generate a first bias signal. The first pre-adjustment circuit includes P-type field-effect transistors CMP4, CMP5, CMP6, and CMP7, N-type field-effect transistors CMN4, CMN5, CMN6, and CMN7, a first resistor, and a second capacitor. Wherein, the gate of CMP4 is configured to receive the first start signal, the source of CMP4 is configured to receive the power supply voltage, and the drain of CMP4 is configured to be connected to the source of CMP6; The gate of the CMP5 is configured to receive the first startup signal, the source of the CMP5 is configured to receive the power supply voltage, and the drain of the CMP5 is configured to be connected to the gate of the CMP5. The gate of CMP6 is configured to be connected to the drain of CMN12, the source of CMP6 is configured to be connected to the source of CMP7, and the drain of CMP6 is configured to be connected to the drain of CMN6. The gate of CMP7 is configured to be connected to the gate of CMP8, the source of CMP7 is configured to provide the first pre-adjusted voltage, and the drain of CMP7 is configured to be connected to the drain of CMN7. The gate of CMN4 is configured to be connected to the drain of CMP6, the source of CMN4 is configured to be grounded, the drain of CMN4 is configured to be connected to the drain of CMP4, and the gate of CMN4 is connected to the drain of CMP6 in sequence through the first resistor and the second capacitor. The gate of CMN5 is configured to be connected to the gate of CMN6, the source of CMN5 is configured to be grounded, and the drain of CMN5 is configured to be connected to the drain of CMP5. The gate of CMN6 is configured to be connected to the gate of CMN7, and the source of CMN6 is configured to be grounded; The gate of the CMN7 is configured to be connected to the drain of the CMN7 and to provide the first reference signal, and the source of the CMN7 is configured to be grounded.

2. The reference current source of claim 1, wherein, The first startup circuit includes P-type field-effect transistors CMP1, CMP2, and CMP3, and N-type field-effect transistors CMN1, CMN2, and CMN3; Wherein, the gate of CMP1 is configured to receive the first reference signal, the source of CMP1 is configured to be connected to the drain of CMP2, and the drain of CMP1 is configured to be connected to the gate of CMN2 and the gate of CMN3 respectively. The gate of CMP2 is configured to be connected to the drain of CMP2, and the source of CMP2 is configured to be connected to the drain of CMP3; The gate of the CMP3 is configured to be connected to the drain of the CMP3, and the source of the CMP3 is configured to receive a power supply voltage. The gate of CMN1 is configured to receive the first reference signal, the source of CMN1 is configured to be grounded, and the drain of CMN1 is configured to be connected to the gate of CMN2 and the gate of CMN3 respectively. The source of CMN2 is configured to be grounded, and the drain of CMN2 is configured to provide the first start signal; The source of CMN3 is configured to be grounded, and the drain of CMN3 is configured to provide the second start signal; Wherein, CMN1 and CMP1 are configured to form an inverter, and when the first reference signal is in a low-level state, the inverter is configured to provide a high-level signal to the gate of CMN2 and the gate of CMN3 to control CMN2 and CMN3 to be in a conducting state; and When the first reference signal is in a high-level state, the inverter is configured to provide a low-level signal to the gate of CMN2 and the gate of CMN3 to control CMN2 and CMN3 to be in a cut-off state.

3. The reference current source of claim 1, wherein, The gates of CMP8, CMP9, CMP10, CMP11, and CMP12 are all configured to receive the second startup signal. The sources of CMP8, CMP9, CMP10, CMP11, and CMP12 are all configured to receive the first pre-adjustment voltage. The drain of CMP8 is configured to be connected to the drain of CMN8. The drain of CMP9 is configured to be grounded through the first capacitor. The drain of CMP10 is configured to be connected to the drain of CMN10. The drain of CMP11 is configured to be connected to the drain of CMN12. The drain of CMP12 is configured to be connected to the drain of CMN13. The gate of CMN8 is configured to be connected to the drain of CMP9, and the source of CMN8 is configured to be connected to the drain of CMN11. The gate of CMN9 is configured to be connected to the gate of CMN10, the source of CMN9 is configured to be grounded, and the drain of CMN9 is configured to be connected to the drain of CMP9. The source of CMN10 is configured to be connected to the drain of CMN11; The gate of CMN11 is configured to be connected to the gate of CMN12, and the source of CMN11 is configured to be grounded; The gate of CMN12 is configured to be connected to the drain of CMN12, the gate of CMN12 is configured to generate the first bias signal, and the source of CMN12 is configured to be connected to the drain of CMN14. The gate of CMN13 is configured to be connected to the gate of CMN14, and the source of CMN13 is configured to be connected to the drain of CMN14. The source of the CMN14 is configured to be grounded.

4. The reference current source of claim 1, wherein, The second startup circuit includes P-type field-effect transistors PMP1, PMP2, and PMP3, and N-type field-effect transistors PMN1, PMN2, and PMN3; Wherein, the gate of PMP1 is configured to receive the second reference signal, the source of PMP1 is configured to be connected to the drain of PMP2, and the drain of PMP1 is configured to be connected to the gate of PMN2 and the gate of PMN3 respectively. The gate of PMP2 is configured to be connected to the drain of PMP2, and the source of PMP2 is configured to be connected to the drain of PMP3. The gate of the PMP3 is configured to be connected to the drain of the PMP3, and the source of the PMP3 is configured to receive the power supply voltage. The gate of PMN1 is configured to receive the second reference signal, the source of PMN1 is configured to be grounded, and the drain of PMN1 is configured to be connected to the gate of PMN2 and the gate of PMN3 respectively. The source of the PMN2 is configured to be grounded, and the drain of the PMN2 is configured to provide the third start signal; The source of the PMN3 is configured to be grounded, and the drain of the PMN3 is configured to provide the fourth start signal; Wherein, PMN1 and PMP1 are configured to form an inverter, and when the second reference signal is in a low-level state, the inverter is configured to provide a high-level signal to the gate of PMN2 and the gate of PMN3 to control PMN2 and PMN3 to be in a conducting state; and When the second reference signal is in a high-level state, the inverter is configured to provide a low-level signal to the gate of PMN2 and the gate of PMN3 to control PMN2 and PMN3 to be in a cut-off state.

5. The reference current source according to claim 1, wherein, The second current generating circuit includes a second feedback adjustment unit, a second current source unit, and a second bias voltage generating unit. The second current source unit includes P-type field-effect transistors PMP9, PMP10, and PMP11, N-type field-effect transistors PMN9 and PMN10, and a third capacitor. The second current source unit is configured to generate the second current. The second feedback adjustment unit includes a P-type field-effect transistor PMP8 and an N-type field-effect transistor PMN8. The second feedback adjustment unit is configured to control the drain voltage of the PMP9 to be equal to the drain voltage of the PMP10. The second bias voltage generating unit includes P-type field-effect transistors PMP12, PMP13, and PMP14 and N-type field-effect transistors PMN11 and PMN12, and the second bias voltage generating unit is configured to generate a second bias signal.

6. The reference current source according to claim 5, wherein, The gates of PMN8, PMN9, PMN10, PMN11, and PMN12 are configured to be interconnected. The sources of PMN8, PMN9, PMN10, PMN11, and PMN12 are all configured to be grounded. The drain of PMN8 is configured to be connected to the gate of PMN8. The drain of PMN9 is configured to be grounded through the third capacitor. The drain of PMN10 is configured to be connected to the drain of PMP10. The drain of PMN11 is configured to be connected to the drain of PMP13. The drain of PMN12 is configured to be connected to the drain of PMP14. The gate of the PMP8 is configured to be connected to the drain of the PMP9, the source of the PMN8 is configured to receive the second pre-adjustment voltage, and the drain of the PMP8 is configured to be connected to the drain of the PMN8. The gate of the PMP9 is configured to receive the fourth start signal, the source of the PMP9 is configured to receive the second pre-adjustment voltage, and the drain of the PMP9 is configured to be connected to the drain of the PMN9. The gate of PMP10 is configured to be connected to the gate of PMP9, the source of PMP10 is configured to be connected to the drain of PMN11, and the drain of PMP10 is configured to be connected to the gate of PMP10. The gate of PMP11 is configured to connect to the gate of PMP13 to receive the second bias signal, and the source of PMP11 is configured to receive the second pre-adjustment voltage. The gate of PMP12 is configured to be connected to the gate of PMP14, the source of PMP12 is configured to be connected to receive the second pre-adjustment voltage, and the drain of PMP12 is configured to be connected to the source of PMP13 and the source of PMP14 respectively. The gate of the PMP13 is configured to be connected to the drain of the PMP13; The gate of the PMP14 is configured to be connected to the drain of the PMP14.

7. The reference current source according to claim 5, wherein, The second pre-adjustment circuit includes P-type field-effect transistors PMP4, PMP5, PMP6, and PMP7, N-type field-effect transistors PMN4, PMN5, PMN6, and PMN7, a second resistor, and a fourth capacitor. Wherein, the gate of the PMP4 is configured to receive the second start signal, the source of the PMP4 is configured to receive the power supply voltage, and the drain of the PMP4 is configured to be connected to the source of the PMP6. The gate of the PMP5 is configured to receive the second startup signal, the source of the PMP5 is configured to receive the power supply voltage, and the drain of the PMP5 is configured to be connected to the gate of the PMP5. The gate of PMP6 is configured to be connected to the gate of PMN9, the source of PMP6 is configured to be connected to the source of PMP7, and the drain of PMP6 is configured to be connected to the drain of PMN6. The gate of the PMP7 is configured to be connected to the gate of the PMP9, the source of the PMP7 is configured to provide the second pre-adjustment voltage, and the drain of the PMP7 is configured to be connected to the drain of the PMN7. The gate of PMN4 is configured to be connected to the drain of PMP6, the source of PMN4 is configured to be grounded, the drain of PMN4 is configured to be the drain of PMP4, and the gate of PMN4 is connected to the drain of PMP6 in sequence through the second resistor and the fourth capacitor. The gate of PMN5 is configured to be connected to the gate of PMN6, the source of PMN5 is configured to be grounded, and the drain of PMN5 is configured to be connected to the drain of PMP5. The gate of PMN6 is configured to be connected to the gate of PMN7, and the source of PMN6 is configured to be grounded; The gate of the PMN7 is configured to be connected to the drain of the PMN7 and to provide the second reference signal, and the source of the PMN7 is configured to be grounded.

8. The reference current source according to claim 1, wherein, The temperature compensation module includes P-type field-effect transistors MA1, MA2, MA3, MA4, and MA5; Wherein, the gate of MA1 is configured to be connected to the second current generating module to obtain the second current, the source of MA1 is configured to be grounded, and the drain of MA1 is configured to be connected to the drain of MA4; The gate of MA2 is configured to be connected to the first current generating module to obtain the first current, the source of MA2 is configured to receive the power supply voltage, and the drain of MA2 is configured to be connected to the drain of MA3. The gate of MA3 is configured to be connected to the gate of MA4, the source of MA3 is configured to be connected to the source of MA2, and the drain of MA3 is configured to be connected to the drain of MA5, so as to output the reference current; The gate of MA4 is configured to be connected to the drain of MA4, and the source of MA4 is configured to be connected to the source of MA3; The gate of the MA5 is configured to be connected to the drain of the MA5, and the source of the MA5 is configured to be grounded.

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