Data processor storage resource management method and device and electronic equipment

Abstract

The application provides a storage resource management method and device of a data processor and electronic equipment. The method comprises the following steps: determining a target bus link in which the data processor is located from a plurality of peripheral component interconnect standard bus links by enumerating a device supporting the peripheral component interconnect standard; configuring the target bus link to adopt a target link function configuration; the supported storage resource read-write bandwidth of the target link function configuration is higher than that of a default link function configuration; and managing the storage resource of the data processor based on the target bus link. By configuring the target bus link to adopt the target link function configuration, the target bus link after the configuration can support high-speed read-write of the storage resource of the DPU, and efficient use of the storage resource of the DPU under the operating system can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular to a storage resource management method and device of a data processor and electronic equipment. BACKGROUND

[0002] With the rapid development of data centers, communication capability and computing capability become two important development directions of data center infrastructure. The data processing unit (DPU) card not only retains the function of the network card, but also adds storage function and security function. Its most direct role is to serve as an offload engine of the central processing unit (CPU), take over the infrastructure layer services such as network virtualization and hardware resource pooling, and release the computing power of the CPU to the upper layer application. The DPU can become the entrance of the storage, localizing the distributed storage and remote access. However, how to efficiently use the storage resources of the DPU under the operating system is a problem to be solved in the industry at present. SUMMARY

[0003] In view of the problems in the prior art, the embodiments of the present application provide a storage resource management method and device of a data processor and electronic equipment.

[0004] In a first aspect, the present application provides a storage resource management method of a data processor, comprising:

[0005] By enumerating the devices supporting the peripheral component interconnect standard, a target bus link where the data processor is located is determined in a plurality of bus links supporting the peripheral component interconnect standard, and the initial bus link adopts a default link function configuration;

[0006] The target bus link is configured to adopt a target link function configuration, and the supported storage resource read-write bandwidth of the target link function configuration is higher than that of the default link function configuration;

[0007] Based on the target bus link, the storage resources of the data processor are managed.

[0008] Optionally, according to the storage resource management method of the data processor provided by the present application, the configuration of the target bus link to adopt the target link function configuration comprises:

[0009] By the basic input / output system, the environment variable corresponding to the target bus link in the target table is updated to a target value, and the target table is used to describe different hardware information of the system;

[0010] Based on the target table, the target bus link is configured to adopt the target link function configuration;

[0011] wherein the environment variable corresponding to each bus link in the initial target table is a default value, and the target value is different from the default value.

[0012] Optionally, the application provides a storage resource management method of a data processor, the environment variable is a variable in an ACPI (Advanced Configuration and Power Interface) protocol, and the configuration of the target bus link adopting the target link function configuration based on the target table comprises:

[0013] filtering out, based on the environment variable delivered by the target table, bus links with the environment variable being the target value from a plurality of bus links through an ACPI protocol.

[0014] configuring the bus links with the environment variable being the target value to adopt the target link function configuration.

[0015] Optionally, the application provides a storage resource management method of a data processor, and the target bus link in which the data processor is located is determined from a plurality of bus links supporting a PCI (Peripheral Component Interconnect) standard by enumerating devices supporting the PCI standard.

[0016] The target bus link in which the data processor is located is determined from a plurality of bus links by enumerating bus devices based on the vendor identification code and the version identification code of each bus device.

[0017] Optionally, the application provides a storage resource management method of a data processor, and the storage resource of the data processor is managed based on the target bus link.

[0018] determining one or more software objects to be installed;

[0019] dividing, for each software object to be installed, a first storage unit from the storage resource of the data processor based on the target bus link, the first storage unit being used to load the software object to be installed.

[0020] Optionally, the application provides a storage resource management method of a data processor, and the storage resource of the data processor is managed based on the target bus link.

[0021] determining one or more software objects to be unloaded;

[0022] recycling, for each software object to be unloaded, a second storage unit to the storage resource of the data processor based on the target bus link, the second storage unit being used to load the software object to be unloaded.

[0023] Optionally, the application provides a storage resource management method of a data processor, and the software object is an operating system, a driver or a business application.

[0024] In a second aspect, the application provides a storage resource management apparatus of a data processor, comprising:

[0025] A determination module is configured to determine a target bus link in which the data processor is located among a plurality of bus links supporting a peripheral component interconnect express (PCIe) standard by enumerating a PCIe device, and the initial bus link adopts a default link function configuration;

[0026] A configuration module is configured to configure the target bus link to adopt a target link function configuration, and the target link function configuration supports a higher storage resource read-write bandwidth than the default link function configuration.

[0027] A management module is configured to manage the storage resource of the data processor based on the target bus link.

[0028] In a third aspect, the application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the storage resource management method of the data processor according to any one of the above aspects when executing the program.

[0029] In a fourth aspect, the application provides a non-transitory computer readable storage medium, which stores a computer program executable by a processor to implement the storage resource management method of the data processor according to any one of the above aspects.

[0030] The storage resource management method, apparatus and electronic device of the data processor provided by the application can determine a target bus link in which the DPU is located among a plurality of PCIe links by enumerating a PCIe device, and then configure the target bus link to adopt a target link function configuration, and the target link function configuration supports a higher storage resource read-write bandwidth than the default link function configuration, that is, the target bus link after the configuration can support high-speed read-write of the storage resource of the DPU, fully adapt to the read-write bandwidth of the SSD, and then after entering the operating system, the storage resource of the DPU can be managed quickly based on the target bus link, and the storage resource of the DPU can be used efficiently under the operating system. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the present application or the prior art, the following will briefly introduce the drawings required to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0032] Figure 1 is one of the flowcharts of the storage resource management method of the data processor provided by the present application;

[0033] Figure 2 is another flowchart of the storage resource management method of the data processor provided by the present application;

[0034] Figure 3 is a third flowchart of the storage resource management method of the data processor provided by the present application;

[0035] Figure 4 is a structural schematic diagram of the storage resource management device of the data processor provided by the present application;

[0036] Figure 5 is a structural schematic diagram of the electronic device provided by the present application. DETAILED DESCRIPTION

[0037] In order to facilitate more clearly understanding the embodiments of the present application, first, some related background knowledge is introduced as follows.

[0038] The DPU card not only retains the function of the network card, but also adds the storage function and the security function, and the DPU can also become the entrance of the storage, localizes the distributed storage and remote access. With the improvement of the performance-price ratio of the SSD, it has become possible to migrate part of the storage to the SSD device. The traditional serial hard disk (Serial ATA, SATA) protocol is not suitable for the SSD storage, so it becomes an optional technical route to access the SSD through the local PCIe or high-speed network system. The Non Volatile Memory Express (NVMe) is a high-speed interface standard protocol for accessing the SSD storage, which can fully exert the bandwidth advantage of the SSD by taking the PCIe as the underlying transmission protocol.

[0039] Meanwhile, in the distributed system, the NVMe over Fabrics (NVMe-oF) protocol can be extended to an InfiniBand, an Ethernet, or a Fibre channel node to realize sharing and remote access of storage in the form of Remote Direct Memory Access (RDMA). These new protocol processes can be integrated in the DPU to realize transparent processing of the CPU. Further, the DPU can take the role of various interconnection protocol controllers to achieve a better balance point in flexibility and performance.

[0040] However, the DPU card can be inserted into any PCIe link on the processor, and the PCIe link can also be used to support other PCIe devices, and some scheme optimization needs to be performed to realize efficient use of the function of the DPU card on the processor.

[0041] In order to overcome the above defects, the present application provides a data processor storage resource management method, device and electronic equipment, which can support high-speed reading and writing of the storage resource of the DPU through the configured target bus link, and can realize efficient use of the storage resource of the DPU under the operating system.

[0042] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the present application will be described clearly and completely below in combination with the drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] Figure 1 The present application provides one of the flowcharts of the data processor storage resource management method, and the execution subject of the data processor storage resource management method can be an electronic equipment, such as a server and the like. The method comprises:

[0044] Step 101, by enumerating the devices supporting the peripheral component interconnection standard, determining the target bus link where the data processor is located in the plurality of bus links supporting the peripheral component interconnection standard, and the initial bus link adopts the default link function configuration.

[0045] Specifically, in order to realize efficient use of the storage resource of the DPU card under the operating system, the PCIe device can be enumerated to determine the target bus link where the DPU is located in the plurality of PCIe links, and the initial PCIe link adopts the default link function configuration, and the link function configuration can be updated for the target bus link.

[0046] In step 102, the target bus link is configured to use a target link function configuration, and the target link function configuration supports a higher read-write bandwidth of storage resources than the default link function configuration.

[0047] Specifically, after determining the target bus link where the DPU is located, the target bus link can be configured to use a target link function configuration, and the target link function configuration supports a higher read-write bandwidth of storage resources than the default link function configuration, and the target bus link can fully adapt to the read-write bandwidth of the SSD.

[0048] Optionally, the target link function configuration can be a link function configuration related to NVMe, and after the target bus link is configured to use the target link function configuration, the target bus link can support NVMe, and can fully exert the bandwidth advantage of the SSD by using PCIe as an underlying transmission protocol, so as to fully adapt to the read-write bandwidth of the SSD.

[0049] In step 103, the storage resources of the data processor are managed based on the target bus link.

[0050] Specifically, after entering the operating system, the storage resources of the DPU can be quickly managed based on the target bus link (the target bus link after configuration can support high-speed read-write of the storage resources of the DPU), and the storage resources of the DPU can be efficiently used under the operating system.

[0051] It can be understood that the DPU card not only includes a network card function, but also includes a chip with a storage function. When the DPU is used in a system, the storage chip of the DPU is a whole large storage device similar to a hard disk. If all applications are placed on this storage chip, it will cause waste of resources. After entering the operating system, the storage resources of the DPU can be divided into multiple storage units (i.e., multiple divided hard disks) based on the target bus link, so that each different application program can be run on a different divided hard disk. When a certain application has been used and the divided hard disk used by the application needs to be released, the divided hard disk is erased and returned to the storage resources of the DPU. When a new service occurs, a new hard disk can be divided from the storage resources of the DPU for application, and the storage resources of the DPU can be repeatedly used without limitation.

[0052] The application provides a storage resource management method of a data processor, wherein by enumerating a PCIe device, a target bus link in which a DPU is located can be determined in multiple PCIe links, and then the target bus link can be configured to adopt a target link function configuration, and a storage resource read-write bandwidth supported by the target link function configuration is higher than a storage resource read-write bandwidth supported by a default link function configuration, that is, the target bus link after the configuration can support high-speed read-write of the storage resource of the DPU, fully adapts to the read-write bandwidth of an SSD, and then after entering an operating system, the storage resource of the DPU can be quickly managed based on the target bus link, and the storage resource of the DPU can be efficiently used under the operating system.

[0053] Optionally, in the storage resource management method of the data processor provided by the application, the configuration of the target bus link to adopt the target link function configuration comprises:

[0054] The environment variable corresponding to the target bus link in the target table is updated to a target value by a basic input output system, and the target table is used for describing different hardware information of a system.

[0055] The target bus link is configured to adopt the target link function configuration based on the target table.

[0056] In the initial target table, the environment variable corresponding to each bus link is a default value, and the target value is different from the default value.

[0057] Specifically, after the target bus link in which the DPU is located is determined, the environment variable corresponding to the target bus link in a target table (The Differentiated System Description Table, DSDT) used for describing different hardware information of a system can be updated to a target value by a basic input output system (Basic Input Output System, BIOS), the environment variable corresponding to each bus link in an initial DSDT is a default value, the target value is different from the default value, the PCIe link (that is, the target bus link) in which the DPU is located can be found in the DSDT through the target value, and then the target bus link can be configured to adopt a target link function configuration based on the DSDT, the storage resource read-write bandwidth supported by the target link function configuration is higher than the storage resource read-write bandwidth supported by a default link function configuration, and the target bus link can fully adapt to the read-write bandwidth of an SSD.

[0058] Optionally, in the storage resource management method of the data processor provided by the application, the environment variable is a variable in an advanced configuration and power management interface protocol, and the configuration of the target bus link to adopt the target link function configuration based on the target table comprises:

[0059] filtering out, based on the environment variable delivered by the target table, a bus link with the environment variable being the target value, from a plurality of bus links via an Advanced Configuration and Power Interface protocol.

[0060] The bus link with the environment variable being the target value adopts the target link function configuration.

[0061] Specifically, after determining the target bus link where the DPU is located, the environment variable corresponding to the target bus link in the DSDT can be updated to the target value via the BIOS, and then based on the environment variable delivered by the target table, whether the environment variable corresponding to each bus link is consistent with a default value can be compared via an Advanced Configuration and Power Interface (ACPI) protocol, the environment variable corresponding to each bus link in the initial DSDT is the default value, and the target value is different from the default value, so that the bus link with the environment variable being the target value (i.e., the PCIe link where the DPU is located) can be filtered out from a plurality of bus links, and then the PCIe link where the DPU is located can be configured to adopt the target link function configuration via the ACPI protocol, so that the PCIe link where the DPU is located can fully adapt to the read-write bandwidth of the SSD.

[0062] Optionally, according to the data processor storage resource management method provided by the application, the target bus link where the data processor is located is determined from a plurality of bus links supporting a peripheral component interface interconnection standard by enumerating devices supporting the peripheral component interface interconnection standard, and the method comprises the following steps.

[0063] The target bus link where the data processor is located is determined from a plurality of bus links by enumerating bus devices based on the vendor identification code and the version identification code of each bus device.

[0064] Specifically, whether each PCIe device is a DPU can be determined in the enumeration process of the PCIe device based on the vendor identification code of each PCIe device and the version identification code of each PCIe device, so that the target bus link where the DPU is located can be determined from a plurality of bus links, the initial PCIe link adopts a default link function configuration, and then the link function configuration of the target bus link can be updated, so that the target bus link can fully adapt to the read-write bandwidth of the SSD.

[0065] Optionally, according to the data processor storage resource management method provided by the application, the storage resource of the data processor is managed based on the target bus link, and the method comprises the following steps.

[0066] Determine one or more software objects to be installed.

[0067] For each to-be-installed software object, a first storage unit is divided from the storage resource of the data processor based on the target bus link, and the first storage unit is used to load the to-be-installed software object.

[0068] Specifically, after entering the operating system, one or more to-be-installed software objects can be determined, for each to-be-installed software object, a first storage unit can be quickly divided from the storage resource of the DPU based on the target bus link (the target bus link after configuration can support high-speed reading and writing of the storage resource of the DPU), and the first storage unit can be used to load the to-be-installed software object.

[0069] Optionally, according to the data processor storage resource management method provided by the application, the management of the storage resource of the data processor based on the target bus link comprises:

[0070] determining one or more to-be-unloaded software objects;

[0071] For each to-be-unloaded software object, a second storage unit is recycled to the storage resource of the data processor based on the target bus link, and the second storage unit is used to load the to-be-unloaded software object.

[0072] Specifically, after entering the operating system, one or more to-be-unloaded software objects can be determined, for each to-be-unloaded software object, a second storage unit (a storage unit used to load the to-be-unloaded software object) can be quickly recycled to the storage resource of the data processor based on the target bus link (the target bus link after configuration can support high-speed reading and writing of the storage resource of the DPU).

[0073] It can be understood that dividing the storage resource of the DPU into a plurality of storage units can conveniently run each different software object on a different storage unit, when a software object has been used up and needs to release the storage unit used by the software object, that is, to erase and return to the storage resource of the DPU, when a new service occurs, a new storage unit can be divided from the storage resource of the DPU for application, and the storage resource of the DPU can be efficiently reused.

[0074] Optionally, according to the data processor storage resource management method provided by the application, the software object is an operating system, a driver or a service application.

[0075] Specifically, after entering the operating system, the operating system, the driver or the business application (application program corresponding to the business) to be installed can be determined, and based on the target bus link, the first storage unit can be quickly divided from the storage resource of the DPU, and the first storage unit can be used to load the operating system, the driver or the business application to be installed.

[0076] Specifically, after entering the operating system, the driver or the business application to be unloaded can be determined, and based on the target bus link, the second storage unit (storage unit for loading the driver or the business application to be unloaded) can be quickly recycled to the storage resource of the data processor.

[0077] It can be understood that the data processor storage resource management method provided by the application has strong replicability and expandability. The basic input and output system startup process is used to perform PCIe device judgment on all PCIe links and confirm that the specific PCIe link supports the DPU card. At the same time, the variable in the ACPI protocol of the PCIe link on the DPU card is modified to meet the efficient reuse of the DPU card storage chip resource under the system, to realize the dynamic support of a DPU card to multiple storage devices required by the system, reduce the demand for manual update of physical hard disks, reduce the server procurement cost, reduce the total cost of ownership (Total Cost of Ownership, TCO) of the data center, and the server using the DPU will be the key development direction of cloud computing. The application is not affected by the processor architecture and can be applied to advanced RISC machines (Advanced RISCMachines, ARM), X86 or processors with reduced instruction set (RISC) (Millions of Instructions Per Second, Mips) and other multi-architecture server products, which is beneficial to large-scale deployment of multi-card server applications.

[0078] The following are two optional examples of the application, but not as a limitation of the application.

[0079] Example one, Figure 2 is a flowchart of the data processor storage resource management method provided by the application, as shown in Figure 2 the method comprises steps 201 to 205.

[0080] Step 201, in the PCIe device enumeration stage of BIOS, based on the manufacturer ID and version ID of the PCIe device, the target bus link where the DPU is located is determined in the plurality of PCIe links.

[0081] In step 202, the ACPI protocol environment variable corresponding to the target bus link in the DSDT is updated to a target value.

[0082] It can be understood that the ACPI protocol environment variable corresponding to each PCIe link in the initial DSDT is a default value, and the target value is different from the default value.

[0083] In step 203, based on the environment variable delivered by the DSDT, the bus link with the environment variable being the target value is screened out from the plurality of bus links through the ACPI protocol.

[0084] In step 204, the bus link with the environment variable being the target value is configured to use the target link function configuration through the ACPI protocol.

[0085] It can be understood that the initial PCIe link uses a default link function configuration, the storage resource read-write bandwidth supported by the target link function configuration is higher than that supported by the default link function configuration, and the link function configuration is updated for the target bus link, so that the target bus link can fully adapt to the read-write bandwidth of the SSD.

[0086] In step 205, the storage resource of the DPU is managed based on the target bus link.

[0087] It can be understood that after entering the operating system, the storage resource of the DPU can be managed quickly based on the target bus link (the target bus link after configuration can support high-speed read-write of the storage resource of the DPU), and the storage resource of the DPU can be efficiently used under the operating system.

[0088] Therefore, whether the PCI device is a DPU card is judged through the BIOS startup PCI enumeration process, and when the PCI device is a DPU card, the variable in the ACPI protocol of the corresponding PCI link is updated, so that the division and repeated return of the storage chip of the DPU card under the operating system can be realized, that is, the storage chip of the DPU card can be arbitrarily divided and recycled under the system according to actual business needs.

[0089] Example two, Figure 3 is a flowchart of a third storage resource management method of a data processor provided by the application, as shown in Figure 3 The method comprises steps 301 to 303.

[0090] In step 301, after the target bus link is configured to use the target link function configuration, one or more storage units are divided from the storage resource of the DPU based on the target bus link, for loading the operating system, the initial driver or the initial business application.

[0091] It can be understood that after step 301 is performed, step 302 or step 303 can be performed as needed.

[0092] In step 302, for each to-be-installed new driver or new service application, one or more storage units are divided from the storage resource of the DPU based on the target bus link, for loading the new driver or the new service application.

[0093] In step 303, for each to-be-unloaded operating system, driver or service application, the corresponding storage unit is recycled to the storage resource of the DPU based on the target bus link.

[0094] Therefore, by dividing the storage resource of the DPU into multiple storage units, each different software object can be conveniently run on a different storage unit. When a driver or a service application has been used, the storage unit used by the driver or the service application can be released and returned to the storage resource of the DPU. When a new service appears, a new storage unit can be divided from the storage resource of the DPU for application, so that the storage resource of the DPU can be efficiently reused.

[0095] The data processor storage resource management method provided by the application can determine the target bus link where the DPU is located in the multiple PCIe links by enumerating the PCIe device, and then can configure the target bus link to use a target link function configuration. The storage resource read-write bandwidth supported by the target link function configuration is higher than the storage resource read-write bandwidth supported by the default link function configuration. That is, the target bus link after configuration can support high-speed reading and writing of the storage resource of the DPU, fully adapt to the read-write bandwidth of the SSD, and then enter the operating system. Based on the target bus link, the storage resource of the DPU can be managed quickly, and the storage resource of the DPU can be efficiently used under the operating system.

[0096] The data processor storage resource management device provided by the application is described below. The data processor storage resource management device described below can be referred to in correspondence with the data processor storage resource management method described above.

[0097] Figure 4 The data processor storage resource management device provided by the application is described below. The data processor storage resource management device described below can be referred to in correspondence with the data processor storage resource management method described above. Figure 4 As shown in FIG. 4, the device comprises a determination module 401, a configuration module 402 and a management module 403, wherein:

[0098] The determination module 401 is configured to determine the target bus link where the data processor is located in the multiple bus links supporting the peripheral component interface interconnection standard by enumerating the device supporting the peripheral component interface interconnection standard. The initial bus link uses a default link function configuration.

[0099] The configuration module 402 is configured to configure the target bus link to adopt a target link function configuration, and the target link function configuration supports a higher storage resource read-write bandwidth than the default link function configuration.

[0100] The management module 403 is configured to manage the storage resource of the data processor based on the target bus link.

[0101] The data processor storage resource management device provided by the application can determine the target bus link in which the DPU is located in the plurality of PCIe links through the determination module 401, and then can configure the target bus link to adopt the target link function configuration through the configuration module 402, and the target link function configuration supports a higher storage resource read-write bandwidth than the default link function configuration, that is, the target bus link after the configuration can support high-speed read-write of the storage resource of the DPU, fully adapt to the read-write bandwidth of the SSD, and then after entering the operating system, the management module 403 can manage the storage resource of the DPU based on the target bus link, and can efficiently use the storage resource of the DPU under the operating system.

[0102] Optionally, according to the data processor storage resource management device provided by the application, the configuration module is specifically configured to:

[0103] The environment variable corresponding to the target bus link in the target table is updated to a target value through the basic input and output system, and the target table is used to describe different hardware information of the system.

[0104] The target bus link is configured to adopt the target link function configuration based on the target table.

[0105] In the initial target table, the environment variable corresponding to each bus link is a default value, and the target value is different from the default value.

[0106] Optionally, the environment variable is a variable in the advanced configuration and power management interface protocol, and according to the data processor storage resource management device provided by the application, the configuration module is specifically configured to:

[0107] The bus link with the environment variable being the target value is screened out from the plurality of bus links through the advanced configuration and power management interface protocol based on the environment variable delivered by the target table.

[0108] The bus link with the environment variable being the target value is configured to adopt the target link function configuration.

[0109] Optionally, the application provides a storage resource management device of a data processor, wherein the determining module is specifically used for:

[0110] The target bus link where the data processor is located is determined among the plurality of bus links based on the vendor identification code and the version identification code of each bus device by enumerating the bus device.

[0111] Optionally, the application provides a storage resource management device of a data processor, wherein the management module is specifically used for:

[0112] determining one or more software objects to be installed;

[0113] For each software object to be installed, a first storage unit is divided from the storage resource of the data processor based on the target bus link, and the first storage unit is used to load the software object to be installed.

[0114] Optionally, the application provides a storage resource management device of a data processor, wherein the management module is specifically used for:

[0115] determining one or more software objects to be unloaded;

[0116] For each software object to be unloaded, a second storage unit is recycled to the storage resource of the data processor based on the target bus link, and the second storage unit is used to load the software object to be unloaded.

[0117] Optionally, the application provides a storage resource management device of a data processor, wherein the software object is an operating system, a driver or a business application.

[0118] The storage resource management device of the data processor provided by the application can determine the target bus link where the DPU is located among the plurality of PCIe links through the determining module 401 enumerating the PCIe device, and then the target bus link can be configured to adopt the target link function configuration through the configuration module 402, the storage resource read-write bandwidth supported by the target link function configuration is higher than that supported by the default link function configuration, that is, the target bus link after configuration can support high-speed reading and writing of the storage resource of the DPU, fully adapts to the read-write bandwidth of the SSD, and then after entering the operating system, the storage resource of the DPU can be quickly managed based on the target bus link through the management module 403, and the storage resource of the DPU can be efficiently used under the operating system.

[0119] Figure 5 is a structural schematic diagram of an electronic device provided by the application, such as Figure 5As shown, the electronic device can include a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor 510, the communications interface 520, and the memory 530 complete mutual communication through the communications bus 540. The processor 510 can invoke a logical instruction in the memory 530 to execute a storage resource management method of a data processor, the method comprising:

[0120] By enumerating a device supporting a peripheral component interconnect standard, determining a target bus link where the data processor is located in a plurality of bus links supporting the peripheral component interconnect standard, and initially configuring the bus link with a default link function;

[0121] Configuring the target bus link to use a target link function configuration, wherein a supported storage resource read-write bandwidth of the target link function configuration is higher than a supported storage resource read-write bandwidth of the default link function configuration;

[0122] Based on the target bus link, managing the storage resource of the data processor.

[0123] In addition, the logical instruction in the memory 530 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0124] On the other hand, the present application also provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer readable storage medium, when the computer program is executed by a processor, the computer can execute the storage resource management method of the data processor provided by the above-mentioned method, the method comprises:

[0125] enumerating peripheral component interconnect express standard supported devices, determining a target bus link where the data processor is located in a plurality of peripheral component interconnect express standard supported bus links, the initial bus link adopting a default link function configuration;

[0126] configuring the target bus link to adopt a target link function configuration, the target link function configuration supporting a higher storage resource read-write bandwidth than the default link function configuration;

[0127] managing storage resources of the data processor based on the target bus link.

[0128] In another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the storage resource management method of the data processor provided by the above method, the method comprising:

[0129] enumerating peripheral component interconnect express standard supported devices, determining a target bus link where the data processor is located in a plurality of peripheral component interconnect express standard supported bus links, the initial bus link adopting a default link function configuration;

[0130] configuring the target bus link to adopt a target link function configuration, the target link function configuration supporting a higher storage resource read-write bandwidth than the default link function configuration;

[0131] managing storage resources of the data processor based on the target bus link.

[0132] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0133] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0134] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of managing storage resources of a data processor, characterized by, The method comprises the following steps: determining a target bus link in which a data processor is located among a plurality of peripheral component interconnect standard (PCIe) bus links by enumerating PCIe devices, wherein the initial bus link adopts a default link function configuration; configuring the target bus link to adopt a target link function configuration, wherein a supported storage resource read-write bandwidth of the target link function configuration is higher than that of the default link function configuration; managing storage resources of the data processor based on the target bus link; the step of configuring the target bus link to adopt the target link function configuration comprises: updating an environment variable corresponding to the target bus link in a target table to a target value by a basic input / output system (BIOS), wherein the target table is used to describe different hardware information of a system; configuring the target bus link to adopt the target link function configuration based on the target table; wherein an environment variable corresponding to each bus link in an initial target table is a default value, and the target value is different from the default value; the environment variable is a variable in an advanced configuration and power interface (ACPI) protocol, and the step of configuring the target bus link to adopt the target link function configuration based on the target table comprises: selecting a bus link with the environment variable being the target value from the plurality of bus links by the ACPI protocol based on the environment variable delivered by the target table; configuring the bus link with the environment variable being the target value to adopt the target link function configuration.

2. The method of claim 1, wherein the data processor is a multi-processor system. The step of determining the target bus link in which the data processor is located among the plurality of PCIe bus links by enumerating the PCIe devices comprises: determining the target bus link in which the data processor is located among the plurality of bus links by enumerating bus devices based on a vendor identification (VID) and a version identification (VID) of each bus device.

3. The method of claim 1, wherein the data processor is a multi-processor system. The step of managing the storage resources of the data processor based on the target bus link comprises: determining one or more software objects to be installed; dividing a first storage unit from the storage resources of the data processor for each software object to be installed based on the target bus link, wherein the first storage unit is used to load the software object to be installed.

4. The method of claim 1, wherein the data processor is a multi-processor system. The step of managing the storage resources of the data processor based on the target bus link comprises: determining one or more software objects to be unloaded; recycling a second storage unit to the storage resources of the data processor for each software object to be unloaded based on the target bus link, wherein the second storage unit is used to load the software object to be unloaded.

5. The method of claim 3 or 4, wherein the data processor is a multi-processor system, and the memory resource is a shared memory resource. The software object is an operating system, a driver or a business application.

6. A storage resource management apparatus of a data processor, characterized by comprising: The method comprises the following steps: determining a target bus link in which a data processor is located among a plurality of peripheral component interconnect standard (PCIe) bus links by enumerating PCIe devices, wherein the initial bus link adopts a default link function configuration; The configuration module is configured to configure the target bus link to adopt a target link function configuration, and a read-write bandwidth of a storage resource supported by the target link function configuration is higher than a read-write bandwidth of a storage resource supported by the default link function configuration. The management module is configured to manage the storage resource of the data processor based on the target bus link. The configuration module is specifically configured to: update, by a basic input output system, an environment variable corresponding to the target bus link in a target table to a target value, the target table being used to describe different hardware information of a system; configure the target bus link to adopt the target link function configuration based on the target table; wherein an environment variable corresponding to each bus link in an initial target table is a default value, and the target value is different from the default value; the environment variable is a variable in a high-level configuration and power management interface protocol, and the configuration module is specifically configured to: select, by a high-level configuration and power management interface protocol, a bus link with the environment variable being the target value from a plurality of bus links based on the environment variable delivered by the target table; and configure the bus link with the environment variable being the target value to adopt the target link function configuration.

7. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the storage resource management method of the data processor according to any one of claims 1 to 5 when executing the program.

8. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the storage resource management method of the data processor according to any one of claims 1 to 5 when executed by the processor.

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