Code compiling method, electronic device and storage medium

Abstract

Embodiments of the present application disclose a code compiling method, an electronic device and a storage medium. The method comprises: obtaining N code blocks, wherein each code block contains a state identifier used for determining the running order of the code block, and N is an integer greater than or equal to 2; determining the running order of the N code blocks according to the state identifier encapsulated in each code block; and generating a pipeline according to the running order of the N code blocks and the N code blocks. The embodiments of the present application are beneficial to improving the pipeline generation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer software, in particular to a code compiling method, an electronic device and a storage medium. BACKGROUND

[0002] With the development of technology and the improvement of processor computing power, the requirement for operation speed is getting higher and higher. At present, a common acceleration method is a pipeline processing mode. A common implementation of the pipeline processing mode uses a double buffer mechanism to realize parallelism between different task flows, but the double buffer mechanism is difficult to apply to the case of complex task flows. With the increase in the number of tasks in the pipeline, the relationship between multiple tasks is also more complex, at which time the parsing of the code is more and more tedious and complex, and the implementation of the pipeline based on the code parsing will also become difficult. Therefore, how to efficiently and quickly construct a pipeline containing multiple tasks is a technical problem to be solved at present. SUMMARY

[0003] Embodiments of the present application provide a code compiling method, an electronic device and a storage medium, which improve the construction efficiency of the pipeline by setting a state identifier in a code block.

[0004] In a first aspect, embodiments of the present application provide a code compiling method, comprising:

[0005] obtaining N code blocks, wherein each code block contains a state identifier for determining the running order of the code block, and N is an integer greater than or equal to 2;

[0006] determining the running order of the N code blocks according to the state identifier encapsulated in each code block;

[0007] generating a pipeline according to the running order of the N code blocks and the N code blocks.

[0008] In an embodiment of the present application, the state identifier is used to indicate the task state of the task implemented by the code block, and the determination of the running order of the N code blocks according to the state identifier encapsulated in each code block comprises:

[0009] determining the dependency relationship between the N code blocks according to the task state indicated by the state identifier in the N code blocks;

[0010] determining the running order of the N code blocks according to the dependency relationship between the N code blocks.

[0011] In an embodiment of the present application, the task state of the task implemented by the N code blocks includes a data loading task, a data operation task and a data storage task.

[0012] In one pipeline, the code block implementing the data loading task, the code block implementing the data operation task and the code block implementing the data storage task are executed in sequence.

[0013] In one embodiment of the present application, the pipeline further comprises a code block;

[0014] The synchronization code block is contained between any two adjacent code blocks in the pipeline;

[0015] The synchronization code block is used to indicate that the (i+1)th code block is executed after the ith code block in the pipeline is executed, wherein i is a positive integer greater than or equal to 1 and less than or equal to N.

[0016] In one embodiment of the present application, the position identifier is further contained in each code block, and the position identifier is used to identify the starting position of the code block in the original code; and the N code blocks are obtained by:

[0017] The code between the jth position identifier and the (j+1)th position identifier in the original code and the jth position identifier are taken as the jth code block, and j is an integer from 1 to N.

[0018] In one embodiment of the present application, before the N code blocks are obtained, the method further comprises:

[0019] The value of the preset flag bit is obtained.

[0020] When the value of the preset flag bit is a preset value, the operation of obtaining the N code blocks is performed.

[0021] In one embodiment of the present application, the number of the pipelines is at least two, and the method further comprises:

[0022] According to the state identifier of each code block in the at least two pipelines, the code blocks in different pipelines in different task states are determined as a parallel code block group, and the plurality of code blocks in the parallel code block group can be executed in parallel in the same time unit.

[0023] In one embodiment of the present application, the parallel code block group is determined according to the state identifier of each code block in the at least two pipelines, and the code blocks in different pipelines in different task states are determined as a parallel code block group, and the plurality of code blocks in the parallel code block group can be executed in parallel in the same time unit.

[0024] When the kth code block in the first pipeline is executed, the (k-1)th code block in the second pipeline is executed in parallel, and the task state of the (k-1)th code block is different from the task state of the first pipeline;

[0025] The first pipeline is any one of the at least two pipelines, the second pipeline is a next pipeline of the first pipeline in the at least two pipelines, k is a positive integer greater than or equal to 2, and k is less than or equal to N.

[0026] In an embodiment of the present application, the method further comprises:

[0027] allocating memory for the parallel code block group, wherein the size of the memory is a product of the number of code blocks in the parallel code group and a preset memory size.

[0028] In an embodiment of the present application, the method further comprises:

[0029] compiling the original code formed by the N code blocks into target code.

[0030] In a second aspect, an embodiment of the present application provides a pipeline generation apparatus, comprising:

[0031] an obtaining unit configured to obtain N code blocks, wherein each code block contains a state identifier used to determine the running order of the code block, and N is an integer greater than or equal to 2;

[0032] a processing unit configured to determine the running order of the N code blocks according to the state identifier encapsulated in each code block;

[0033] generate a pipeline according to the running order of the N code blocks and the N code blocks.

[0034] In an embodiment of the present application, the state identifier is used to indicate the task state of a task implemented by the code block, and in the aspect of determining the running order of the N code blocks according to the state identifier encapsulated in each code block, the processing unit is specifically configured to:

[0035] determine the dependency relationship between the N code blocks according to the task state indicated by the state identifier in the N code blocks;

[0036] determine the running order of the N code blocks according to the dependency relationship between the N code blocks.

[0037] In an embodiment of the present application, the task state of the task implemented by the N code blocks includes a data loading task, a data operation task, and a data storage task.

[0038] In a pipeline, the code blocks implementing the data loading task, the code blocks implementing the data operation task, and the code blocks implementing the data storage task are executed in sequence.

[0039] In an embodiment of the present application, the pipeline further comprises a code block;

[0040] The synchronization code block is arranged between any two adjacent code blocks in the pipeline.

[0041] The synchronization code block is used to indicate that the (i+1)th code block is executed after the ith code block in the pipeline is executed, wherein i is a positive integer greater than or equal to 1 and less than or equal to N.

[0042] In an embodiment of the present application, each code block further comprises a position identifier, which is used to identify the starting position of the code block in the original code; and the obtaining unit is specifically configured to:

[0043] The code between the jth position identifier and the (j+1)th position identifier in the original code and the jth position identifier are taken as the jth code block, and j is an integer from 1 to N.

[0044] In an embodiment of the present application, before the N code blocks are obtained, the obtaining unit is further configured to obtain the value of a preset flag; and the processing unit is further configured to determine that the value of the preset flag is a preset value, and then execute the operation of obtaining the N code blocks.

[0045] In an embodiment of the present application, the number of the pipelines is at least two, and the processing unit is further configured to:

[0046] According to the state identifier of each code block in the at least two pipelines, the code blocks in different pipelines in different task states are determined as a parallel code block group, and the plurality of code blocks in the parallel code block group can be executed in parallel in the same time unit.

[0047] In an embodiment of the present application, according to the state identifier of each code block in the at least two pipelines, the code blocks in different pipelines in different task states are determined as a parallel code block group, and the processing unit is specifically configured to:

[0048] When the kth code block in the first pipeline is executed, the (k-1)th code block in the second pipeline is executed in parallel, and the task state of the (k-1)th code block is different from the task state of the first pipeline;

[0049] The first pipeline is any one of the at least two pipelines, the second pipeline is the next pipeline of the first pipeline in the at least two pipelines, k is a positive integer greater than or equal to 2 and less than or equal to N.

[0050] In an embodiment of the present application, the processing unit is further configured to allocate memory for the parallel code block group, wherein the size of the memory is the product of the number of code blocks in the parallel code group and a preset memory size.

[0051] In an embodiment of the present application, the processing unit is further configured to compile the original code formed by the N code blocks into target code.

[0052] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, the processor being connected with a memory, the memory being configured to store a computer program, and the processor being configured to execute the computer program stored in the memory, so that the electronic device executes the method in the first aspect.

[0053] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium storing a computer program, and the computer program causing a computer to execute the method in the first aspect.

[0054] In a fifth aspect, an embodiment of the present application provides a computer program product, the computer program product including a non-transitory computer readable storage medium storing a computer program, and the computer being operable to cause a computer to execute the method in the first aspect.

[0055] The embodiment of the present application has the following beneficial effects:

[0056] It can be seen that, in the embodiment of the present application, the code blocks are provided with state identifiers, and the running order of the code blocks of each task can be directly determined according to the state identifiers, without the need to determine the running order of the code blocks of each task by analyzing the functions of the codes and the data flow among the code blocks, so as to realize the rapid and efficient construction of the pipeline. Further, since the state identifiers are encapsulated in each code block, for the scene of a complex task flow, the present application can generate a corresponding pipeline for each task flow according to the above implementation manner, and the manner of generating the pipeline will not be limited by hardware resources (such as the number of memory partitions), so as to support the scene of a complex task flow. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0058] Figure 1 A schematic diagram of an implementation process of a double buffer mechanism provided by an embodiment of the present application;

[0059] Figure 2 A flowchart of a code compiling method provided by an embodiment of the present application is shown in FIG. 1.

[0060] Figure 3 A schematic diagram of obtaining a code block provided by an embodiment of the present application is shown in FIG. 2.

[0061] Figure 4 A schematic diagram of a composition pipeline provided by an embodiment of the present application is shown in FIG. 3.

[0062] Figure 5 A schematic diagram of another composition pipeline provided by an embodiment of the present application is shown in FIG. 4.

[0063] Figure 6 A schematic diagram of still another composition pipeline provided by an embodiment of the present application is shown in FIG. 5.

[0064] Figure 7 A function unit composition block diagram of a pipeline generation apparatus provided by an embodiment of the present application is shown in FIG. 6.

[0065] Figure 8 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 7. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0067] The terms "first", "second", "third", and "fourth" and the like in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a particular order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include other steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0068] In this document, the term "embodiment" means that a particular feature, result, or characteristic described in connection with an embodiment can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily mutually exclusive or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0069] In order to efficiently perform different tasks, the computing resources of the hardware are fully utilized, and tasks that are dependent on each other are often composed into a pipeline, so that tasks in different pipelines that do not depend on each other can be executed in parallel, thereby improving the execution efficiency of the tasks. For different processing scenarios, the generation and implementation of the task pipeline can have many different ways, and the purpose of the present disclosure is to provide a generation method, device and related product for a multi-stage pipeline of a complex task flow.

[0070] A common pipeline implementation is to use storage partitioning, and the data in different storage blocks can be sent to the operation unit in turn for operation, but this implementation can only support simple task flows of at most two pipelines, and is difficult to apply to complex task flow scenarios. For example, Figure 1 A process of implementing a task pipeline using a double buffer mechanism is shown, and the following describes the process of implementing the double buffer mechanism. Figure 1 The implementation process of the current double buffer mechanism is introduced.

[0071] As shown in Figure 1 To reduce the waiting time of the operation unit, the storage space of the unified cache can be divided into two parts, for example, the unified cache is split into a first cache and a second cache. When the operation unit reads and calculates the data in the first cache, the storage unit can write the next data into the second cache in parallel. When the operation unit switches to reading and calculating the data in the second cache, the storage unit can write the calculation results stored in the first cache to the storage unit in parallel, or the storage unit can write the next data into the first cache in parallel. Thus, the data access task and the operation unit calculation task can be executed in parallel, thereby effectively alleviating the idle problem of the operation unit, improving the utilization rate of the operation unit, and improving the execution efficiency of the task. However, the double buffer mechanism is implemented for each task by analyzing the underlying code to find the code content of each task, and then implementing the task based on the code content. For example, for the calculation task of the operation unit in a pipeline, the underlying code is analyzed to find the code content that can implement the calculation task, and the calculation task is implemented by executing the code content. However, as the number of tasks in the pipeline increases, the analysis of the code becomes more and more tedious and complex. Therefore, how to efficiently construct a pipeline that supports multiple tasks is a technical problem to be solved at present.

[0072] Referring to Figure 2 , Figure 2 A flowchart of a code compilation method provided by an embodiment of the present application is shown. The method can be implemented by a compiler running on a processor (such as a general-purpose processor CPU, etc.). The method can include the following steps:

[0073] 201: obtaining N code blocks, N is an integer greater than or equal to 2.

[0074] Each code block has a function to implement a task, so the execution of a code block mentioned in the present application is essentially the execution of a task, and the two are essentially consistent and do not need to be distinguished. In addition, different code blocks have different functions, that is, different code blocks are used to implement different types of tasks. In the present application, the tasks implemented by the N code blocks are mainly data loading tasks (data_load), data computing tasks (data_computer) and data storage tasks (data_store) are exemplarily illustrated, and in actual application, there can be other task states, which will not be described in detail.

[0075] The present application can first obtain the original code and obtain N code blocks based on the original code. For example, the original code is pre-provided with at least one code block identifier, i.e. a position identifier; in this way, when the original code is parsed, the code between the position identifier and the next position identifier can be taken as a code block to obtain N code blocks.

[0076] Specifically, the position identifier can be placed in each code block, and the position identifier is used to identify the starting position of the code block in the original code. Therefore, for the N code blocks, N position identifiers are set in the original code. When parsing the original code, the code between the jth position identifier and the j+1th position identifier, and the jth position identifier are taken as the jth code block, and j takes an integer value of 1 to N.

[0077] Optionally, the with block level scope in the present application encapsulates the code block corresponding to each task to obtain the original code. The position identifier mentioned in the present application can be represented by using a block level identifier, for example, with IR.block. Then, in the process of parsing the original code, if the with IR.block identifier is identified, the with IR.block and the code between the with IR.block and the next with IR.block can be taken as a code block to obtain N code blocks. Wherein, the IR in the position identifier represents the code level of the original code. In an implementable manner, the code level of the original code includes but is not limited to high-level Python code, low-level Python code and lower-level target code, and the target code can be a code formed by using a C-like language (for example, CUDAC). Wherein, the low-level Python code can be a code formed by using a tensor computing primitive based on the Python language, for example, TCP (Tensor Computer Primitive) or TIK (Tensor Iterator Kernel).

[0078] For example, for the three tasks to be implemented in the present application, the with tcp.block can be taken as the position identifier. As shown in Figure 3 , the first with tcp.block and the code between the first with tcp.block and the second with tcp.block can be taken as the first code block, the second with tcp.block and the code between the second with tcp.block and the third with tcp.block can be taken as the second code block, and the code between the third with tcp.block and the end of the code can be taken as the third code block.

[0079] 202: Determine the running order of the N code blocks according to the state identifier encapsulated in each code block.

[0080] Wherein, each code block contains a state identifier for determining the running order of the code block.

[0081] For example, the state identifier in each code block can be used to indicate the task state of the task implemented by the code block. Optionally, the state identifier can be represented by the function of each code block itself, that is, by the function of each code block itself to indicate the task state of the task implemented by each code block.

[0082] For example, as shown in Figure 3As shown, the state identifier of the first code block for implementing the data loading task can be "stage_scope=load", and thus, when the state identifier of the code block is parsed as "stage_scope=load", it is determined that the task implemented by the code is the data loading task. The state identifier of the second code block for implementing the data operation task can be "stage_scope=computer", and thus, when the state identifier of the code block is parsed as "stage_scope=computer", it is determined that the task implemented by the code is the data operation task. The state identifier of the third code block for implementing the data storage task can be "stage_scope=store", and thus, when the state identifier of the code block is parsed as "stage_scope=store", it is determined that the task implemented by the code is the data storage task. Through the above steps, the present application can obtain three code blocks for implementing the data loading task, the data operation task and the data storage task respectively. Subsequently, the present application can determine the running order of the three code blocks according to the dependency relationship between the tasks implemented by the three code blocks.

[0083] Further, the dependency relationship of the N code blocks is determined according to the task state indicated by the state identifier in the N codes. The dependency relationship is the data flow between the code blocks. Thus, the running order of the N code blocks can be determined according to the dependency relationship between the N code blocks.

[0084] For example, for the data loading task, the data operation task and the data storage task, the dependency relationship is that the data operation task depends on the data loading task, and the data storage task depends on the data operation task, and thus, the dependency relationship between the code blocks corresponding to the three tasks is that the code block for implementing the data operation task depends on the code block for implementing the data loading task, and the code block for implementing the data storage task depends on the code block for implementing the data operation task. Thus, in the pipeline, the code block for implementing the data loading task, the code block for implementing the data operation task and the code block for implementing the data storage task need to be executed in sequence. It should be clear that the data loaded by the data loading task is the input data of the data operation task, and the data written by the data storage task is the output data of the data operation task, and thus, there is a data dependency relationship between the three tasks. Otherwise, in other scenarios, the above three tasks do not necessarily have a data dependency relationship.

[0085] In one possible implementation, the running order of each code block can be directly encapsulated in the code block, for example, the state identifier of each code block can be directly set as the running order of the code block. For example, for the code block used to implement the data loading task, the state identifier thereof can be set as "1", so that after the code block is obtained, the running order of the code block can be directly determined as the first one based on the state identifier "1" of the code block, without the need to determine the dependency relationship of the N code blocks according to the task state of the task implemented by each code block, and then determine the running order of the N code blocks according to the dependency relationship, thereby improving the construction efficiency of the pipeline.

[0086] 203: generating a pipeline according to the running order of the N code blocks and the N code blocks.

[0087] For example, the N code blocks can be automatically combined to generate a pipeline according to the running order of the N code blocks.

[0088] For example, for the three code blocks of the present application, the three code blocks can be combined to form a pipeline as shown in Figure 4

[0089] As can be seen, in the embodiments of the present application, the state identifier is placed in the code block, and the running order of the code block of each task can be directly determined according to the state identifier, without the need to determine the running order of the code block of each task by analyzing the function of the code and the data flow between the code blocks, thereby realizing the rapid and efficient construction of the pipeline. Further, since the state identifier is encapsulated in each code block, for the complex task flow scenario, the present application can generate a corresponding pipeline for each task flow according to the above implementation, and the pipeline generation manner is not limited by the hardware resources (such as the number of storage partitions), thereby being able to support the complex task flow scenario.

[0090] ​In one embodiment of the present application, a synchronization code block is inserted between any two adjacent code blocks in the pipeline, which indicates that the (i+1)th code block is executed after the ith code block is executed, where i is a positive integer greater than or equal to 1 and less than or equal to N. Although the N code blocks are combined according to the execution order, the execution time of some code blocks can be relatively long. In order to completely ensure the sequential execution of the N code blocks, a synchronization code block is inserted between any two adjacent code blocks, so that for the two adjacent code blocks, the next code block is executed only after the previous code block is executed. From the perspective of task execution, each synchronization code block implements a synchronization task, that is, a synchronization task is inserted between any two adjacent tasks implemented by the two adjacent code blocks, so that for the two adjacent tasks in the pipeline, the next task is executed only after the previous task is executed, thereby realizing the sequential execution of the N tasks in the pipeline. Inserting a synchronization code block between any two adjacent code blocks in the pipeline can generate a pipeline with inserted synchronization code blocks as shown in Figure 5

[0091] In one embodiment of the present application, the number of the generated pipelines is at least two, that is, the N code blocks can be combined into two or more pipelines. For each pipeline, the N code blocks are combined according to the execution order, which will not be described again. For example, for three code blocks in the present application, three pipelines can be formed according to the order of the code blocks as shown in Figure 6 , and a synchronization code block is inserted between any two adjacent code blocks in each pipeline, so as to ensure that the three code blocks in each pipeline are executed sequentially.

[0092] As shown in Figure 2 or Figure 6 , the pipeline can be a serial pipeline formed by a timeline. The pipeline of the present application can also include parallel pipelines formed based on different task states. Further, according to the state identifier of each code block in the at least two pipelines, the code blocks in different pipelines in different task states can be determined as a parallel code block group, and the multiple code blocks in the parallel code block group are executed in parallel in a same time unit, and the parallel code block group can form a parallel pipeline.

[0093] Specifically, the at least two pipelines can have priorities. For example, for Figure 6 ​The priority of the top pipeline is the highest, and the priority of other pipelines decreases in turn. The priority of at least two pipelines in the application can be determined based on different iteration periods. For example, the at least two pipelines can be different iteration periods in the same loop. From the time line, the priority of the pipeline executed first is higher than the priority of the pipeline executed later, where the iteration period of the pipeline executed first is less than the iteration period of the pipeline executed later. As shown in FIG. 2, a loop can include three iteration periods, where the three iteration periods correspond to three pipelines in the loop in terms of their priorities. Figure 6 Figure 6 In order to improve the parallelism of tasks between different pipelines and the execution efficiency of tasks, the code blocks in different task states in different pipelines can be determined as a parallel code block group, and the multiple code blocks in the parallel code block group are executed in parallel in the same time unit, so that the task pipeline of the tasks implemented by different code blocks can be realized, and the operation efficiency and hardware utilization rate can be improved.

[0094] Since the N code blocks are used to implement different serial tasks, and different hardware resources are called between adjacent two tasks (such as storage and calculation of two different resources are called by adjacent two tasks), the code block group can be composed in the following manner for the at least two pipelines:

[0095] When the kth code block in the first pipeline is executed, the k-1th code block in the second pipeline is executed in parallel, that is, the kth code block in the first pipeline and the k-1th code block in the second pipeline are taken as a code block group; where the first pipeline is any one of the at least two pipelines, the second pipeline is the next pipeline of the first pipeline in the at least two pipelines, and k is an integer from 2 to N.

[0096] ​Specifically, for hardware resources, generally, two tasks in the same task state are not executed simultaneously in a time unit, and thus, for a task in a task state, in a time unit, the corresponding hardware resource is allocated to execute the task. For example, for the three tasks in the present application, in the first time unit, the storage resource is allocated to the data loading task of the first pipeline, so as to execute the first code block of the first pipeline; in the second time unit, since the first code block of the first pipeline has been executed, the calculation resource is allocated to the data operation task of the first pipeline, and since the storage resource is idle, the second code block of the first pipeline and the first code block of the second pipeline are taken as a code block group, and thus, in the second time unit, the two code blocks in the code block group can be executed in parallel using the storage resource and the calculation resource. By analogy, in the third time unit, the third code block of the first pipeline, the second code block of the second pipeline and the first code block of the third pipeline are taken as a code block group, and thus, in the third time unit, the three code blocks in the code block group can be executed in parallel using the storage resource and the calculation resource. Therefore, for the case that the N code blocks are contained in the plurality of pipelines, in the Nth time unit, the N code blocks are taken as a code block group, so as to execute the N code blocks in parallel, and the parallel execution of the N tasks is realized.

[0097] Further, the present application is also used to insert the synchronization task between different pipelines, so as to ensure that the code blocks can be executed in parallel. That is, the synchronization code block is inserted between the adjacent code blocks in each iteration cycle, so as to realize the synchronization task. For example, the synchronization code block is inserted between the code block for completing the data storage task in the first iteration cycle and the code block for completing the data loading task in the second iteration cycle, so as to realize the synchronization task.

[0098] In an embodiment of the present application, the method can further comprise allocating the memory for the code block group.

[0099] Optionally, the size of the memory is the product of the number of code blocks in the parallel code block group and the preset storage space size, and the size of the memory can also be equal to the maximum number of code blocks that can be contained in the parallel code block. The preset space size is related to the size of the data to be processed. It can be understood that for each code block group, in the same time unit, all the code blocks in the code block group need to be executed in parallel, and thus, each code block needs to have the corresponding memory to cache the running result of the code block, and thus, according to the number of code blocks in the code block group, the memory is allocated to all the code blocks at one time, and thus, it is not necessary to allocate the memory to each code block separately, and the efficiency of the memory allocation can be improved.

[0100] For example, if the data to be processed is two-dimensional data, the size of the two-dimensional data can be represented by m*n, where m represents the size of the data to be processed in the first dimension, and n represents the size of the data to be processed in the second dimension. If the original code is to complete the processing of the data to be processed, m iteration cycles are required, and each iteration cycle processes data with a size of n. In each iteration cycle, the data loading task, the data calculation task, and the data storage task are sequentially completed along one pipeline of the timeline. Figure 6 For the data processing of each iteration cycle, a preset storage space is required to complete the processing of the data to be processed with a size of n. In an embodiment of the present application, to support the implementation of the multi-level pipeline, memory can be allocated for the entire parallel code block group at one time, where the size of the memory can be equal to the number N of parallel code blocks multiplied by the size n of the preset storage space required in a single iteration cycle. As shown in Figure 6 the size of the memory can be 3n.

[0101] In an embodiment of the present application, an automatic pipeline generation mode and a normal mode can be included, where the automatic pipeline generation mode refers to automatically generating a pipeline according to the state identifier in the code block, such as the method steps described above. The normal mode refers to a way of generating a pipeline according to a traditional code analysis method. To support the switching between the two modes, the present disclosure can further set a preset flag in the original code to implement the mode switching. Specifically, during the process of parsing the original code, when it is determined that the value of the preset flag is a preset value, it is determined to enable the automatic pipeline generation mode, and when it is determined that the value of the preset flag is not the preset value, it is determined to enable the normal mode, where the preset value can be 1 or other values.

[0102] In the present embodiment, a flag is preset, and when it is read that the value of the preset flag is a preset value, it is determined that the automatic pipeline generation mode needs to be enabled, at which time N code blocks are obtained, and the N code blocks are combined into a pipeline in the manner shown in Figure 2 or Figure 6 Specifically, if it is determined to enable the automatic pipeline generation mode, the memory allocation operation described above can be automatically completed. If the value of the preset flag is not the preset value, it is determined to enable the normal mode, at which time N code blocks are not obtained, and a pipeline is generated according to the traditional code analysis method according to the writing order of the original code.

[0103] In an embodiment of the present application, the above method can further include:

[0104] The original code formed by the N code blocks is compiled into target code, which can be C language representation code (such as CudaC). In the embodiment of the present application, the original code after pipeline optimization can be compiled to generate target code. Further, the present application can also compile the target code into binary instructions executable by a hardware platform. The hardware platform includes but is not limited to a processing unit and a storage unit, wherein the processing unit and the storage unit can complete corresponding operations in the manner of the pipeline shown in the figure. Figure 6

[0105] Referring to Figure 7 , Figure 7 The embodiment of the present application provides a function unit composition block diagram of a pipeline generation device. The pipeline generation device 700 includes:

[0106] An acquisition unit 701 is configured to acquire N code blocks, wherein each code block contains a state identifier for determining the running order of the code block, and N is an integer greater than or equal to 2;

[0107] A processing unit 702 is configured to determine the running order of the N code blocks according to the state identifier encapsulated in each code block;

[0108] A pipeline is generated according to the running order of the N code blocks and the N code blocks.

[0109] In an embodiment of the present application, the state identifier is used to indicate the task state of a task implemented by the code block, and in the aspect of determining the running order of the N code blocks according to the state identifier encapsulated in each code block, the processing unit 702 is specifically configured to:

[0110] Determine the dependency relationship between the N code blocks according to the task state indicated by the state identifier in the N code blocks;

[0111] Determine the running order of the N code blocks according to the dependency relationship between the N code blocks.

[0112] In an embodiment of the present application, the task state of the task implemented by the N code blocks includes a data loading task, a data operation task and a data storage task;

[0113] In a pipeline, the code blocks implementing the data loading task, the data operation task and the data storage task are executed in sequence.

[0114] In an embodiment of the present application, the pipeline further includes a code block;

[0115] ​The synchronization code block is used to indicate that the (i+1)th code block is executed after the ith code block in the pipeline is executed, wherein i is a positive integer greater than or equal to 1, and i is less than or equal to N.

[0116] The synchronization code block is used to indicate that the (i+1)th code block is executed after the ith code block in the pipeline is executed, wherein i is a positive integer greater than or equal to 1, and i is less than or equal to N.

[0117] In an embodiment of the present application, each of the code blocks further comprises a position identifier, which is used to identify the starting position of the code block in the original code; in the aspect of obtaining the N code blocks, the obtaining unit 702 is specifically used for:

[0118] obtaining the code between the jth position identifier and the (j+1)th position identifier in the original code, and the jth position identifier as the jth code block, wherein j is an integer from 1 to N.

[0119] In an embodiment of the present application, before the N code blocks are obtained, the obtaining unit 701 is further used to obtain the value of a preset flag; and the processing unit 702 is further used to determine that when the value of the preset flag is a preset value, the operation of obtaining the N code blocks is performed.

[0120] In an embodiment of the present application, the number of the pipelines is at least two, and the processing unit 702 is further used to:

[0121] According to the state identifier of each code block in the at least two pipelines, the code blocks in different pipelines in different task states are determined as a parallel code block group, and the plurality of code blocks in the parallel code block group can be executed in parallel in the same time unit.

[0122] In an embodiment of the present application, in the aspect of determining the code blocks in different pipelines in different task states as the parallel code block group according to the state identifier of each code block in the at least two pipelines, the processing unit 702 is specifically used for:

[0123] When the kth code block in the first pipeline is executed, the (k-1)th code block in the second pipeline is executed in parallel, and the task state of the (k-1)th code block is different from the task state of the first pipeline;

[0124] wherein the first pipeline is any one of the at least two pipelines, the second pipeline is a next pipeline of the first pipeline in the at least two pipelines, k is a positive integer greater than or equal to 2, and k is less than or equal to N.

[0125] In one embodiment of this application, the processing unit 702 is further configured to allocate memory for the parallel code block group, wherein the size of the memory is the product of the number of code blocks in the parallel code group and the preset storage space size.

[0126] In one embodiment of this application, the processing unit 702 is further configured to compile the original code formed by the N code blocks into object code.

[0127] See Figure 8 , Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 8 As shown, the electronic device 800 includes a transceiver 801, a processor 802, and a memory 803. These are connected via a bus 804. The memory 803 stores computer programs and data, and can transfer data stored in the memory 803 to the processor 802.

[0128] Processor 802 is used to read the computer program in memory 803 and perform the following operations:

[0129] Obtain N code blocks, where each code block contains a status flag used to determine the execution order of the code block, and N is an integer greater than or equal to 2;

[0130] The execution order of the N code blocks is determined based on the state identifier encapsulated in each code block;

[0131] A pipeline is generated based on the execution order of the N code blocks and the N code blocks themselves.

[0132] The specific functions of the processor 802 can be referred to the specific functions of the processing unit 702 and the acquisition unit 701 mentioned above, and will not be described again.

[0133] This application also provides a computer-readable storage medium storing a computer program that is executed by a processor to implement some or all of the steps of any of the code compilation methods described in the above method embodiments.

[0134] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the code compilation methods described in the above method embodiments.

[0135] It should be noted that, for the foregoing method embodiments, the sequences of the described actions are not the only ones that can be used to implement the present application. In some embodiments, the sequences of the actions described in the foregoing embodiments can be changed or the actions described in the foregoing embodiments can be performed in parallel. In addition, it should be noted that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0136] In the above embodiments, the description of each embodiment is focused on the description of the embodiment, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0137] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented by other means. For example, the apparatus embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical or other forms.

[0138] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment.

[0139] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software program module.

[0140] If the integrated unit is realized in the form of a software program module and sold or used as an independent product, it can be stored in a computer readable memory. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a memory and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0141] A person of ordinary skill in the art can understand that all or part of the steps in the above-mentioned embodiments can be completed by instructing the relevant hardware through a program, which can be stored in a computer readable memory. The memory can include a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0142] The embodiments of the present application are described in detail above, and the specific examples are applied to the principles and implementation modes of the present application. The above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed; in summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A code compiling method characterized by, The method comprises the following steps: acquiring N code blocks, wherein each code block contains a state identifier for determining the running order of the code block, and N is an integer greater than or equal to 2; determining the running order of the N code blocks according to the state identifier encapsulated in each code block; generating a pipeline according to the running order of the N code blocks and the N code blocks. Each code block further contains a position identifier for identifying the starting position of the code block in the original code; the step of acquiring the N code blocks comprises the following steps: taking the code between the jth position identifier and the (j+1)th position identifier in the original code and the jth position identifier as the jth code block, wherein j is an integer from 1 to N.

2. The method of claim 1, wherein, The state identifier is used to indicate the task state of the task implemented by the code block; the step of determining the running order of the N code blocks according to the state identifier encapsulated in each code block comprises the following steps: determining the dependency relationship between the N code blocks according to the task state indicated by the state identifier in the N code blocks; determining the running order of the N code blocks according to the dependency relationship between the N code blocks.

3. The method according to claim 1 or 2, characterized in that, The task state of the task implemented by the N code blocks comprises a data loading task, a data operation task and a data storage task; In one pipeline, the code blocks implementing the data loading task, the code blocks implementing the data operation task and the code blocks implementing the data storage task are executed in sequence.

4. The method according to any one of claims 1 to 3, characterized in that, The number of the pipelines is at least two; the method further comprises the following steps: determining the code blocks in different task states in different pipelines as a parallel code block group according to the state identifier of each code block in the at least two pipelines, and the plurality of code blocks in the parallel code block group can be executed in parallel in the same time unit.

5. The method of claim 4, wherein, The step of determining the code blocks in different task states in different pipelines as a parallel code block group according to the state identifier of each code block in the at least two pipelines comprises the following steps: when the kth code block in the first pipeline is executed, the (k-1)th code block in the second pipeline is executed in parallel, and the task state of the (k-1)th code block is different from the task state of the first pipeline; wherein the first pipeline is any one of the at least two pipelines, the second pipeline is the next pipeline of the first pipeline in the at least two pipelines, k is a positive integer greater than or equal to 2, and k is less than or equal to N.

6. The method according to claim 4 or 5, characterized in that, The method further comprises the following steps: allocating memory for the parallel code block group, wherein the size of the memory is the product of the number of code blocks in the parallel code block group and a preset storage space size.

7. The method according to any one of claims 1 to 6, characterized in that, The method further comprises the following steps: acquiring the value of a preset flag bit; when the value of the preset flag bit is a preset value, entering an automatic pipeline generation mode to automatically generate a pipeline according to the state identifier encapsulated in each code block.

8. The method according to any one of claims 1 to 7, characterized in that, The method further comprises the following steps: compiling the original code formed by the N code blocks into target code.

9. An electronic device, comprising: The method comprises the following steps: A processor and a memory, the processor being connected with the memory, the memory being used for storing a computer program, and the processor being used for executing the computer program stored in the memory, so that the electronic device executes the method in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method in any one of claims 1-8.

Images