A multi-core processor shared data access design method based on spin lock

Abstract

The application relates to a multi-core processor shared data access design method based on a spin lock. Two 4N-bit anti-radiation reinforced atomic lock registers are designed, atomic locks of the two registers can be realized, each register can be divided into two parts of high 2N bits and low 2N bits, the low 2N bits save the identification number COREn_ID of a processor core which is applying for the atomic lock of the register, and the high 2N bits save the identification number LOCKn_ID of a processor core which is currently acquiring the atomic lock of the register. The application can reduce the dependence of atomic operation on software algorithms in the process of multi-core task scheduling, and further reduce thread execution errors caused by malicious attacks on the atomic operation software algorithms, and is a high-safety and high-reliability multi-core scheduling atomic lock implementation method.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of thread synchronization, and relates to a multi-core processor shared data access design method based on a high-safety and high-reliability spin lock. BACKGROUND

[0002] A common general multi-core processor system (such as a desktop, a server, a mobile high-performance multi-core processor, etc.) adopts an atomic lock query and acquisition mode to protect system shared resources according to the demand of high performance and high real-time scheduling in an application scenario, and sets an atomic lock in an external memory such as a DDR through processor execution of an atomic lock operation, performs locking and unlocking protection operations on the access of some multi-core shared resources, avoids the access conflict caused by the simultaneous access of other cores or other threads to shared data.

[0003] A multi-core processor developed for an aerospace application scenario may be affected by cosmic environment radiation in the storage of atomic lock data in an external memory such as a DDR from the perspective of high-reliability design; from the perspective of high-safety design, the multi-core scheduling of an existing operating system mainly depends on a software algorithm, and may be attacked by malicious attacks on atomic operations, causing thread execution errors, and even leading to the collapse of a multi-core system. In order to ensure the reliability of a task, a safer scheduling method is to realize relatively fixed scheduling according to application program requirements, and reduce the dependence on a software algorithm. SUMMARY

[0004] The application solves the problem: in view of the high-reliability and high-safety application requirements of a multi-core processor in the aerospace field, a register atomic lock operation meeting the fixed scheduling requirement is proposed, which is a high-safety and high-reliability multi-core scheduling atomic lock implementation method.

[0005] The technical scheme of the application is: a multi-core processor shared data access design method based on a spin lock, which realizes the scheduling of thread access to shared data by providing a register atomic lock to a multi-core processor; the register atomic lock is realized by a 4N-bit atomic lock register; N is the number of cores of the processor;

[0006] The atomic lock register is divided into a high 2N-bit part and a low 2N-bit part;

[0007] The low 2N-bit part of the atomic lock register is set as a COREn_ID area, and the identification number COREn_ID of the processor core currently applying for the register atomic lock is saved, wherein the low N-bit part of the COREn_ID area represents the value of COREn_ID, and the high N-bit COREn_ID_WEN is the write enable of the low N-bit part corresponding bit;

[0008] The high 2N bits of the atomic lock register are set as LOCKn_ID area, which stores the identification number LOCKn_ID of the processor core currently attempting to acquire the atomic lock of the register, wherein the low N bits of the LOCKn_ID area represent the value of the LOCKn_ID, and the high N bits LOCKn_ID_WEN are the write enable of the low N bits;

[0009] Each processor core has the same opportunity to acquire the register atomic lock;

[0010] At the same time, the same register atomic lock can be acquired by at most one processor core.

[0011] Preferably, the number of bits of the atomic lock register is determined according to the number of processor cores, and each atomic lock register implements a register atomic lock. The register atomic lock implemented by a single 4N-bit atomic lock register is suitable for access scheduling of at most N processor cores to a shared address.

[0012] Preferably, the LOCKn_ID area in the atomic lock register for storing the identification number of the processor core currently attempting to acquire the atomic lock of the register includes:

[0013] The low N bits LOCKn_ID of the area can be written only when the corresponding enable bit is valid, and the LOCKn_ID can only be read when the corresponding enable bit is invalid. When the value of the LOCKn_ID is 0, it represents that the register atomic lock is in a released state. When the value of the LOCKn_ID is not 0, the value represents the identification number of the processor core currently attempting to acquire the atomic lock of the register;

[0014] The high N bits LOCKn_ID_WEN of the area are the enable bits of the LOCKn_ID, which respectively correspond to the write enable of the low N bits. When the enable bit is high, it is valid. When the enable bit is low, it is invalid. After the LOCKn_ID_WEN is written, the hardware will automatically clear it.

[0015] Preferably, the COREn_ID area in the atomic lock register for storing the identification number of the processor core currently attempting to acquire the atomic lock of the register includes:

[0016] The low N bits COREn_ID of the area can be written only when the corresponding enable bit is valid, and the COREn_ID can only be read when the corresponding enable bit is invalid. The COREn_ID stores the identification number of each processor core currently attempting to acquire the atomic lock of the register;

[0017] The high N bits COREn_ID_WEN of the area are the enable bits of the COREn_ID, which respectively correspond to the write enable of the low N bits. When the enable bit is high, it is valid. When the enable bit is low, it is invalid. After the COREn_ID_WEN is written, the hardware will automatically clear it.

[0018] Preferably, the processor core obtaining the register atomic lock comprises:

[0019] The processor core requests the register atomic lock, reads the value of LOCKn_ID in the atomic lock register corresponding to the register atomic lock, judges whether the atomic lock register is in the released state, if yes, writes the identification number of the processor core into the COREn_ID area in the atomic lock register, otherwise, exits the request;

[0020] reads the identification number of the processor core currently requesting the atomic lock from the COREn_ID area in the atomic lock register, and judges the priority according to the read value, when the processor core has the highest priority, writes the identification number of the processor core into the LOCKn_ID in the atomic lock register, otherwise, clears the identification number of the processor core in the COREn_ID area;

[0021] judges whether the processor core in the LOCKn_ID in the atomic lock register is unique, if yes, the processor core successfully obtains the register atomic lock, otherwise, clears the identification number of the processor core in the LOCKn_ID area and the COREn_ID area in the atomic lock register, and releases the register atomic lock.

[0022] Preferably, the priority judgment mode of each processor core requesting the register atomic lock is a polling mode, in one priority judgment, the next processor core adjacent to the processor core that has obtained the atomic lock last time is preferentially authorized, and if the processor core preferentially authorized is idle, the priority is extended to the next adjacent processor core.

[0023] Preferably, the identification number of the processor core that has obtained the register atomic lock last time is saved in the atomic lock history register, which is used for priority judgment.

[0024] Preferably, for the operating system of the multi-core processor, the unlimited atomic lock is realized by combining the global variable lock and the register atomic lock, so as to meet the scheduling requirements of different application scenarios in the operating system.

[0025] Preferably, the operating system of the multi-core processor saves the lock used for inter-thread scheduling in the global variable lock, sets the global variable locks saved in different addresses according to the number requirements of the applications, so as to realize the atomic lock number meeting the application requirements.

[0026] Preferably, the processor core locks and unlocks the register atomic lock before and after performing the access operation on the global variable lock, so as to protect the access operation, and the access operation of the processor core on the global variable lock comprises:

[0027] reading the global variable to obtain the value of the current global variable lock;

[0028] comparing the value of the current global variable lock with an expected value to determine whether the lock is in a released state;

[0029] if the global variable lock is not in the released state, the request fails;

[0030] if the global variable lock is in the released state, the processor core acquires the lock and writes a new value to the global variable to indicate that the lock is occupied.

[0031] Preferably, the locking operation of the register atomic lock comprises: requesting the register atomic lock, if it is determined that the value of LOCKn_ID in the atomic lock register is the identification number of the current processor core, then the request is not determined to fail, and the request operation is continued after the atomic lock nesting flag is set, so as to ensure that the deadlock situation caused by requesting the same register atomic lock again after the processor core holding the register atomic lock is interrupted does not occur.

[0032] Preferably, the method further comprises:

[0033] After the processor core completes the access operation of the global variable lock under the protection of the register atomic lock, the unlocking operation of the register atomic lock comprises:

[0034] determining whether there is an atomic lock nesting flag and whether the request for the global variable lock is successful;

[0035] if the request for the global variable lock is not successful, releasing the register atomic lock and requesting the register atomic lock and the global variable lock again;

[0036] if the request for the global variable lock is successful and there is no atomic lock nesting flag, releasing the register atomic lock;

[0037] if the request for the global variable lock is successful and there is an atomic lock nesting flag, not releasing the register atomic lock until the program for the unlocking operation of the register atomic lock is interrupted.

[0038] Preferably, the global variable lock is released by writing a specific value representing an idle lock into the corresponding global variable.

[0039] A multi-core processor shared data access system based on a spin lock, comprising a register atomic lock, through which the scheduling of shared data access between different threads of the multi-core processor is realized; each processor core has the same opportunity to acquire the register atomic lock; at the same time, at most one processor core can acquire the same register atomic lock;

[0040] The register atomic lock is realized by an atomic lock register of 4N bits; N is the number of processor cores.

[0041] The low 2N bits of the atomic lock register are a COREn_ID area, which stores the identification number COREn_ID of the processor core currently applying for the atomic lock of the register, wherein the low N bits in the COREn_ID area represent the value of COREn_ID, and the high N bits COREn_ID_WEN are write enables of the corresponding bits of the low N bits.

[0042] The high 2N bits of the atomic lock register are a LOCKn_ID area, which stores the identification number LOCKn_ID of the processor core currently trying to acquire the atomic lock of the register, wherein the low N bits in the LOCKn_ID area represent the value of LOCKn_ID, and the high N bits LOCKn_ID_WEN are write enables of the corresponding bits of the low N bits.

[0043] Preferably, the system further comprises an atomic lock history register for storing the identification number of the processor core that acquired the atomic lock of the register last time, for priority judgment of the processor core in the process of requesting the atomic lock of the register; the priority judgment mode of each processor core for requesting the atomic lock of the register is a polling mode, in which priority is given to the next processor core adjacent to the processor core that acquired the atomic lock last time in one priority judgment, and if the processor core to which the priority is given is idle, the priority is extended to the next adjacent processor core.

[0044] Preferably, the system further comprises a global variable lock, and the processor core performs locking and unlocking of the atomic lock of the register before and after performing an access operation on the global variable lock to protect the access operation.

[0045] The present application has the following beneficial effects compared with the prior art:

[0046] (1) The present application proposes a multi-core processor shared data access design method based on a high-security and high-reliability spin lock, which can save the atomic lock data in the chip internal anti-radiation hardened register, improves the protection capability of the atomic lock data in the cosmic radiation environment, and reduces the dependence of the atomic operation for accessing shared data in multi-core task scheduling on the software algorithm, thereby reducing the thread execution errors caused by malicious attacks on the atomic operation software algorithm, and is a high-security and high-reliability multi-core scheduling atomic lock implementation method.

[0047] (2) The present application designs a specific locking and unlocking mode through the hardware implementation characteristics of the atomic lock register, reduces the dependence of the atomic operation for accessing shared data in multi-core task scheduling on the software algorithm, thereby reducing the thread execution errors caused by malicious attacks on the atomic operation software algorithm, and is a high-security multi-core scheduling atomic lock implementation method.

[0048] (3) The application sets a write enable area of processor core identification number in the atomic lock register, and the hardware design of the enable bit setting ensures that each processor core can only modify the identification number corresponding to the processor core when performing the write operation on the atomic lock register, and will not change the state written by other processor cores, which ensures the atomicity of the processor core atomic lock request acquisition operation on the register;

[0049] (4) The application can obtain the processor core currently applying for the atomic lock of the register and the processor core last acquiring the atomic lock of the register by setting the atomic lock register and the atomic lock history register, thereby improving the transparency of the multi-core processor system shared data access state to the user;

[0050] (5) The register atomic lock proposed in the application is combined with the global variable lock to realize the unlimited atomic lock, which can meet the quantity demand of the multi-core processor operating system on the atomic lock and improve the flexibility of the multi-core processor in the shared data access mode;

[0051] (6) The multi-core processor shared data access design method proposed in the application sets the atomic lock nesting mark, which can meet the application scenario of the atomic lock nesting caused by the interruption and improve the adaptability of the multi-core processor thread scheduling mode to the operating system. BRIEF DESCRIPTION OF DRAWINGS

[0052] Figure 1 is the register atomic lock acquisition flowchart in the multi-core processor shared data access method of the application;

[0053] Figure 2 is the atomic lock register structure schematic diagram in the multi-core processor shared data access method of the application;

[0054] Figure 3 is the multi-processor core request register atomic lock schematic diagram in the multi-core processor shared data access method of the application;

[0055] Figure 4 is the unlimited atomic lock design flowchart in the multi-core processor shared data access method of the application. DETAILED DESCRIPTION

[0056] The application will be further described in detail below in combination with the drawings:

[0057] In a multi-core processor system, in order to realize correct scheduling between threads in different processor cores, an atomic lock protection mode is required to access shared data. When a processor core applies for an atomic lock, it needs to first query whether the atomic lock is being held by other processor cores. If the atomic lock is in a released state, the processor core successfully acquires the atomic lock and releases the held atomic lock after executing access to the protected shared resource. If the atomic lock is being held by other processor cores, the processor core enters a loop state and continuously queries and attempts to acquire the atomic lock until the atomic lock is successfully acquired.

[0058] The present application relates to an atomic lock implementation method based on an anti-radiation hardened register, which can effectively ensure safe access of shared data by different threads of a multi-core processor. The method designs a 4N-bit atomic lock register, which can provide a register atomic lock for thread scheduling of the multi-core processor. At any runtime of the system, the same register atomic lock can be held by at most one processor core.

[0059] The atomic lock register of the design method is used to save atomic lock data, including an identification number COREn_ID of a processor core that is applying for the register atomic lock and an identification number LOCKn_ID of a processor core that currently acquires the register atomic lock. Meanwhile, the design method also sets an atomic lock history register, which saves an identification number of a processor core that last acquired the register atomic lock, and is used to determine the priority of the request for the register atomic lock. The priority determination mode of the request for the register atomic lock by each processor core is a polling mode, which ensures that each processor core has the same opportunity to acquire the register atomic lock. In the priority determination of the request for the register atomic lock, the next processor core adjacent to the processor core that last acquired the atomic lock is preferentially authorized. If the processor core that is preferentially authorized is idle, the priority is extended to the next adjacent processor core.

[0060] Embodiment 1

[0061] Reference Figure 1 , Figure 1 The figure is a flowchart of the process of acquiring the register atomic lock in the embodiment of the present application. The steps of acquiring the register atomic lock include:

[0062] S101, the processor core first reads the identification number LOCKn_ID of the processor core that currently holds the register atomic lock in the atomic lock register.

[0063] S102, judge whether the register atomic lock is in the release state, if the LOCKn_ID in the atomic lock register is all 0, it indicates that the register atomic lock is in the release state, continue to execute the request operation of obtaining the register atomic lock, if the LOCKn_ID is not all 0, it indicates that the register atomic lock is not in the release state, the processor core ends the request operation.

[0064] S103, the processor core writes the identification number core_ID of the processor core into the COREn_ID area in the atomic lock register, indicating that the processor core is requesting the register atomic lock.

[0065] S104, the processor core reads out the identification number of the processor core which obtains the register atomic lock last time from the atomic lock history register, reads out the identification number of each processor core which is requesting the register atomic lock from the COREn_ID area in the atomic lock register, to judge the priority of the request of obtaining the register atomic lock.

[0066] S105, the processor core judges the priority according to the read value, if the result of the priority judgment of the processor core is that the processor core has the priority of obtaining the register atomic lock, continue to execute the subsequent operation of obtaining the register atomic lock, if the result of the priority judgment is that the current other processor core has the priority of obtaining the register atomic lock, the processor core fails to request the register atomic lock, execute S106.

[0067] S106, clear the identification number core_ID of the processor core in the COREn_ID area, and end the request operation.

[0068] S107, the result of the priority judgment of the processor core is that the processor core has the priority of obtaining the register atomic lock, write the identification number core_ID of the processor core into the LOCKn_ID in the atomic lock register.

[0069] S108, the processor core reads out the value of LOCKn_ID from the LOCKn_ID area in the atomic lock register, judges whether the LOCKn_ID area only has the identification number of the processor core, if yes, it indicates that the processor core successfully obtains the register atomic lock, execute S110, if the LOCKn_ID area has multiple identification numbers of processor cores, it represents that multiple processor cores have write operation on the LOCKn_ID area, the processor core fails to request the register atomic lock, execute S109.

[0070] S109, clear the identification number core_ID of the processor core in the LOCKn_ID area and the COREn_ID area, and end the request operation.

[0071] S110, successfully acquiring the register atomic lock, updating the atomic lock history register, and writing the identification number core_ID of the current processor core into the atomic lock history register.

[0072] Referring to Figure 2 , Figure 2 is a structural diagram of an atomic lock register. Each atomic lock register can be divided into a high sixteen-bit part and a low sixteen-bit part, wherein the low sixteen-bit part is a COREn_ID area that stores the identification number of the processor core that is currently applying for the atomic lock of the register, and the high sixteen-bit part is a LOCKn_ID area that stores the identification number of the processor core that is currently acquiring the atomic lock of the register.

[0073] The LOCKn_ID area and the COREn_ID area each include a data area and a write enable area of the identification number of the processor core of the respective area, the data area has a length of eight bits, so that the register atomic lock is applicable to up to eight processor cores for access scheduling of a shared address, and meanwhile, through the hardware design of the write enable area, it can be ensured that each processor core can only modify the identification number corresponding to the processor core when performing a write operation on the atomic lock register, and cannot modify the state written by other processor cores, which ensures the atomicity of the request acquisition operation of the processor core on the register atomic lock.

[0074] The high eight bits LOCKn_ID_WEN of the LOCKn_ID area are the enable bits of the LOCKn_ID, which are respectively the write enables of the low eight bits LOCKn_ID of the area, the enable bit is high when it is valid, and the enable bit is low when it is invalid, and the hardware automatically clears the LOCKn_ID_WEN after writing. The low eight bits of the LOCKn_ID area correspond to the identification numbers of eight processor cores, and only when the corresponding enable bit is valid can the identification number be written, and when the corresponding enable bit is invalid, the LOCKn_ID can only be read. The value of the LOCKn_ID is all 0, which represents that the register atomic lock is in a released state, and the value of the LOCKn_ID is not 0, which represents the identification number of the processor core that is currently acquiring the atomic lock of the register.

[0075] The high eight bits COREn_ID_WEN of the COREn_ID area are the enable bits of the COREn_ID, which are respectively the write enables of the low eight bits COREn_ID of the area, the enable bit is high when it is valid, and the enable bit is low when it is invalid, and the hardware automatically clears the COREn_ID_WEN after writing. The low eight bits of the COREn_ID area correspond to the identification numbers of eight processor cores, and only when the corresponding enable bit is valid can the identification number be written, and when the corresponding enable bit is invalid, the COREn_ID can only be read, and the COREn_ID stores the identification number of the processor core that is currently applying for the atomic lock of the register.

[0076] The processor core clears the identification number of the processor core in the LOCKn_ID area and the COREn_ID area of the atomic lock register when performing the unlocking operation, and releases the atomic lock of the register.

[0077] Referring to Figure 3 , Figure 3 Figure 1 is a schematic diagram of a plurality of processor cores requesting the same register atomic lock in an embodiment of the present application. It is assumed that processor cores 0, 1 and 3 are requesting the same register atomic lock, the initial value of the atomic lock register LOCKREG is 0, and the initial value of the atomic lock history register H_LOCK is 7. In step one, the values obtained by the three processor cores accessing the atomic lock register are all 0, and the judgment result is that the lock is in the released state, and the request operation is continued.

[0078] In step two, the three processor cores write their own processor core identification numbers core0_ID, core1_ID and core3_ID into the COREn_ID area of the atomic lock register.

[0079] In step three, it is learned from the atomic lock history register that the last processor core holding the lock is core 7, and the priority judgment shows that the processor core 0 has the priority to acquire the register atomic lock. Therefore, the processor core 0 writes its own identification number into the LOCKn_ID area of the atomic lock register, and the processor cores 1 and 3 clear the identification number of the processor core in the COREn_ID area of the atomic lock register, ending the request operation and starting a new request.

[0080] In step four, the processor core 0 reads the atomic lock register, confirms that the processor core identification number in the LOCKn_ID area is unique, successfully acquires the register atomic lock, and ends the request operation after writing its own identification number into the atomic lock history register.

[0081] In step five, the processor core 0 clears the identification number of the processor core in the COREn_ID area and the LOCKn_ID area of the atomic lock register after executing the protected thread, and releases the register atomic lock.

[0082] In step six, the processor cores 1 and 3 query that the register atomic lock is released, and write their own processor core identification numbers into the COREn_ID area of the atomic lock register.

[0083] In step seven, it is learned from the atomic lock history register that the last processor core holding the lock is the processor core 0, and the priority judgment shows that the processor core 1 has the priority, successfully acquires the register atomic lock, updates the atomic lock history register, and the processor core 3 fails in the request operation, ending the request operation and starting a new request.

[0084] Step eight, after the protected thread is executed, the processor core 1 clears the identification number of the processor core in the atomic lock register COREn_ID area and the LOCKn_ID area, and releases the register atomic lock.

[0085] Step nine, the processor core 3 queries that the register atomic lock is released, writes the identification number of the processor core to the COREn_ID area of the atomic lock register, and since the last processor core 1 that takes the lock has the priority, the priority should be granted to the processor core 2 first, but the processor core 2 does not initiate the lock request, so the priority is postponed to the processor core 3, and the processor core 3 successfully acquires the register atomic lock.

[0086] Embodiment 2

[0087] For the application of the multi-core processor based on the operating system, the method of the application can be combined with the global variable to realize the unlimited atomic lock to meet the scheduling requirements of different application scenarios in the operating system. In the multi-core operating system, the global variable is used to save the lock used for the inter-thread scheduling, and the global variable lock saved in different addresses can be set according to the application requirements, so as to realize the atomic lock quantity meeting the application requirements.

[0088] Before and after the processor core performs the access operation on the global variable lock, the locking and unlocking of the register atomic lock are performed to protect the access operation, when the register atomic lock is requested, if the processor core judges that the value of LOCKn_ID in the atomic lock register is the identification number of the other processor core, it represents that the register atomic lock is being held by the other processor core, the processor core fails to request the register atomic lock, and if it is judged that the value of LOCKn_ID in the atomic lock register is the identification number of the processor core, it will not be judged as a request failure, and the request operation will be continued after the atomic lock nesting flag is set, so as to ensure that the deadlock phenomenon caused by the processor core holding the register atomic lock being interrupted and then requesting the same register atomic lock again will not occur.

[0089] Reference Figure 4 , Figure 4 The step diagram for the processor core to acquire the global variable lock includes the following steps:

[0090] S401, the processor core first performs the register atomic lock locking operation, and reads the value of LOCKn_ID in the atomic lock register.

[0091] S402, it is judged whether the value of LOCKn_ID is the identification number of the other processor core, if yes, the request for the register atomic lock fails, the request operation is ended and a new request is started, and if not, S403 is executed.

[0092] S403, judging whether LOCKn_ID is all 0 or the processor core identification number, if the value of LOCKn_ID is the processor core identification number, executing S404, if the value of LOCKn_ID is all 0, executing S405.

[0093] S404, the processor core judges that the value of LOCKn_ID is the processor core identification number, and carries out the atomic lock nesting mark.

[0094] S405-S406, the processor core continues to execute the request register atomic lock operation, if the request fails, ending the request operation and starting a new request, if the request succeeds, executing S407.

[0095] S407, the processor core successfully acquires the register atomic lock, and starts to carry out the access operation to the global variable lock, and reads the global variable to obtain the current value of the global variable lock.

[0096] S408, the processor core compares the current global variable lock value with the expected value, judges whether the lock is in the release state, if the global variable lock value is not the same as the expected value, it represents that the global variable lock is not in the release state, the request fails, executing S409, otherwise, it represents that the global variable lock is in the release state, executing S410.

[0097] S409, the processor core requests the global variable lock unsuccessfully, releases the register atomic lock, and starts a new request.

[0098] S410, the processor core judges that the global variable lock is in the release state, successfully acquires the lock, and writes a new value into the global variable to indicate that the lock is occupied.

[0099] S411, after the processor core successfully requests the global variable lock, judging whether there is an atomic lock nesting mark, if yes, the request ends, the register atomic lock is not released, and the execution continues to execute the user program protected by the atomic lock, if not, executing S412.

[0100] S412, the processor core judges that there is no atomic lock nesting mark, releases the register atomic lock, the request ends, and the execution continues to execute the user program protected by the atomic lock.

[0101] After executing the protected task, the processor core releases the global variable lock by writing a specific value representing that the lock is idle into the global variable lock.

[0102] The part of the application not described in detail belongs to the technology known in the art.

Claims

1. A design method for shared data access in a multi-core processor based on a spin lock, characterized by: By providing register atomic locks to multi-core processors, thread access to shared data is scheduled; the register atomic lock is implemented by a 4N-bit atomic lock register, where N is the number of processor cores; The atomic lock register is divided into two parts: the upper 2N bits and the lower 2N bits; Set the lower 2N bits of the atomic lock register to the COREn_ID area to save the identification number COREn_ID of the processor core that is applying for the atomic lock of the register. The lower N bits in the COREn_ID area represent the value of COREn_ID, and the upper N bits COREn_ID_WEN are the write enable of the corresponding bits of the lower N bits. Set the upper 2N bits of the atomic lock register to the LOCKn_ID area to save the identification number LOCKn_ID of the processor core currently trying to obtain the atomic lock of the register. The lower N bits in the LOCKn_ID area represent the value of LOCKn_ID, and the upper N bits LOCKn_ID_WEN are the write enable of the corresponding bits of the lower N bits. Each processor core has the same opportunity to acquire the register atomic lock; At the same time, the same register atomic lock can be acquired by at most one processor core; The processor core acquires the register atomic lock including: The processor core requests the register atomic lock, reads the LOCKn_ID value in the atomic lock register corresponding to the register atomic lock, and determines whether the atomic lock register is in the released state. If so, writes the identification number of the processor core to the COREn_ID area in the atomic lock register, otherwise exits the request; Read the identification number of the processor core currently requesting the atomic lock from the COREn_ID area in the atomic lock register, and perform priority judgment based on the read value. If the processor core has the highest priority, write the identification number of the processor core to the LOCKn_ID area of ​​the atomic lock register; otherwise, clear the identification number of the processor core in the COREn_ID area. Determine whether the processor core in the LOCKn_ID of the atomic lock register is unique. If so, the processor core successfully obtains the register atomic lock. Otherwise, clear the identification number of the processor core in the LOCKn_ID area and COREn_ID area in the atomic lock register and release the register atomic lock.

2. The method according to claim 1, wherein: The number of bits of the atomic lock register is determined by the number of processor cores. Each atomic lock register implements a register atomic lock. The register atomic lock implemented by a single 4N-bit atomic lock register is suitable for access scheduling of shared addresses by up to N processor cores.

3. The method according to claim 1, wherein: The LOCKn_ID area of ​​the atomic lock register that stores the identification number of the processor core currently attempting to acquire the atomic lock of the register includes: The lower N bits of LOCKn_ID in this area can be written only when the corresponding enable bit is valid. When the corresponding enable bit is invalid, LOCKn_ID can only be read. When the value of LOCKn_ID is 0, it means that the register atomic lock is in the released state. When the value of LOCKn_ID is not 0, it represents the identification number of the processor core currently trying to acquire the register atomic lock. The high N bits LOCKn_ID_WEN in this area are the enable bits of LOCKn_ID, which correspond to the write enable of the low N bits. The enable bit is valid when it is high and invalid when it is low. LOCKn_ID_WEN will be automatically cleared after writing.

4. The method according to claim 1, wherein: The atomic lock register stores the identification number COREn_ID area of ​​the processor core that is applying for the register atomic lock, including: The lower N bits of the COREn_ID in this area can be written only when the corresponding enable bit is valid. When the corresponding enable bit is invalid, the COREn_ID can only be read. The COREn_ID stores the identification number of each processor core that is currently applying for the atomic lock of this register. The high N bits COREn_ID_WEN in this area are the enable bits of COREn_ID, which correspond to the write enable of the low N bits. The enable bit is valid when it is high and invalid when it is low. COREn_ID_WEN will be automatically cleared after writing.

5. The method according to claim 1, wherein: The priority determination method for each processor core requesting the register atomic lock is polling. In a priority determination, priority is granted to the next processor core adjacent to the processor core that last obtained the atomic lock. If the processor core to which priority is granted is vacant, the priority is deferred to the next adjacent processor core.

6. The method according to claim 1 or 5, characterized in that: The identification number of the processing core that last acquired the register atomic lock is saved by setting the atomic lock history register for priority determination.

7. The method according to claim 1, wherein: For operating systems of multi-core processors, unlimited atomic locks are achieved by combining global variable locks and register atomic locks to meet the scheduling requirements of different application scenarios in the operating system.

8. The method according to claim 7, wherein: The operating system of a multi-core processor uses a global variable lock to save the lock used for scheduling between threads. The global variable locks stored at different addresses are set according to the number of applications required, so as to achieve the number of atomic locks that meet the application requirements.

9. The method according to claim 7, wherein: Before and after the processor core performs an access operation on the global variable lock, it locks and unlocks the register atomic lock to protect the access operation. The processor core's access operation on the global variable lock includes: Read the global variable to get the current value of the global variable lock; Compare the current value of the global variable lock with the expected value to determine whether the lock is in the released state; If the global variable lock is not in the released state, the request fails; If the global variable lock is in a released state, the processor core obtains the lock and writes a new value to the global variable to indicate that the lock is occupied.

10. The method according to claim 9, characterized in that: The locking operation of the register atomic lock includes: requesting the register atomic lock. If it is determined that the value of LOCKn_ID in the atomic lock register is the identification number of the processor core, the request will not be determined to have failed, and the request operation will continue to be executed after the atomic lock nesting mark is performed, ensuring that there will be no deadlock caused by the processor core holding the register atomic lock being interrupted and requesting the same register atomic lock again.

11. The method according to claim 10, characterized in that: The method further comprises: After the processor core completes the access operation of the global variable lock under the protection of the register atomic lock, the unlocking operation of the register atomic lock includes: Determine whether there is an atomic lock nesting mark and whether the request for the global variable lock is successful; If the request for the global variable lock is unsuccessful, the register atomic lock is released, and the register atomic lock and global variable lock are requested again; If the global variable lock request is successful and there is no atomic lock nesting flag, the register atomic lock is released; If the request for the global variable lock is successful and there is an atomic lock nesting mark, the register atomic lock will not be released until the program interrupted by the nesting performs the register atomic lock unlocking operation.

12. The method according to claim 9, wherein: The global variable lock is released by writing a specific value representing that the lock is free into the corresponding global variable.

13. A multi-core processor shared data access system based on spin lock, characterized by: It includes a register atomic lock, which is used to schedule access to shared data between different threads of a multi-core processor; each processor core has the same opportunity to obtain the register atomic lock; At the same time, the same register atomic lock can be acquired by at most one processor core; The register atomic lock is implemented by a 4N-bit atomic lock register; N is the number of processor cores; The lower 2N bits of the atomic lock register are the COREn_ID area, which stores the identification number COREn_ID of the processor core that is applying for the atomic lock of the register. The lower N bits in the COREn_ID area represent the value of COREn_ID, and the upper N bits COREn_ID_WEN are the write enable of the corresponding bits of the lower N bits. The upper 2N bits of the atomic lock register are the LOCKn_ID area, which stores the identification number LOCKn_ID of the processor core currently trying to obtain the atomic lock of the register. The lower N bits in the LOCKn_ID area represent the value of LOCKn_ID, and the upper N bits LOCKn_ID_WEN are the write enable of the corresponding bits of the lower N bits. The processor core acquires the register atomic lock including: The processor core requests the register atomic lock, reads the LOCKn_ID value in the atomic lock register corresponding to the register atomic lock, and determines whether the atomic lock register is in the released state. If so, writes the identification number of the processor core to the COREn_ID area in the atomic lock register, otherwise exits the request; Read the identification number of the processor core currently requesting the atomic lock from the COREn_ID area in the atomic lock register, and perform priority judgment based on the read value. If the processor core has the highest priority, write the identification number of the processor core to the LOCKn_ID area of ​​the atomic lock register; otherwise, clear the identification number of the processor core in the COREn_ID area. Determine whether the processor core in the LOCKn_ID of the atomic lock register is unique. If so, the processor core successfully obtains the register atomic lock. Otherwise, clear the identification number of the processor core in the LOCKn_ID area and COREn_ID area in the atomic lock register and release the register atomic lock.

14. The system according to claim 13, wherein: It also includes an atomic lock history register, which is used to save the identification number of the processing core that last obtained the register atomic lock, and is used to determine the priority of the processor core during the register atomic lock request process; the priority determination method for each processor core requesting the register atomic lock is a polling method. In a priority determination, priority is granted to the next processor core adjacent to the processor core that last obtained the atomic lock. If the processor core to which priority is granted is vacant, the priority is deferred to the next adjacent processor core.

15. The system according to claim 13, wherein: It also includes a global variable lock. Before and after the processor core performs an access operation on the global variable lock, it locks and unlocks the register atomic lock to protect the access operation.

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