Low power branch target buffer with two-level prediction mechanism and design method

Abstract

The application discloses a low-power branch target buffer with a two-stage prediction mechanism and relates to the technical field of processors. The low-power branch target buffer comprises a serially connected M-BTB module, a V-BTB module and a decision module, the M-BTB module comprises a serially connected M-BTB prediction mechanism and a M-BTB structure, an input current instruction address is predicted by the M-BTB prediction mechanism to store potential Banks of a target instruction address in the M-BTB structure, the V-BTB module comprises a V-BTB prediction mechanism and a V-BTB structure, an input current instruction address is predicted by the V-BTB prediction mechanism to store potential Ways of a target instruction address in the V-BTB structure, and the decision module checks the target instruction addresses output by the M-BTB module and the V-BTB module. The application reduces the query power consumption of a current instruction address accessing a BTB structure by predicting Banks and Ways through a two-stage prediction mechanism.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a low-power branch target buffer with a two-level prediction mechanism and its design method. Background Technology

[0002] Processor design is an engineering task that involves designing the key components of a computer. The branch prediction module is one of the critical modules in the processor core. The performance of branch prediction determines whether the processor can continuously fetch instruction addresses for instruction fetching.

[0003] The Branch Target Buffer (BTB) is a core component of the branch prediction module and is crucial for processor branch prediction performance. The BTB contains the current instruction address, the target instruction address, and the instruction type. Accessing the BTB structure at the current instruction address, if the instruction at that address is triggered, it is considered a branch instruction, and the stored target instruction address is output. Otherwise, it is considered that the current instruction address has not been triggered.

[0004] As program complexity increases, processor performance requirements also rise. To meet the execution demands of more complex programs, the capacity of the BTB (Browser Targeting) structure is gradually expanding, leading to increased power consumption for BTB module lookups. Previous statistics indicate that BTB power consumption accounts for 7.4% of total processor power consumption. Summary of the Invention

[0005] The purpose of this invention is to propose a low-power branch target buffer and its design method with a two-level prediction mechanism. By predicting the potential storage location of the target instruction address in the M-BTB structure and V-BTB through the two-level prediction mechanism, the query power consumption of the current instruction address accessing the BTB structure is reduced, which solves the problem that the capacity of the BTB structure is gradually increasing, leading to an increase in the query power consumption of the BTB module.

[0006] The technical solution adopted in this invention is as follows:

[0007] This invention is a low-power branch target buffer with a two-stage prediction mechanism, comprising a serially connected M-BTB module, a V-BTB module, and a decision module.

[0008] The M-BTB module includes a serially connected M-BTB prediction mechanism and an M-BTB structure. The M-BTB structure includes four banks. The input current instruction address is predicted by the M-BTB prediction mechanism to determine the potential bank where the target instruction address is stored in the M-BTB structure. The current instruction address accesses the bank.

[0009] The V-BTB module includes a V-BTB prediction mechanism and a V-BTB structure. The V-BTB structure includes four Ways. The input current instruction address is used by the V-BTB prediction mechanism to predict the potential Way stored in the V-BTB structure for the target instruction address. The current instruction address accesses the Way.

[0010] The decision module verifies the target instruction address output by the M-BTB module and the target instruction address of the V-BTB module.

[0011] Furthermore, the M-BTB prediction mechanism includes a two-to-four decoder. The two-to-four decoder decodes two bits of the current instruction address and the target instruction address in the M-BTB structure to obtain the corresponding Bank and stores them in the corresponding Bank. The two bits of the input current instruction address are decoded by the two-to-four decoder to obtain the target instruction address, which is stored in the potential Bank. The input current instruction address accesses the Bank.

[0012] Furthermore, the M-BTB structure is a fully associative structure with 40 entries, divided into 4 banks, each containing 10 entries.

[0013] Furthermore, the V-BTB prediction mechanism includes a Partial Tag table, which contains 2K entries. Each entry is 32 bits long and is divided into A, B, C, and D, which correspond to the current instruction addresses of the four Ways, respectively. Eight bits of the current instruction addresses of the four Ways are selected and mapped to A, B, C, and D in the Partial Tag.

[0014] The Partial Tag table corresponds to the four Ways in V-BTB. The 8 bits of the current instruction address are matched with the Partial Tag table, and the matched Way is selected for access.

[0015] V-BTB contains 8K entries, divided into 4 Ways, each containing 2K entries.

[0016] The design method of a low-power branch target buffer with a two-level prediction mechanism includes the following steps:

[0017] Step S1: Input the current instruction address, access the M-BTB module, and access the M-BTB structure according to the prediction result of the M-BTB prediction mechanism. If the input current instruction address hits the M-BTB structure, proceed to step S2; otherwise, proceed to step S3.

[0018] Step S2: Determine that the current input instruction is a branch instruction. The M-BTB structure outputs the target instruction address PC1 and compares it with the target instruction address PC3 output by the decision module. If PC3 is the same as PC1, the prediction result of the M-BTB module is correct and no redirection is required. Otherwise, if PC2 is different from PC1, the prediction result of the M-BTB module is incorrect and redirection is required.

[0019] Step S3: The input current instruction address accesses the V-BTB module. Based on the prediction result of the V-BTB prediction mechanism, the V-BTB structure is accessed. If the input current instruction address hits the V-BTB structure, proceed to step S4. If the V-BTB structure is not hit, proceed to step S5.

[0020] Step S4: Output the target instruction address PC2 and compare it with the target instruction address PC3 output by the decision module. If PC2 and PC3 are the same, the prediction result of the V-BTB module is correct and no redirection is required. Otherwise, if PC2 and PC3 are different, the prediction result of the V-BTB module is incorrect and redirection is required.

[0021] Step S5: Determine that the current instruction is a sequential execution instruction and will not be verified by the decision module. The prediction result of the M-BTB module is incorrect, so no redirection will be performed.

[0022] Furthermore, the redirection specifically involves: assigning the target instruction address PC3 to the PC register, sending the current instruction address and the target instruction address PC3 verified by the decision module back to the M-BTB module, and updating the M-BTB module.

[0023] Furthermore, while performing step S3 and accessing the V-BTB module, the current instruction address is sequentially incremented to the target instruction address PC1*, and returned to the PC register to continue fetching instructions.

[0024] Furthermore, step S1 specifically includes:

[0025] The two bits of the current instruction address are input into the M-BTB prediction mechanism. The M-BTB prediction mechanism predicts the potential Bank for storing the target instruction address in the M-BTB structure. The current instruction address is used to select the potential Bank for storing the target instruction address in the M-BTB structure and access it. If the input current instruction address successfully matches the entry in the Bank, then the Bank is hit, that is, the current instruction address hits the M-BTB structure.

[0026] Furthermore, the M-BTB prediction mechanism is a 2-to-4 decoder that decodes a 2-bit address to obtain a 4-bit index, accesses 4 banks in the M-BTB structure, and each bank corresponds to 0001, 0010, 0100, and 1000. The current instruction address and the target instruction address in the M-BTB structure are decoded by the 2-to-4 decoder, and the corresponding bank obtained by the decoder is selected for storage.

[0027] Furthermore, step S4 specifically includes:

[0028] The input current instruction address is fed into the V-BTB prediction mechanism, which is a Partial Tag table. The Partial Tag table corresponds to the four Ways in the V-BTB in sequence. The 8 bits of the input current instruction address are matched with the Partial Tag table, and the matched Way is accessed. If the input current instruction address matches the current instruction address in the Way table entry, it means that the Way is hit, that is, the current instruction address hits the V-BTB structure.

[0029] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0030] This invention is a low-power branch target buffer with a two-level prediction mechanism. This invention serializes the two-level structure of the M-BTB module and the V-BTB module, adding a two-level prediction mechanism. The M-BTB structure contains 40 entries, has a smaller area, and has a faster prediction speed. The V-BTB structure contains 8K entries, providing more accurate prediction results.

[0031] This invention is a design method for a low-power branch target buffer with a two-level prediction mechanism. The input current instruction address predicts the potential way of the target instruction address through the M-BTB prediction mechanism. When the Bank in the M-BTB module is triggered, the V-BTB module is no longer accessed, effectively reducing the query power consumption of the two-level structure. When the branch instruction in the M-BTB module is triggered, the V-BTB module is accessed again. The V-BTB prediction mechanism matches the 8-bit address to predict the potential way of the target instruction address, resulting in more accurate prediction results. By predicting the Bank and Way through the two-level prediction mechanism, the query power consumption of the current instruction address accessing the BTB structure is reduced. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort, wherein:

[0033] Figure 1 This is a schematic diagram of the BTB structure of the present invention;

[0034] Figure 2 This illustrates the correspondence between the V-BTB prediction mechanism and the V-BTB structure in this invention.

[0035] Figure 3 This is a flowchart of the design method of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention; that is, the described embodiments are merely some embodiments of the invention, and not all embodiments. The components of the embodiments of the invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0037] It should be noted that the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0038] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0039] Example 1

[0040] like Figure 1 As shown, this invention is a low-power branch target buffer with a two-level prediction mechanism, including a serially connected M-BTB module, a V-BTB module, and a decision module.

[0041] The M-BTB module includes a serially connected M-BTB prediction mechanism and an M-BTB structure. The M-BTB structure includes four banks. The input current instruction address is predicted by the M-BTB prediction mechanism to determine the potential bank where the target instruction address is stored in the M-BTB structure. The current instruction address accesses the bank.

[0042] The V-BTB module includes a V-BTB prediction mechanism and a V-BTB structure. The V-BTB structure includes four Ways. The input current instruction address is used by the V-BTB prediction mechanism to predict the potential Way stored in the V-BTB structure for the target instruction address. The current instruction address accesses the Way.

[0043] The decision module verifies the target instruction address output by the M-BTB module and the target instruction address of the V-BTB module.

[0044] Preferably, the M-BTB prediction mechanism includes a two-to-four decoder. The two-to-four decoder decodes two bits of the current instruction address and the target instruction address in the M-BTB structure to obtain the corresponding Bank and stores them in the corresponding Bank. The two bits of the input current instruction address are decoded by the two-to-four decoder to obtain the target instruction address, which is stored in the potential Bank. The input current instruction address accesses the Bank.

[0045] When the current instruction address and the target instruction address are written into the Bank of the M-BTB structure for storage, the two-bit address is decoded by a two-to-four decoder, and then an empty entry in the corresponding Bank is selected for storage.

[0046] Preferably, the M-BTB structure is a fully associative structure with 40 entries, divided into 4 banks, each containing 10 entries.

[0047] Preferably, the V-BTB prediction mechanism includes a Partial Tag table, which contains 2K entries, each 32 bits long, categorized as A, B, C, and D, corresponding to the current instruction addresses of the four ways, respectively. Eight bits are selected and mapped to A, B, C, and D in the Partial Tag, as shown below. Figure 2 As shown;

[0048] The Partial Tag table corresponds to the four Ways in V-BTB. The 8 bits of the current instruction address are matched with the Partial Tag table, and the matched Way is selected for access.

[0049] V-BTB contains 8K entries, divided into 4 Ways, each containing 2K entries.

[0050] The current instruction address and the target instruction address are written into the four Ways of the V-BTB structure. The current instruction address or the target instruction address is divided by the table length 2K to obtain the corresponding table position as the i-th table entry. The Way in the four Ways where the i-th table entry is empty is selected for storage.

[0051] This invention relates to a low-power BTB structure based on a two-level prediction mechanism, which mainly includes an M-BTB module, a V-BTB module, and a decision module.

[0052] The M-BTB module comprises two parts: the M-BTB prediction mechanism and a 4-Bank M-BTB structure. The first-stage predictor predicts the potential Banks in the M-BTB module where the target instruction address is stored. In this embodiment, the M-BTB prediction mechanism includes a 2-to-4 decoder. The Banks in the M-BTB can be 1, 2, 4, or 8, which are 0001, 0010, and 0100 in binary. The appropriate decoder can be selected based on the processor's performance requirements. The two bits of the input current instruction address are decoded by the 2-to-4 decoder and indexed to obtain the potential Banks in the M-BTB module where the target instruction address is stored. The input current instruction address accesses the potentially predicted Banks. If a match is found, the Bank is hit, the target instruction address is output, and the decision module determines whether to perform redirection. If the Bank is not hit, it means the instruction is not in the M-BTB structure and is considered to be executed sequentially. The current instruction is incremented sequentially and passed to the PC register, while the current instruction address is passed to the V-BTB module.

[0053] The V-BTB module consists of two parts: the V-BTB prediction mechanism and the 4-Way V-BTB structure. The V-BTB prediction mechanism includes a Partial Tag table, which corresponds sequentially to the 4-Way structures in V-BTB, such as... Figure 2 This shows the correspondence between the V-BTB prediction mechanism and the V-BTB structure. For the V-BTB structure, taking the i-th entry as an example, the current instruction address in each entry is i. c For 4Way, there are a total of 4 i entries, namely Through multiple experiments, we found that for the i-th entry in different ways, the differences between them are significant, and entries that are not the target instruction address can be excluded without matching 32 bits. For a 4-way V-BTB structure, accessing the input current instruction address and simultaneously matching 32 bits of the address results in high power consumption. Through multiple sets of different experiments, we proved that for 32-bit instruction addresses, choosing 8 bits as the index is sufficient to distinguish different addresses.

[0054] Therefore, this invention uses the current instruction address of the i-th entry in the four Ways. We select 8 bits and map them to the Partial Tag. When accessing the V-BTB structure with the input current instruction address, we first match it using the Partial TAG, select the Way that matches the input current instruction address, and access that Way. If the input current instruction address matches the current instruction address in the Way table entry, then the Way table entry is hit, the target instruction address is output, and then the decision module decides whether to perform redirection. If no Way is hit, the decision module does not participate, and redirection is not required.

[0055] The M-BTB structure of this invention contains 40 entries, has a smaller area, and a faster prediction speed. The V-BTB structure contains 8K entries, providing more accurate prediction results. By serializing the two-level structures of the M-BTB module and the V-BTB module, a two-level prediction mechanism is added. By predicting the Bank and Way, when a branch instruction in the M-BTB module is triggered, the V-BTB module is no longer accessed, effectively reducing the query power consumption of the two-level structure.

[0056] Example 2

[0057] like Figure 3 As shown, this invention is a design method for a low-power branch target buffer with a two-level prediction mechanism, comprising the following steps:

[0058] Step S1: Input the current instruction address, access the M-BTB module, and access the M-BTB structure according to the prediction result of the M-BTB prediction mechanism. If the input current instruction address hits the M-BTB structure, proceed to step S2; otherwise, proceed to step S3.

[0059] Step S2: Determine that the current input instruction is a branch instruction. The M-BTB structure outputs the target instruction address PC1 and compares it with the target instruction address PC3 output by the decision module. If PC3 is the same as PC1, the prediction result of the M-BTB module is correct and no redirection is required. Otherwise, if PC2 is different from PC1, the prediction result of the M-BTB module is incorrect and redirection is required.

[0060] Step S3: The input current instruction address accesses the V-BTB module. Based on the prediction result of the V-BTB prediction mechanism, the V-BTB structure is accessed. If the input current instruction address hits the V-BTB structure, proceed to step S4. If the V-BTB structure is not hit, proceed to step S5.

[0061] Step S4: Output the target instruction address PC2 and compare it with the target instruction address PC3 output by the decision module. If PC2 and PC3 are the same, the prediction result of the V-BTB module is correct and no redirection is required. Otherwise, if PC2 and PC3 are different, the prediction result of the V-BTB module is incorrect and redirection is required.

[0062] Step S5: Determine that the current instruction is a sequential execution instruction and will not be verified by the decision module. The prediction result of the M-BTB module is incorrect, so no redirection will be performed.

[0063] Preferably, the redirection specifically involves: assigning the target instruction address PC3 to the PC register, sending the current instruction address and the target instruction address PC3 verified by the decision module back to the M-BTB module, and updating the M-BTB module.

[0064] Preferably, while performing step S3 and accessing the V-BTB module, the current instruction address is sequentially incremented to the target instruction address PC1*, and returned to the PC register to continue fetching instructions.

[0065] Preferably, step S1 specifically comprises:

[0066] The two bits of the current instruction address are input into the M-BTB prediction mechanism. The M-BTB prediction mechanism predicts the potential Bank for storing the target instruction address in the M-BTB structure. The current instruction address is used to select the potential Bank for storing the target instruction address in the M-BTB structure and access it. If the input current instruction address successfully matches the entry in the Bank, then the Bank is hit, that is, the current instruction address hits the M-BTB structure.

[0067] Preferably, the M-BTB prediction mechanism is a 2-to-4 decoder, which decodes a 2-bit address to obtain a 4-bit index, accesses four banks in the M-BTB structure, and each bank corresponds to 0001, 0010, 0100, and 1000. The current instruction address and the target instruction address in the M-BTB structure are decoded by the 2-to-4 decoder, and the corresponding bank obtained from the decoding is selected for storage. When selecting a bank for storage for the current instruction address and the target instruction address, after decoding the 2-bit address by the 2-to-4 decoder, an empty entry in the corresponding bank is selected for storage.

[0068] Preferably, step S4 specifically comprises:

[0069] The input current instruction address is fed into the V-BTB prediction mechanism, which is a Partial Tag table. The Partial Tag table corresponds to the four Ways in the V-BTB in sequence. The 8 bits of the input current instruction address are matched with the Partial Tag table, and the matched Way is accessed. If the input current instruction address matches the current instruction address in the Way table entry, it means that the Way is hit, that is, the current instruction address hits the V-BTB structure.

[0070] like Figure 3 As shown, this invention divides the above design method into 5 cases, specifically:

[0071] Scenario 1: First, obtain the current instruction address, access the M-BTB module, decode the 2-bit address of the current instruction to obtain a 4-bit index, and access the corresponding Bank in the M-BTB structure. If the Bank in the M-BTB structure is hit, it indicates that the instruction is a branch instruction, and the target instruction address PC1 is output. Because the M-BTB structure is hit, the V-BTB prediction mechanism and V-BTB structure are not accessed again. The target instruction address PC1 output by the M-BTB module is directly compared with the target instruction address PC3 output by the decision module for a second decision. If the target instruction address PC3 output by the decision module matches PC1 (PC1 == PC3), it indicates that the M-BTB module prediction is correct, and redirection is not required.

[0072] Case 2: Unlike Case 1, if PC3 is different from PC1, it means that the target instruction address PC3 obtained from the second decision is different from the output of the M-BTB module. In this case, redirection is required. The target instruction address PC3 is given to the PC register, and the current instruction address and target instruction address PC3 verified by the decision module are sent back to the M-BTB module to update the M-BTB module.

[0073] Scenario 3: First, obtain the current instruction address, access the M-BTB module, decode the 2-bit address to obtain a 4-bit index, and access the M-BTB structure. If the M-BTB structure is not found, it is assumed that the instruction corresponding to that instruction address will not jump, and the current instruction address is sequentially incremented to PC1* (PC1* = current instruction address PC + M), and returned to the register to continue fetching instructions. Simultaneously, access the V-BTB module. The input current instruction address first passes through the Partial TAG table to obtain the Way storing the potential target instruction address, and then the input current instruction address accesses that Way to check if a hit occurs (whether the input current instruction address matches the current instruction address in that Way). If a hit occurs in the V-BTB module, the target instruction address PC2 is output, and the target instruction address PC2 is compared with the target instruction address PC3 output according to the decision. If PC2 == PC3, it means that the V-BTB prediction is correct, and execution continues.

[0074] Case 4: For Case 3, if the values ​​of PC2 and PC3 are not equal, it means that the prediction result of the V-BTB module is incorrect. In this case, redirection is required. The target instruction address PC3 is given to the PC register, and the current instruction address and the target instruction address PC3 verified by the decision module are sent back to the M-BTB module to update the M-BTB module.

[0075] Case 5: For Case 3, if the V-BTB module also does not trigger a response, the instruction is considered to be a sequential instruction and will not be verified by the decision module or redirected.

[0076] Based on simulation experiments, Embodiments 1 and 2 of the present invention will be further described as follows:

[0077] 1. Simulation conditions and content:

[0078] The hardware platform used in this simulation experiment is as follows: Intel Core i7-7700 CPU (3.6GHz), 16GB of memory, and Python 3.6 and Vivado 2019.1 as the simulation software platform.

[0079] Simulation 1: Verifying the missing entry rates of the M-BTB and V-BTB modules. Using a two-level BTB structure, 20 different traces with jump conditions were accessed. The missing entry rates are shown in Tables 1 and 2 below:

[0080]

[0081] Simulation 2: Verifying the prediction results of the two-level prediction mechanism. Without the prediction mechanism, the current address needs to access all entries in the M-BTB and all Ways in the V-BTB. By adding a prediction mechanism to predict the Bank and Way, the query result can be obtained by accessing a specific Way based on the prediction result. The prediction results are shown in Tables 3 and 4, and Table 5 shows the prediction success rate using the two-level prediction mechanism.

[0082] 2. Simulation Result Analysis:

[0083] Table 1. Missing Item Rate of M-BTB Module

[0084]

[0085] Table 2, Missing Item Rate of V-BTB Module

[0086]

[0087] To investigate the robustness of our proposed two-level prediction mechanism for a low-power branch target buffer structure, we selected the high-complexity trace for experiments. Table 1 shows that when using 40 entries, the M-BTB entry missing rate reaches 12%. Table 2 shows that the V-BTB, containing 8K entries, has an entry missing rate of less than 1%. This demonstrates that our two-level prediction mechanism for a low-power branch target buffer structure can effectively perform instruction address prediction. The M-BTB module provides faster prediction speed, while the V-BTB module provides more accurate prediction results.

[0088] Table 3. Prediction results of the M-BTB prediction mechanism

[0089]

[0090] Table 4. Prediction results of the V-BTB prediction mechanism

[0091]

[0092] Table 3 shows the prediction results of the M-BTB prediction mechanism. We used 2-bit address decoding to select a Bank for storage and matching. Experimental results show that we hit one of the paths with a 100% probability, indicating that for all instructions, we predict only one Bank for access. Compared to not adding a prediction mechanism and needing to access all entries, we reduced the number of accesses by 75%. For the V-BTB module, we used an 8-bit Partial Tag as an index to pre-match possible Ways. Experimental results show that 96.4% of instruction addresses hit one Way, and 3.6% of instruction addresses hit two Ways, indicating that using the 8-bit current address as the Partial Tag can effectively complete the prediction task.

[0093] Table 5. Prediction success rate of the two-stage prediction mechanism

[0094]

[0095] Table 5 shows the reduction in access counts and the success rate of the two-level prediction mechanism under our two-level structure. Experimental results show that the M-BTB prediction mechanism reduced the number of queries to M-BTB by 75%, and the V-BTB prediction mechanism reduced the number of accesses by 74.1%. The success rate of both prediction mechanisms is 100%, indicating that we effectively completed the prediction work for the Bank and Way, ensuring that all potentially hit entries were not lost, and minimizing the number of queries to the two-level prediction mechanism.

[0096] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A low-power branch target buffer with a two-level prediction mechanism, characterized in that, This includes serially connected M-BTB modules, V-BTB modules, and decision modules. The M-BTB module includes a serially connected M-BTB prediction mechanism and an M-BTB structure. The M-BTB structure includes four banks. The input current instruction address is predicted by the M-BTB prediction mechanism to determine the potential bank where the target instruction address is stored in the M-BTB structure. The current instruction address accesses the bank. The V-BTB module includes a V-BTB prediction mechanism and a V-BTB structure. The V-BTB structure includes four Ways. The input current instruction address is used by the V-BTB prediction mechanism to predict the potential Way stored in the V-BTB structure for the target instruction address. The current instruction address accesses the Way. The decision module verifies the target instruction address output by the M-BTB module and the target instruction address of the V-BTB module; The M-BTB prediction mechanism includes a two-to-four decoder. The two-to-four decoder decodes two bits of the current instruction address and the target instruction address in the M-BTB structure to obtain the corresponding Bank and stores them in the corresponding Bank. The two bits of the input current instruction address are decoded by the two-to-four decoder to obtain the target instruction address and store it in the potential Bank. The input current instruction address accesses the Bank. The V-BTB prediction mechanism includes a Partial Tag table, which contains 2K entries. Each entry is 32 bits long and is divided into A, B, C, and D, which correspond to the current instruction addresses of the four Ways, respectively. Eight bits of the current instruction addresses of the four Ways are selected and mapped to A, B, C, and D in the Partial Tag. The Partial Tag table corresponds to the four Ways in V-BTB. The 8 bits of the current instruction address are matched with the Partial Tag table, and the matched Way is selected for access. V-BTB contains 8K entries, divided into 4 Ways, each containing 2K entries.

2. The low-power branch target buffer with a two-level prediction mechanism according to claim 1, characterized in that, The M-BTB structure is a fully associative structure with 40 entries, divided into 4 banks, each containing 10 entries.

3. The design method of the low-power branch target buffer with a two-level prediction mechanism according to claim 1, characterized in that, Includes the following steps: Step S1: Input the current instruction address, access the M-BTB module, and access the M-BTB structure according to the prediction result of the M-BTB prediction mechanism. If the input current instruction address hits the M-BTB structure, proceed to step S2; otherwise, proceed to step S3. Step S2: Determine that the current input instruction is a branch instruction. The M-BTB structure outputs the target instruction address PC1 and compares it with the target instruction address PC3 output by the decision module. If PC3 is the same as PC1, the prediction result of the M-BTB module is correct and no redirection is required. Otherwise, if PC2 is different from PC1, the prediction result of the M-BTB module is incorrect and redirection is required. Step S3: The input current instruction address accesses the V-BTB module. Based on the prediction result of the V-BTB prediction mechanism, the V-BTB structure is accessed. If the input current instruction address hits the V-BTB structure, proceed to step S4. If the V-BTB structure is not hit, proceed to step S5. Step S4: Output the target instruction address PC2 and compare it with the target instruction address PC3 output by the decision module. If PC2 and PC3 are the same, the prediction result of the V-BTB module is correct and no redirection is required. Otherwise, if PC2 and PC3 are different, the prediction result of the V-BTB module is incorrect and redirection is required. Step S5: Determine that the current instruction is a sequential execution instruction and will not be verified by the decision module. The prediction result of the M-BTB module is incorrect, so no redirection will be performed.

4. The design method of the low-power branch target buffer with a two-level prediction mechanism according to claim 3, characterized in that, The redirection specifically involves: assigning the target instruction address PC3 to the PC register, sending the current instruction address and the target instruction address PC3 verified by the decision module back to the M-BTB module, and updating the M-BTB module.

5. The design method of the low-power branch target buffer with a two-stage prediction mechanism according to claim 3, characterized in that, While performing step S3 and accessing the V-BTB module, the current instruction address is sequentially incremented to the target instruction address PC1*, and returned to the PC register to continue fetching instructions.

6. The design method of the low-power branch target buffer with a two-level prediction mechanism according to claim 3, characterized in that, Step S1 specifically involves: The two bits of the current instruction address are input into the M-BTB prediction mechanism. The M-BTB prediction mechanism predicts the potential Bank for storing the target instruction address in the M-BTB structure. The current instruction address is used to select the potential Bank for storing the target instruction address in the M-BTB structure and access it. If the input current instruction address successfully matches the entry in the Bank, then the Bank is hit, that is, the current instruction address hits the M-BTB structure.

7. The design method of the low-power branch target buffer with a two-stage prediction mechanism according to claim 3, characterized in that, The M-BTB prediction mechanism is a 2-to-4 decoder that decodes a 2-bit address to obtain a 4-bit index, accesses 4 banks in the M-BTB structure, and each bank corresponds to 0001, 0010, 0100, and 1000. The current instruction address and the target instruction address in the M-BTB structure are decoded by the 2-to-4 decoder, and the corresponding bank obtained by the decoder is selected for storage.

8. The design method of the low-power branch target buffer with a two-level prediction mechanism according to claim 3, characterized in that, Step S4 specifically involves: The input current instruction address is fed into the V-BTB prediction mechanism, which is a Partial Tag table. The Partial Tag table corresponds to the four Ways in the V-BTB in sequence. The 8 bits of the input current instruction address are matched with the Partial Tag table, and the matched Way is accessed. If the input current instruction address matches the current instruction address in the Way table entry, it means that the Way is hit, that is, the current instruction address hits the V-BTB structure.

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