A detector power-on working system

Abstract

A detector power-on working system relates to the technical field of detector power-on, and solves the problem that the training result fails in the existing detector power-on working time sequence during the training process. The power-on working system includes an imaging controller and an imaging unit; the imaging unit includes an instruction parsing and sending module, a timing control module, and a training and data integration module; the imaging controller detects the training state after each training operation. Whether the training operation is ended is indicated by an indication signal of whether the training process is ended. A high level indicates that the training process has ended, and a low level indicates that the training process has not ended; when it is detected that the training fails, the operation of restarting the training is started, and when it is detected that the training is successful, the operation of restarting the training is not started. In this way, the influence of the newly started training on the previous training process and result can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of detector power-on, and particularly to a detector power-on working system based on space applications. Background Art

[0002] After the detector has completed the training after power-on configuration and received a timing reset command, it starts a training operation again. At this stage, the data output by the detector jitters and the training may fail; the detection of the training state starts before the training after the timing reset is completed. When it is detected that the training is not successful, a third training is restarted, and the final training result may also fail because the newly started training cannot start completely from the beginning.

[0003] The prior art is as Figure 1 shown. The working timing of detector power-on usually includes three steps: (1) power-on configuration and subsequent training operations; (2) timing reset and training operations after receiving a timing reset command; (3) detection of the training state. If the training is not successful, the training operation is started. After the power-on configuration and subsequent training operations, when a timing reset command is received, a training operation is restarted again. At this stage, the data output by the detector jitters and the training may fail. If a telemetry indicating training failure occurs before the training after the timing reset is completed, the detection of the training state starts at this time. When it is detected that the training is not successful, a third training is restarted, and the final training result may also fail because the newly started training cannot start completely from the beginning.

[0004] As Figure 2 shown, the training state machine loop includes three states: training idle state, training start state, and training end judgment state. State initialization is performed in the training idle state. When power-on or a training command is received, it enters the training start state, and then enters the training end judgment state. In the training end judgment state, when all channels have completed training, it returns to the training idle state. Summary of the Invention

[0005] The present invention provides a detector power-on working system to solve the problem of training result failure in the training process of the existing detector power-on working timing.

[0006] A detector power-on working system, the power-on working system includes an imaging controller and an imaging unit; the imaging unit includes an instruction parsing and sending module, a timing control module, and a training and data integration module;

[0007] The imaging controller sends instructions and status to the imaging unit through a 422 bus, and at the same time, the imaging controller sends a timing reset signal to perform the timing reset of the detector;

[0008] The instruction parsing and sending module receives the 422 communication instructions sent by the imaging controller, parses them and then sends them to the timing control module and the training and data integration module. The timing control module and the training and data integration module simultaneously return telemetry status information and transmit it to the imaging controller through the instruction parsing and sending module;

[0009] The instruction parsing and sending module receives the timing reset signal of the imaging controller and transmits it to the timing control module;

[0010] The timing control module generates the training control signal, system reset signal, timing reset signal and drive control signal required by the detector, and simultaneously transmits the power-on completion signal during the power-on process and the indication signal of the output data validity to the training and data integration module;

[0011] The training and data integration module receives the serial image data output by the detector, converts it into parallel image data for data integration and then outputs it; meanwhile, during the training process, it outputs the indication signals of the training status and stage to the timing control module; and outputs the status return signal 1 to the instruction parsing and sending module;

[0012] During the training process, the training state machine loop includes four states: training idle state, pre-training initialization state, training start state and training end judgment state;

[0013] In the training idle state, training start state and training end judgment state, when power-on or a training command is received, it enters the pre-training initialization state for state initialization; when the pre-training initialization is completed, it enters the training start state; when the training start is completed and there is no power-on or a training command is received, it enters the training end judgment state; in the training end judgment state, when all channels are trained and there is no power-on or a training command is received, it returns to the training idle state.

[0014] The beneficial effects of the present invention:

[0015] 1. The imaging controller detects the training status only after each training operation ends. Whether the training operation ends is indicated by the indication signal of whether the training process ends. A high level indicates that the training process has ended, and a low level indicates that the training process has not ended yet; when a training failure is detected, the operation of starting a new training is initiated, and when a training success is detected, the operation of starting a new training is not initiated. This can avoid the influence of the newly started training on the previous training process and results.

[0016] 2. During the training process, the number of calibration adjustments required is more than twice the number of adjusted positions, that is, it is required to detect each position at least twice. In this way, even if there are occasional jitters in the image data during the training process, the training can still succeed.

[0017] 3. During the training process, cancel the timing reset and the write operation of SPI to avoid interference from these two operations during the training process, which may cause errors in the training process.

[0018] 4. The training operation command of the present invention can interrupt the previous training operation and start completely anew, enabling the training operation to start completely over and resetting various states after the original training to avoid the influence of unsuccessful previous training. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is the working timing diagram of the existing detector when powered on;

[0020] Figure 2 is Figure 1 the schematic diagram of the state machine loop used during training;

[0021] Figure 3 is the structural diagram of the detector power-on control system of the present invention;

[0022] Figure 4 is the schematic diagram of n-bit parallel image data;

[0023] Figure 5 is the schematic diagram of channel correction of n-bit parallel image data;

[0024] Figure 6 is the schematic diagram of the training state machine loop. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In combination with Figures 3 to 6 this embodiment is described. A detector power-on working system, the power-on working system is composed of an imaging controller and an imaging unit; as Figure 3 shown, the imaging unit includes an instruction parsing and sending module, a timing control module, a training and data integration module, and a detector;

[0026] The imaging controller sends instructions and transfers status to the imaging unit via the 422 bus. Meanwhile, the imaging controller can send a timing reset signal for the timing reset of the detector. The instruction parsing and sending module receives the 422 instructions sent by the imaging controller, parses them, and then sends them to the timing control module and the training and data integration module for execution. At the same time, it returns relevant telemetry status information. The received timing reset signal is transmitted to the timing control module. The timing control module generates the training control signal, system reset signal, timing reset signal, and drive control signal required by the detector. Meanwhile, it transmits the power-on completion signal during the power-on process and the indication signal of the output data validity to the training and data integration module. The training and data integration module receives the serial image data output by the detector, converts it into parallel image data, and outputs it after data integration according to the transmission protocol. Meanwhile, it outputs the indication signal of the training status and stage to the timing module during the training process. Meanwhile, it outputs the status return signal 1 (the module outputs the training result telemetry signal and the indication signal of whether the training process is over) to the instruction parsing and sending module.

[0027] In this embodiment, the imaging controller detects the training status after each training operation ends. Whether the training operation ends is indicated by the indication signal of whether the training process ends. A high level indicates that the training process has ended, and a low level indicates that the training process has not ended yet. When a training failure is detected, the re-training operation is started. When a training success is detected, the re-training operation is not started anymore.

[0028] In this embodiment, during the training process, the training and data integration module requires that the number of times of word correction and channel correction adjustment is higher than twice the number of adjustable states, that is, it is required to detect at least twice in each state.

[0029] As Figure 4 shown, for the word correction operation, it is required that the number of times of adjusting the n-bit parallel image data combination is higher than or equal to 2n times, where n is the number of bits of the parallel image data.

[0030] As Figure 5 shown, for the channel correction, it is required that after the training control signal TRAIN sends a pulse signal with a single pixel clock cycle width, the number of delay position states of the detected parallel training word relative to the positive pulse of the TRAIN signal is 2m. Then, it is required that the number of times of channel correction detection is higher than or equal to 4m times. Before each power-on training starts, the delay position of the parallel training word relative to the positive pulse of the TRAIN signal is preset to the mth delay position.

[0031] In this embodiment, the timing control module detects the training status signal output by the training and data integration module. When in the training state, the output of the timing reset is cancelled and set to an invalid high level; at the same time, the SPI write operation is cancelled and the control signal of the SPI write operation is set to an invalid low level.

[0032] In this embodiment, the training operation command can interrupt the previous training operation state machine in the data integration module and start completely anew. Figure 6 As shown, the improved training state machine loop includes four states: training idle state, pre-training initialization state, training start state, and training end judgment state. In the training idle state, training start state, and training end judgment state, when power is applied or a training command is received, it enters the pre-training initialization state for state initialization; when the pre-training initialization is completed, it enters the training start state; when the training starts and is completed and power is not applied or a training command is not received, it enters the training end judgment state. In the training end judgment state, when all channels have been trained and power is not applied or a training command is not received, it returns to the training idle state.

[0033] In this embodiment, the imaging controller uses a minimum system board based on a domestic DSP. The instruction parsing and sending module, timing control module, and training and data integration module use an FPGA of Shanghai Fudan Microelectronics Co., Ltd. to implement related functions; the detector uses a CMOS detector of Chenxin Company.

Claims

1. A detector power-on working system, the power-on working system comprising an imaging controller and an imaging unit; characterized in that: The imaging unit includes an instruction parsing and sending module, a timing control module, and a training and data integration module; The imaging controller sends instructions and statuses to the imaging unit via a 422 bus. Meanwhile, the imaging controller sends a timing reset signal for the timing reset of the detector; The instruction parsing and sending module receives the 422 communication instructions sent by the imaging controller, parses them, and then sends them to the timing control module and the training and data integration module. The timing control module and the training and data integration module simultaneously return telemetry status information and transmit it to the imaging controller through the instruction parsing and sending module; The instruction parsing and sending module receives the timing reset signal from the imaging controller and transmits it to the timing control module; The timing control module generates the training control signal, system reset signal, timing reset signal, and drive control signal required by the detector. Meanwhile, it transmits the power-on completion signal during the power-on process and the indication signal of output data validity to the training and data integration module; The training and data integration module receives the serial image data output by the detector, converts it into parallel image data, integrates the data, and then outputs it; meanwhile, during the training process, it outputs the indication signal of the training status and stage to the timing control module; and outputs the status return signal 1 to the instruction parsing and sending module; During the training process, the training state machine loop includes four states: training idle state, pre-training initialization state, training start state, and training end judgment state; In the training idle state, training start state, and training end judgment state, when powered on or receiving a training command, it enters the pre-training initialization state for state initialization; When the pre-training initialization is completed, it enters the training start state; When the training start is completed and not powered on and not receiving a training command, it enters the training end judgment state; In the training end judgment state, when all channels are trained and not powered on and not receiving a training command, it returns to the training idle state.

2. The power-on working system of a detector according to claim 1, characterized in that: The imaging controller detects the training state after each training process; whether the training process ends is determined by the indication signal of whether the training process ends. A high level indicates that the training process has ended, and a low level indicates that the training process has not ended; When detecting training failure, it starts the operation of retraining. When detecting training success, it does not start the retraining operation again.

3. The power-on working system of a detector according to claim 1, wherein: During the training process, the training and data integration module requires that the number of times of word correction and channel correction adjustment is greater than twice the number of adjustable states, that is, it requires at least 2 detections in each state.

4. A detector power-on working system according to claim 3, characterized in that: For the word correction operation, it requires that the number of times of adjusting the n-bit parallel image data combination is greater than or equal to 2n times, where n is the number of bits of the parallel image data.

5. The power-on working system of a detector according to claim 3, wherein: For channel correction, it is required that after the training control signal TRAIN issues a pulse signal with a single pixel clock cycle width, the number of delay position states of the detected parallel training word relative to the positive pulse of the TRAIN signal is 2m. It is required that the number of times of channel correction detection is greater than or equal to 4m times; before each power-on training starts, the delay position of the parallel training word relative to the positive pulse of the TRAIN signal is pre-set to the mth delay position.

6. The power-on working system of a detector according to claim 3, characterized in that: The timing control module detects the training status signal output by the training and data integration module. When in the training state, it cancels the output of the timing reset and sets it to an invalid high level; at the same time, it cancels the SPI write operation and sets the control signal of the SPI write operation to an invalid low level.

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