A LDO circuit design method based on Python language

Abstract

The present invention discloses a Python-based LDO circuit design method, which is applied to a terminal and implemented by executing code, and includes the following steps: Step 10, determining an initial circuit structure module based on design indicators; Step 20, searching for optimal size information for each transistor in a transistor parameter database; Step 30, generating multiple test circuit modules; Step 40, calling a simulator to perform simulation testing to obtain pre-simulation results; Step 50, generating a circuit layout; Step 60, calling a simulator to perform simulation testing to obtain post-simulation results; Step 70, if the post-simulation results do not meet the design indicators, executing Step 30. The present invention codifies and automates the LDO design process, and the code can be run to complete the complete design process from circuit description, size generation, multi-index simulation, and automatic layout and routing of the layout, thereby shortening the LDO layout design cycle, improving design efficiency, and achieving full automation of the LDO circuit to layout design process.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and in particular relates to an LDO circuit design method based on Python language. Background Art

[0002] LDO circuits, with their advantages of low noise, low power consumption, high ripple rejection, excellent line regulation and load transient response, and easy integration with other on-chip modules, occupying a small chip area, are widely used in consumer electronics such as mobile phones, smart home appliances, and laptops, as well as in industrial fields such as smart home appliances and the automotive industry. However, the level of automation in analog IC design is far less mature than that of digital circuits. The current huge consumer demand and market space for analog ICs is extremely mismatched with the low level of automation in analog IC design using current EDA technology. Even small-scale LDO design development cycles are extremely long. Therefore, developing a fully automated approach to LDO design and optimization is crucial to improving the LDO development cycle, accelerating product iterations, and improving design efficiency.

[0003] In the existing technology, the design process of analog integrated circuits is divided into two parts: circuit design and layout design. The former mainly relies on and integrates the knowledge of analog integrated circuit experts to code and algorithmize the calculation of transistor size in the circuit; the latter is aimed at the layout of the layout, and proposes different algorithms under conditions such as wiring, signal delay, crosstalk and other electrical effects and area to complete the automatic generation of the layout. Both are partial automation of the design process and cannot achieve full-process automated design, which affects design efficiency. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an LDO circuit design method based on Python language. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] A Python-based LDO circuit design method is applied to a terminal and implemented by executing code, including the following steps:

[0006] Step 10: determining an initial circuit structure module based on the design indicators; the initial circuit structure module indicates a code for generating a circuit diagram, the code including a description of the topological relationship between the submodules of the circuit and the plurality of transistors based on the Python language, wherein the design indicators and process types are represented in the form of parameters in the code;

[0007] Step 20, searching for optimal size information of each transistor in a transistor parameter database according to the design index, the submodule corresponding to the initial circuit structure module, and the process type;

[0008] Step 30, returning the optimal size information to the corresponding field in the initial circuit structure module and adding multiple simulation condition information and multiple simulation stimulus information to generate multiple test circuit modules;

[0009] Step 40, generating a simulator netlist file from the simulation condition information, simulation stimulus information, submodules, and topological relationships of multiple transistors in the test circuit module, and calling the simulator to perform simulation testing to obtain a pre-simulation result;

[0010] Step 50: If the pre-simulation result meets the design specification, a circuit layout is generated according to the optimal size information, the topological relationship of the plurality of transistors, the preset relative position relationship between the plurality of transistors, and the layout constraint conditions;

[0011] Step 60, adding the parasitic parameters and interconnection delay corresponding to the circuit layout to the simulator netlist file, and calling the simulator to perform simulation testing to obtain a post-simulation result;

[0012] Step 70: If the post-simulation result does not meet the design specification, execute step 30.

[0013] In one embodiment of the present invention, step 20 includes:

[0014] Step 21, determining a transistor parameter database according to the process type;

[0015] Step 22, determining a circuit performance index calculation formula according to the submodule corresponding to the initial circuit structure module;

[0016] Step 23, searching for multiple sets of design parameters corresponding to a transistor in the transistor parameter database according to the design index;

[0017] Step 24, determining a circuit performance index based on one set of the design parameters and the circuit performance index calculation formula;

[0018] Step 25: If the circuit performance index meets the design index, the size information in the current design parameters is determined as the optimal size information;

[0019] If the circuit performance index does not meet the design index, step 24 is executed.

[0020] In one embodiment of the present invention, the transistor parameter database is a gm / ID lookup table.

[0021] In one embodiment of the present invention, the simulation condition information includes parameters of a power supply.

[0022] Beneficial effects of the present invention:

[0023] By describing the circuit structure based on the more concise Python programming language, the present invention coded and automated the LDO design process. Running the code can complete the complete design process from circuit description, size generation, multi-index simulation, and automatic layout and routing of the layout, shortening the LDO layout design cycle, improving design efficiency, and realizing the automation of the entire process from LDO circuit to layout design.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart of a Python-based LDO circuit design method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0027] like Figure 1 As shown, a Python-based LDO circuit design method is applied to a terminal and implemented by executing code, including the following steps:

[0028] Step 10, determining an initial circuit structure module based on the design indicators; the initial circuit structure module indicates the code for generating a circuit diagram, the code including a description of the sub-modules of the circuit and the topological relationship of multiple transistors based on the Python language, wherein the design indicators and process types are represented in the form of parameters in the code.

[0029] In this embodiment, the design indicators include various indicators required for LDO circuit design, such as the LDO circuit PSR (power supply rejection ratio), LDR (load regulation rate), LNR (line regulation rate), and gain. The circuit submodules include a power reference circuit, a current reference circuit, an operational amplifier, a common-source amplifier, a source follower, a power stage circuit, an overcurrent protection circuit, and other submodules. The initial circuit structure module is described in Python. Running the code program of the initial circuit structure module can generate a circuit diagram of the analog circuit. The Python language description is more concise, reducing the complexity of the code.

[0030] Specifically, each submodule of the circuit is described in code in advance to form different circuit structure modules. The circuit structure module selected as the initial circuit structure module can be determined based on the gain and power supply rejection ratio. When the circuit design method is started, a judgment and selection process is first performed: the gain and power supply rejection ratio are obtained. If the gain is greater than 60dB, the circuit structure module corresponding to the secondary structure is selected as the initial circuit structure module. If the gain is less than or equal to 60dB, the circuit structure module corresponding to the five-tube amplifier is selected as the initial circuit structure module.

[0031] At the same time, if the power supply rejection ratio PSR is greater than 90dB, the circuit structure module corresponding to the common source and common gate two-stage amplifier circuit is selected as the initial circuit structure module; if the power supply rejection ratio PSR is less than or equal to 90dB, the circuit structure module corresponding to the five-tube two-stage amplifier circuit is selected as the initial circuit structure module.

[0032] In a feasible implementation, the code of the initial circuit structure module is as follows:

[0033] @module / / Module modifier, used to identify the following content as circuit description content def LDO_core(self,VINP,VINN,vfb,IDC,vout:Output) / / Define an LDO circuit core module named LDO_core. The five required input variables in the brackets are the four input ports and one output port of the circuit.

[0034] (IDC,IDC,Vdd(),Vdd())>>Mosfet(model="pch_v1",l=l0,w=w7).rename("m7")

[0035] / / Description of circuit connection relationship. The rule is that the four ports in the first bracket are connected to the drain d, gate g, source s, and substrate b of the MOS tube in sequence. The content in the bracket of Mosfet is used to specify the type and size of the MOS tube. The same applies to the following)

[0036] ("vtail",IDC,Vdd(),Vdd())>>Mosfet(model="pch_v1",l=l0,w=w0).rename("m0")

[0037] ("vcur",VINP,"vtail",Vdd())>>Mosfet(model="pch_v1",l=l1,w=w1).rename("m1")

[0038] ("vo1",VINN,"vtail",Vdd())>>Mosfet(model="pch_v1",l=l1,w=w1).rename("m2")

[0039] ("vcur","vcur",Vss(),Vss())>>Mosfet(model="nch_v1",l=l3,w=w3).rename("m3")

[0040] ("vo1","vcur",Vss(),Vss())>>Mosfet(model="nch_v1",l=l3,w=w3).rename("m4")

[0041] ("vo2",IDC,Vdd(),Vdd())>>Mosfet(model="pch_v1",l=l6,w=w6).rename("m6")

[0042] ("vo2","vo1",Vss(),Vss())>>Mosfet(model="nch_v1",l=l5,w=w5).rename("m5")

[0043] ("vo1","r2c")>>Resistor(r=Rz).rename("Rz")

[0044] / / Description of circuit connection relationship. The rule is that the two ports in the first bracket are resistors and capacitors, which correspond to input and output respectively.

[0045] ("r2c","vo2")>>Capacitor(c=Cc).rename("Cc")

[0046] Vdd()>>(m8:=PMOS(model="pch_v1",l=l8,w=WP2,m=math.ceil(w8 / WP2))%(vo2))>>vout

[0047] (vout,vfb)>>Resistor(r=R1).rename("R1")

[0048] (vfb,Vss())>>Resistor(r=R2).rename("R2")

[0049] return vout / / return output port

[0050] Step 20: Search the transistor parameter database for the optimal size of each transistor based on the design specifications, the submodules corresponding to the initial circuit structure module, and the process type. Convert the circuit constraints and optimization specifications into static operating point requirements for each transistor, and then perform size optimization.

[0051] Specifically, step 20 includes steps 21 to 25.

[0052] Step 21: Determine a transistor parameter database based on the process type. The transistor parameter database is a gm / ID lookup table. Different process types correspond to different lookup tables. The pre-selected process type is input into the initial circuit structure module in the form of parameters.

[0053] Step 22: Determine a circuit performance index calculation formula based on the submodule corresponding to the initial circuit structure module. Different submodules correspond to different circuit performance index calculation formulas. The circuit performance index is calculated using the corresponding circuit performance index calculation formula based on the submodule corresponding to the selected initial circuit structure module.

[0054] Step 23: Search the transistor parameter database for multiple sets of design parameters corresponding to a transistor based on the design specifications. The transistor parameter database searches for multiple sets of design parameters corresponding to the design specifications. Each set of design parameters for each transistor corresponds to a size, and different sizes correspond to multiple sets of design parameters.

[0055] Step 24: Determine a circuit performance index based on one set of design parameters and a circuit performance index calculation formula. Each set of design parameters is substituted into the circuit performance index calculation formula to calculate the circuit performance index. The circuit performance index calculation formula includes multiple formulas for calculating different circuit performance indexes.

[0056] Step 25: If the circuit performance index meets the design index, the size information in the current design parameters is determined as the optimal size information. If the circuit performance index calculated based on the current set of design parameters meets the design index requirements, the size information in the current design parameters is determined as the optimal size information.

[0057] If the circuit performance index does not meet the design index, step 24 is executed. If the circuit performance index calculated based on the current set of design parameters does not meet the design index requirement, the circuit performance index is calculated using the next set of design parameters until the circuit performance index calculated based on a set of design parameters meets the design index.

[0058] In step 30, the optimal size information is returned to the corresponding fields in the initial circuit structure module and multiple simulation condition information and simulation stimulus information are added to generate multiple test circuit modules. The optimal size information, simulation condition information, and simulation stimulus information are incorporated into the initial circuit structure module to form code instructions for the test circuit module, thereby generating a circuit diagram for the test circuit. The simulation condition information includes power supply parameters; for example, the voltage source parameters differ between DC and AC simulations.

[0059] Step 40 generates a simulator netlist file based on the simulation condition information, simulation stimulus information, submodules, and topological relationships of multiple transistors in the test circuit module. The simulator is then invoked to perform simulation testing to obtain pre-simulation results. The simulator netlist file is in a format that the simulator can recognize. In this step, relevant information in the test circuit module is extracted and converted or created into a format that generates a simulator netlist file, and pre-simulation is performed.

[0060] Step 50: If the pre-simulation results meet the design specifications, a circuit layout is generated based on the optimal size information, the topological relationships of the multiple transistors, the preset relative positional relationships between the multiple transistors, and the layout constraints. In this step, the parameters of the circuit components and the relationship information between the components can be converted into a layout format, and the layout generation program automatically generates the layout, while also generating parasitic parameters and interconnect delays.

[0061] Step 60: Add the parasitic parameters and interconnection delays corresponding to the circuit layout to the simulator netlist file, and call the simulator to perform simulation testing to obtain post-simulation results.

[0062] Step 70: If the post-simulation result does not meet the design criteria, then execute step 30. If the post-simulation result does not meet the design criteria, then return to step 30 and redetermine the optimal size. If the post-simulation result meets the design criteria, then end.

[0063] This invention automates the LDO design process by coding it. Simply running the code completes the entire design process, from circuit description and dimensioning to multi-index simulation and automatic layout and routing. This shortens the LDO layout design cycle, improves design efficiency, and automates the entire LDO circuit-to-layout design process. By using the more concise Python programming language to describe the circuit structure, the code complexity is reduced, simplifying the design process.

[0064] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0066] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0067] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0068] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0069] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A Python-based LDO circuit design method, characterized in that: The method is applied to a terminal and implemented by executing code, including the following steps: Step 10: determining an initial circuit structure module based on the design indicators; the initial circuit structure module indicates a code for generating a circuit diagram, the code including a description of the topological relationship between the submodules of the circuit and the plurality of transistors based on the Python language, wherein the design indicators and process types are represented in the form of parameters in the code; Step 20, searching for optimal size information of each transistor in a transistor parameter database according to the design index, the submodule corresponding to the initial circuit structure module, and the process type; Step 30, returning the optimal size information to the corresponding field in the initial circuit structure module and adding multiple simulation condition information and multiple simulation stimulus information to generate multiple test circuit modules; Step 40, generating a simulator netlist file from the simulation condition information, simulation stimulus information, submodules, and topological relationships of multiple transistors in the test circuit module, and calling the simulator to perform simulation testing to obtain a pre-simulation result; Step 50: If the pre-simulation result meets the design specification, a circuit layout is generated according to the optimal size information, the topological relationship of the plurality of transistors, the preset relative position relationship between the plurality of transistors, and the layout constraint conditions; Step 60, adding the parasitic parameters and interconnection delay corresponding to the circuit layout to the simulator netlist file, and calling the simulator to perform simulation testing to obtain a post-simulation result; Step 70: If the post-simulation result does not meet the design specification, execute step 30; Wherein, the step 20 includes: Step 21, determining a transistor parameter database according to the process type; Step 22, determining a circuit performance index calculation formula according to the submodule corresponding to the initial circuit structure module; Step 23, searching for multiple sets of design parameters corresponding to a transistor in the transistor parameter database according to the design index; Step 24, determining a circuit performance index based on one set of the design parameters and the circuit performance index calculation formula; Step 25: If the circuit performance index meets the design index, the size information in the current design parameters is determined as the optimal size information; If the circuit performance index does not meet the design index, step 24 is executed.

2. The LDO circuit design method based on Python language according to claim 1, wherein: The transistor parameter database is a gm / ID lookup table.

3. The LDO circuit design method based on Python language according to claim 1, wherein: The simulation condition information includes parameters of a power supply.

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