A display panel, a driving method thereof, and a display device

Abstract

The present invention discloses a display panel, a driving method thereof, and a display device. Among them, in the display panel, a light-emitting control transistor of a pixel driving circuit is connected in series between an anode of a light-emitting element and a first power signal line, and a cathode switching transistor is connected in series between a cathode of the light-emitting element and a second power signal line. During at least one light-emitting stage, the conduction time of the cathode switching transistor lags behind the conduction time of the light-emitting control transistor. The display panel, the driving method thereof, and the display device provided by the embodiments of the present invention solve the problem of color cast caused by differences in pixel capacitors in light-emitting elements emitting different colors of light by connecting a cathode switching transistor in series between the cathode of the light-emitting element and the second power signal line, and making the cathode switching transistor conduct later than the light-emitting control transistor during the light-emitting stage, so that the pixel capacitors of the light-emitting elements emitting different colors of light are charged completely and then emit light simultaneously when the cathode switching transistor conducts.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel, a driving method thereof, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) display panel has the advantages of high visibility, high brightness, and being thinner and lighter. Therefore, the application of OLED display panels is becoming more and more widespread.

[0003] However, in existing OLED display panels, there is a problem of display color deviation, which affects the display effect of the display panel. Summary of the Invention

[0004] The present invention provides a display panel, a driving method thereof, and a display device to improve the problem of color deviation.

[0005] According to one aspect of the present invention, a display panel is provided, which includes a cathode switching transistor and a plurality of sub-pixels arranged in an array;

[0006] The sub-pixel includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit, and the pixel driving circuit includes a driving transistor and at least one light-emitting control transistor;

[0007] The driving transistor, the light-emitting control transistor, the light-emitting element, and the cathode switching transistor are connected in series between a first power supply signal line and a second power supply signal line. Among them, the light-emitting control transistor is connected in series between the anode of the light-emitting element and the first power supply signal line, and the cathode switching transistor is connected in series between the cathode of the light-emitting element and the second power supply signal line;

[0008] The gate of the light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the cathode switching transistor is electrically connected to a second light-emitting control signal line; within at least one light-emitting stage, the start time of the effective pulse of the second light-emitting control signal on the second light-emitting control signal line lags behind the start time of the effective pulse of the first light-emitting control signal on the first light-emitting control signal line.

[0009] According to another aspect of the present invention, a display device is provided, which includes the display panel described in the first aspect.

[0010] According to another aspect of the present invention, there is provided a driving method for a display panel, the display panel including a cathode switching transistor and a plurality of sub-pixels arranged in an array; the sub-pixels include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit, and the pixel driving circuit includes a driving transistor and at least one light-emitting control transistor; the driving transistor, the light-emitting control transistor, the light-emitting element, and the cathode switching transistor are connected in series between a first power signal line and a second power signal line, wherein the light-emitting control transistor is connected in series between the anode of the light-emitting element and the first power signal line, and the cathode switching transistor is connected in series between the cathode of the light-emitting element and the second power signal line; the gate of the light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the cathode switching transistor is electrically connected to a second light-emitting control signal line;

[0011] The driving method includes:

[0012] Applying a first light-emitting control signal to the first light-emitting control signal line;

[0013] Applying a second light-emitting control signal to the second light-emitting control signal line;

[0014] Wherein, within at least one light-emitting stage, the start time of the effective pulse of the second light-emitting control signal lags behind the start time of the effective pulse of the first light-emitting control signal.

[0015] The display panel, its driving method, and the display device provided by the embodiments of the present invention are such that by connecting a light-emitting control transistor in series between the anode of the light-emitting element and the first power signal line, and connecting a cathode switching transistor in series between the cathode of the light-emitting element and the second power signal line, and electrically connecting the gate of the light-emitting control transistor to the first light-emitting control signal line and the gate of the cathode switching transistor to the second light-emitting control signal line, and by setting that within the light-emitting stage, the start time of the effective pulse of the second light-emitting control signal on the second light-emitting control signal line lags behind the start time of the effective pulse of the first light-emitting control signal on the first light-emitting control signal line, so that within the light-emitting stage, the light-emitting control transistor is turned on first to charge the pixel capacitor of the light-emitting element, and after the pixel capacitors of the light-emitting elements emitting different colors of light are charged, then the cathode switching transistor is turned on, so that the light-emitting elements emitting different colors of light emit light simultaneously when the cathode switching transistor is turned on, thereby making the light-emitting durations of the light-emitting elements emitting different colors of light tend to be consistent during the light-emitting stage and the light-emitting efficiencies tend to be consistent, and solving the color cast problem caused by the differences in pixel capacitors among the light-emitting elements emitting different colors of light.

[0016] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 Schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 is Figure 1 Schematic cross-sectional structure diagram along the A-A' direction;

[0020] Figure 3 Schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0021] Figure 4 Schematic driving timing diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0022] Figure 5 Schematic structural diagram of a pixel driving circuit in the related art;

[0023] Figure 6 Schematic driving timing diagram of a pixel driving circuit in the related art;

[0024] Figure 7 Schematic potential diagram of the N4 node of a pixel driving circuit in the related art during the light-emitting stage;

[0025] Figure 8 Schematic luminous efficiency curve diagram of a sub-pixel in the related art;

[0026] Figure 9 Schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0027] Figure 10 Schematic driving timing diagram of a pixel driving circuit in the first sub-pixel row provided by an embodiment of the present invention;

[0028] Figure 11 Schematic driving timing diagram of a pixel driving circuit in the second sub-pixel row provided by an embodiment of the present invention;

[0029] Figure 12Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0030] Figure 13 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0031] Figure 14 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0032] Figure 15 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0033] Figure 16 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0034] Figure 17 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0035] Figure 18 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0036] Figure 19 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0037] Figure 20 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0038] Figure 21 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0039] Figure 22 is Figure 21 A cross-sectional structural schematic diagram along the C-C' direction;

[0040] Figure 23 Another structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0041] Figure 24 A partial cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0042] Figure 25 Another partial cross-sectional structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0043] Figure 26 A structural schematic diagram of a display device provided by an embodiment of the present invention;

[0044] Figure 27 A flowchart of a driving method for a display panel provided by an embodiment of the present invention. Detailed implementation manners

[0045] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1 It is a schematic structural diagram of a display panel provided by an embodiment of the present invention Figure 2 is Figure 1 a schematic cross-sectional structural diagram along the A-A' direction Figure 3 It is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention Figure 4 It is a schematic driving timing diagram of a pixel driving circuit provided by an embodiment of the present invention, such as Figures 1 - 4As shown in the figure, the display panel provided by the embodiment of the present invention includes a cathode switching transistor M0 and a plurality of sub-pixels 11 arranged in an array. The sub-pixel 11 includes a pixel driving circuit 111 and a light-emitting element 112 electrically connected to the pixel driving circuit 111. The pixel driving circuit 111 includes a driving transistor M3 and at least one light-emitting control transistor M16. The driving transistor M3, the light-emitting control transistor M16, the light-emitting element 112, and the cathode switching transistor M0 are connected in series between a first power supply signal line PVDD and a second power supply signal line PVEE. Among them, the light-emitting control transistor M16 is connected in series between the anode of the light-emitting element 112 and the first power supply signal line PVDD, and the cathode switching transistor M0 is connected in series between the cathode of the light-emitting element 112 and the second power supply signal line PVEE. The gate of the light-emitting control transistor M16 is electrically connected to a first light-emitting control signal line EM1, and the gate of the cathode switching transistor M0 is electrically connected to a second light-emitting control signal line EM2. During at least one light-emitting stage, the start time of the effective pulse of the second light-emitting control signal of the second light-emitting control signal line EM2 lags behind the start time of the effective pulse of the first light-emitting control signal of the first light-emitting control signal line EM1.

[0048] Specifically, as Figures 1 - 4 shown, the display panel provided in this embodiment may be an Organic Light Emitting Diode (OLED) display panel. A plurality of sub-pixels 11 are arranged in an array on the display panel. The plurality of sub-pixels 11 may include at least two sub-pixels 11 of different colors. For example, as Figure 1 shown, the plurality of sub-pixels 11 may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. In other embodiments, a white sub-pixel may also be included, etc., to achieve color image display.

[0049] Among them, Figure 1 only the standard RGB arrangement of the plurality of sub-pixels 11 on the display panel is used for exemplary illustration. In other embodiments, the plurality of sub-pixels 11 may also be arranged in other ways. In addition, the shape of the light-emitting area of the sub-pixel 11 includes but is not limited to Figure 1 the rectangle shown in the figure. In other embodiments, the shape of the light-emitting area of the sub-pixel 11 can also be designed according to actual needs.

[0050] Furthermore, the sub-pixel 11 includes a pixel driving circuit 111 and a light-emitting element 112, as Figure 2As shown in the figure, taking the light-emitting element 112 as an organic light-emitting diode as an example for illustration, the light-emitting element 112 may include an anode 21, a light-emitting layer 22, and a cathode 23 which are stacked. When electrons and holes are respectively injected into the light-emitting layer 22 from the cathode 23 and the anode 21, excitons will be formed in the light-emitting layer 22 and the light-emitting molecules will be excited, so that the light-emitting layer 22 emits visible light. Among them, by setting different materials of the light-emitting layer 22, visible light of different colors can be emitted.

[0051] Continue to refer to Figure 2 and Figure 3 , the pixel driving circuit 111 is electrically connected to the light-emitting element 112. The pixel driving circuit 111 is configured to transmit a light-emitting driving current to the light-emitting element 112 under the action of signals of signal lines (such as scan signal lines, data signal lines, power supply signal lines, etc.) driven on the display panel, so as to provide a driving current for the light-emitting element 112 to drive the light-emitting element 112 to emit light.

[0052] Specifically, as Figure 2 and Figure 3 shown, in the pixel driving circuit 111, the light-emitting element 112, the driving transistor M3, and the light-emitting control transistor M16 are connected in series between the first power supply signal line PVDD and the second power supply signal line PVEE, and the light-emitting control transistor M16 is connected in series between the anode of the light-emitting element 112 and the first power supply signal line PVDD. Among them, the first power supply signal line PVDD is used to transmit the first power supply voltage, the second power supply signal line PVEE is used to transmit the second power supply voltage, and the first power supply voltage is greater than the second power supply voltage.

[0053] Among them, the driving transistor M3 can be turned on according to the potential of its gate, and the driving current formed by its conduction is used to drive the light-emitting element 112 to emit light. Among them, the driving transistor M3 serves as a driving transistor, and the gate potential of the driving transistor M3 will determine the magnitude of its conduction current, so that the light-emitting brightness of the light-emitting element 112 can be adjusted by controlling the gate voltage of the driving transistor M3 to achieve grayscale control.

[0054] The light-emitting control transistor M16 is used to control the conduction or disconnection between the driving transistor M3 and the first power supply signal terminal PVDD. Among them, the light-emitting control transistor M16 serves as a switching transistor, and the light-emitting control transistor M16 is turned on and off according to its gate voltage. As Figure 3 shown, the gate of the light-emitting control transistor M16 is electrically connected to the light-emitting control signal line EM1, so that the light-emitting control transistor M16 can be turned on or off under the control of the first light-emitting control signal transmitted by the light-emitting control signal line EM1.

[0055] Figure 5 is a schematic structural diagram of a pixel driving circuit in the related art. Figure 6It is a schematic diagram of the driving timing of a pixel driving circuit in the related art, as Figure 5 and Figure 6 shown. Exemplarily, taking the pixel driving circuit 111 as a 7T1C circuit as an example for illustration, the pixel driving circuit 111 may further include:

[0056] A first reset transistor M5, the gate of the first reset transistor M5 is electrically connected to the first scan signal line S1, the first pole of the first reset transistor M5 is electrically connected to the reference signal line Vref, and the second pole of the first reset transistor M5 is connected to the gate of the driving transistor M3 at the first node N1.

[0057] A data writing transistor M2, the gate of the data writing transistor M2 is electrically connected to the second scan signal line S2, the first pole of the data writing transistor M2 is electrically connected to the data signal line Vdata, and the second pole of the data writing transistor M2 is electrically connected to the first pole of the driving transistor M3.

[0058] An additional transistor M4, the gate of the additional transistor M4 is electrically connected to the second scan signal line S2, the first pole of the additional transistor M4 is electrically connected to the second pole of the driving transistor M3, and the second pole of the additional transistor M4 is electrically connected to the first node N1.

[0059] A light-emitting reset transistor M7, the gate of the light-emitting reset transistor M7 is connected to the first scan signal line S1, the first pole of the light-emitting reset transistor M7 is electrically connected to the reference signal line Vref, and the second pole of the light-emitting reset transistor M7 is electrically connected to the anode of the light-emitting element 112.

[0060] A first capacitor Cst, one end of the first capacitor Cst is electrically connected to the first power supply signal line PVDD, and the other end of the first capacitor Cst is electrically connected to the first node N1.

[0061] Among them, as Figure 5 and Figure 6 shown, the driving process of the pixel driving circuit 111 is, for example:

[0062] In the initialization stage T1, the first scan signal Scan1 on the first scan signal line S1 makes the first reset transistor M5 conduct, and the reference voltage on the reference signal line Vref is applied to one end of the first capacitor Cst through the first reset transistor M5, that is, the potential of the first node N1 is the reference voltage to reset the first node N1. At this time, the potential of the gate of the driving transistor M3 is also the reference voltage.

[0063] Meanwhile, in the initialization stage T1, the first scan signal Scan1 on the first scan signal line S1 turns on the light-emitting reset transistor M7. The light-emitting reset transistor M7 writes the reference voltage on the reference signal line Vref to the anode of the light-emitting element 112, resetting the anode potential of the light-emitting element 112. This can reduce the influence of the anode voltage of the light-emitting element 112 in the previous frame on the anode voltage of the light-emitting element 112 in the subsequent frame, which helps to improve the display uniformity.

[0064] In the data signal voltage writing stage T2, the second scan signal Scan2 on the second scan signal line S2 turns on the data writing transistor M2 and the additional transistor M4. At this time, the gate potential of the driving transistor M3 is the reference voltage, and the driving transistor M3 is also turned on. The data signal voltage on the data signal line Vdata is applied to the first node N1 through the data writing transistor M2, the driving transistor M3, and the additional transistor M4, thereby writing the data signal voltage into the first capacitor Cst.

[0065] In the light-emitting stage T3, the first light-emitting control signal Emit1 on the light-emitting control signal line EM1 turns on the light-emitting control transistor M16. A current path is formed among the first power supply signal line PVDD, the light-emitting control transistor M16, the driving transistor M3, the light-emitting element 112, and the second power supply signal line PVEE, so that the driving current generated by the driving transistor M3 is provided to the light-emitting element 112. Thus, the light-emitting element 112 is driven to emit light through the driving transistor M3, realizing the light-emitting and display functions of the display panel.

[0066] Figure 7 It is a voltage schematic diagram of the N4 node of a pixel driving circuit in the related art during the light-emitting stage. Figure 8 It is a light-emitting efficiency curve diagram of a sub-pixel in the related art, as Figures 5 - 8 shown. The inventor has found through research that in the light-emitting stage T3, the first light-emitting control signal Emit1 on the light-emitting control signal line EM1 turns on the light-emitting control transistor M16. The light-emitting element 112 has a pixel capacitor. After the light-emitting control transistor M16 is turned on, it will first charge the pixel capacitor of the light-emitting element 112. At this time, the anode potential of the light-emitting element 112 (i.e., the potential of the N4 node) gradually rises. When the pixel capacitor of the light-emitting element 112 is fully charged, the light-emitting element 112 starts to continuously emit light.

[0067] Since the materials of the light-emitting layers 22 of the light-emitting elements 112 emitting different colors of light are different, the light-emitting elements 112 emitting different colors of light have different pixel capacitances. Among them, the light-emitting element 112 with a smaller pixel capacitance requires a shorter time to charge the pixel capacitance of the light-emitting element 112 during the light-emitting stage T3; while the light-emitting element 112 with a larger pixel capacitance requires a longer time to charge the pixel capacitance of the light-emitting element 112 during the light-emitting stage T3. Since the light-emitting element 112 does not emit light until the pixel capacitance is fully charged, within the limited duration of the light-emitting stage T3 in one frame, the longer the charging time of the pixel capacitance of the light-emitting element 112, the later the light-emitting start time of the light-emitting element 112, and the shorter the light-emitting duration of the light-emitting element 112, thus resulting in a lower light-emitting efficiency of the light-emitting element 112; similarly, the shorter the charging time of the pixel capacitance of the light-emitting element 112, the earlier the light-emitting start time of the light-emitting element 112, and the longer the light-emitting duration of the light-emitting element 112, thus enabling a higher light-emitting efficiency of the light-emitting element 112.

[0068] Therefore, as Figure 8 shown, the light-emitting elements 112 emitting different colors of light (such as the red sub-pixel R, green sub-pixel G, and blue sub-pixel B in the figure) have differences in the charging time (or light-emitting time) of the pixel capacitance during the light-emitting stage T3 due to the differences in their pixel capacitances, resulting in relatively large differences in the changes in the light-emitting efficiency of the light-emitting elements 112 emitting different colors of light at low gray levels, thus causing a color shift problem.

[0069] Based on the above technical problems, as Figure 3 and Figure 4 shown, in this embodiment, a cathode switching transistor M0 is arranged in series between the cathode of the light-emitting element 112 and the second power supply signal line PVEE, and the gate of the cathode switching transistor M0 is electrically connected to the second light-emitting control signal line EM2.

[0070] Within at least one light-emitting stage T3 of one frame duration, it is set that the effective pulse start time of the second light-emitting control signal Emit2 of the second light-emitting control signal line EM2 lags behind the effective pulse start time of the first light-emitting control signal Emit1 of the first light-emitting control signal line EM1.

[0071] With such a setting, as Figure 3 and Figure 4 shown, the light-emitting stage T3 includes a first light-emitting sub-stage T31 and a second light-emitting sub-stage T32 arranged in sequence. Among them, the first light-emitting sub-stage T31 is the time period between the effective pulse start time of the second light-emitting control signal Emit2 of the second light-emitting control signal line EM2 and the effective pulse start time of the first light-emitting control signal Emit1 of the first light-emitting control signal line EM1.

[0072] Continue to refer to Figure 3 and Figure 4 In the first light-emitting sub-phase T31, the first light-emitting control signal Emit1 on the light-emitting control signal line EM1 transitions to an effective pulse, causing the light-emitting control transistor M16 to conduct, and the second light-emitting control signal Emit2 on the second light-emitting control signal line EM2 controls the cathode switch transistor M0 to turn off. At this time, the anode of the light-emitting element 112 and the first power supply signal line PVDD are connected, and the driving current formed by the conduction of the driving transistor M3 charges the pixel capacitor of the light-emitting element 112; while the cathode of the light-emitting element 112 and the second power supply signal line PVEE are disconnected. Therefore, in the first light-emitting sub-phase T31, even if the pixel capacitor of the light-emitting element 112 is fully charged, the light-emitting element 112 will not emit light.

[0073] In the second light-emitting sub-phase T32, the first light-emitting control signal Emit1 on the light-emitting control signal line EM1 remains an effective pulse, causing the light-emitting control transistor M16 to remain conducting, that is, the anode of the light-emitting element 112 and the first power supply signal line PVDD remain connected. The second light-emitting control signal Emit2 on the second light-emitting control signal line EM2 transitions to an effective pulse, causing the cathode switch transistor M0 to conduct. At this time, at the start time of the effective pulse of the second light-emitting control signal Emit2 on the second light-emitting control signal line EM2, the cathode switch transistor M0 conducts, causing the cathode of the light-emitting element 112 and the second power supply signal line PVEE to be connected. Since the pixel capacitors of the light-emitting elements 112 emitting different colors of light have all completed the charging process in the first light-emitting sub-phase T31, therefore, the light-emitting elements 112 emitting different colors of light can directly emit light when the cathode switch transistor M0 conducts, without having to go through the stage of charging the pixel capacitor again. Thus, the light-emitting elements 112 emitting different colors of light start to emit light simultaneously in the light-emitting stage T3, that is, the light-emitting start times of the light-emitting elements 112 emitting different colors of light in the light-emitting stage T3 become consistent, and then the light-emitting durations of the light-emitting elements 112 emitting different colors of light in the light-emitting stage T3 will be more consistent, thereby making the light-emitting efficiencies of the light-emitting elements 112 tend to be consistent, solving the color cast problem caused by the differences in pixel capacitors among the light-emitting elements 112 emitting different colors of light.

[0074] It should be noted that Figure 3 the pixel driving circuit shown in Figure 5 adds a cathode switch transistor M0 on the basis of the 7T1C circuit in Figure 3 and Figure 5In the pixel driving circuit structure, in other types of pixel driving circuit structures, by connecting a cathode switching transistor M0 in series to the cathode of the light-emitting element 112, it is also possible to make the light-emitting elements 112 emitting different colors of light emit simultaneously when the cathode switching transistor M0 is turned on, so that the light-emitting duration of the light-emitting elements 112 emitting different colors of light during the light-emitting stage T3 tends to be consistent, and the light-emitting efficiency of the light-emitting elements 112 tends to be consistent, thus solving the color cast problem caused by the difference in pixel capacitance among the light-emitting elements 112 emitting different colors of light.

[0075] Continue to refer to Figure 3 and Figure 5 , optionally, at least one light-emitting control transistor M16 includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6. The gate of the first light-emitting control transistor M1 is electrically connected to the first light-emitting control signal line EM1, the first pole of the first light-emitting control transistor M1 is electrically connected to the first power supply signal line PVDD, and the second pole of the first light-emitting control transistor M1 is electrically connected to the first pole of the driving transistor M3; the gate of the second light-emitting control transistor M6 is electrically connected to the first light-emitting control signal line EM1, the first pole of the second light-emitting control transistor M6 is electrically connected to the second pole of the driving transistor M3, and the second pole of the second light-emitting control transistor M6 is electrically connected to the light-emitting element 112.

[0076] Among them, by setting the light-emitting control transistor M16 to include two transistors, namely the first light-emitting control transistor M1 and the second light-emitting control transistor M6, during the non-light-emitting stage, the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are simultaneously turned off under the action of the first light-emitting control signal Emit1 on the light-emitting control signal line EM1, so as to ensure that the light-emitting element 112 is disconnected from the first power supply signal line PVDD, thereby avoiding the leakage current generated by the light-emitting control transistor M16 causing the light-emitting element 112 to emit light secretly during the non-light-emitting stage and affecting the display effect.

[0077] In summary, for the display panel provided by the embodiment of the present invention, a light-emitting control transistor is connected in series between the anode of the light-emitting element and the first power signal line, and a cathode switch transistor is connected in series between the cathode of the light-emitting element and the second power signal line. The gate of the light-emitting control transistor is electrically connected to the first light-emitting control signal line, and the gate of the cathode switch transistor is electrically connected to the second light-emitting control signal line. By setting that, within the light-emitting stage, the start time of the effective pulse of the second light-emitting control signal on the second light-emitting control signal line lags behind the start time of the effective pulse of the first light-emitting control signal on the first light-emitting control signal line, so that within the light-emitting stage, the light-emitting control transistor is turned on first to charge the pixel capacitor of the light-emitting element. After the pixel capacitors of the light-emitting elements emitting different colors of light are charged, the cathode switch transistor is turned on, so that the light-emitting elements emitting different colors of light emit light simultaneously when the cathode switch transistor is turned on, thereby making the light-emitting duration of the light-emitting elements emitting different colors of light tend to be consistent during the light-emitting stage, and the light-emitting efficiency tend to be consistent, and solving the color cast problem caused by the difference in pixel capacitors in the light-emitting elements emitting different colors of light.

[0078] Continuing to refer to Figures 1 - 4 , optionally, at least some of the sub-pixels 11 have different light-emitting colors. The light-emitting elements 112 in the sub-pixels 11 have corresponding pixel capacitors, and the capacitance values of the pixel capacitors of the light-emitting elements 112 in the sub-pixels 11 with different light-emitting colors are different. In at least one row of sub-pixels, the sub-pixel with the largest capacitance value of the pixel capacitor of the light-emitting element 112 is the sub-pixel with the largest capacitance, and the charging time of the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance is t1. For at least one row of sub-pixels 11, within the light-emitting stage T3, the start time of the effective pulse of the second light-emitting control signal Emit2 on the second light-emitting control signal line EM2 corresponding to the sub-pixel 11 lags behind the start time of the effective pulse of the first light-emitting control signal Emit1 on the first light-emitting control signal line EM1 corresponding to the sub-pixel 11 by a time duration of the delay time, where the delay time is Δt, and Δt≥t1.

[0079] As described above, the display panel includes at least two types of sub-pixels 11 with different colors. As Figure 1 shown, the display panel may include red sub-pixels R, green sub-pixels G, and blue sub-pixels B. In other embodiments, it may also include white sub-pixels, etc., to achieve color image display.

[0080] Among them, for the light-emitting elements 112 emitting different colors of light, due to the difference in the materials of their light-emitting layers 22, the pixel capacitors of the light-emitting elements 112 emitting different colors of light have different capacitance values.

[0081] Continuing to refer to Figures 1 - 4, the display panel includes a plurality of data signal lines Vdata and a plurality of second scan signal lines S2. The extending directions of the data signal lines Vdata and the second scan signal lines S2 intersect, and the plurality of data signal lines Vdata and the second scan signal lines S2 cross to define a plurality of sub-pixels 11.

[0082] Among them, the plurality of second scan signal lines S2 can extend along the row direction and be arranged along the column direction. One second scan signal line S2 is correspondingly arranged and electrically connected to the pixel driving circuit 111 of one row of sub-pixels 11; the plurality of data signal lines Vdata can extend along the column direction and be arranged along the row direction. One data signal line Vdata is correspondingly arranged and connected to the pixel driving circuit 111 of one column of sub-pixels 11. The second scan signal line S2 is used to provide a second scan signal Scan2 to the pixel driving circuit 111 of the corresponding row of sub-pixels 11, so that the data signal on the data signal line Vdata can be written into the pixel driving circuit 111 of the corresponding row of sub-pixels 11. The second scan signal Scan2 mentioned here refers to the effective pulse signal output by the second scan signal line S2. For example, in the structure of the pixel driving circuit 111 shown in Figure 3 , the second scan signal Scan2 output by the second scan signal line S2 is a signal that can turn on the data writing transistor M2 and the additional transistor M4. Among them, when the data writing transistor M2 and the additional transistor M4 are PMOS, the second scan signal Scan2 is at a low level, and when the data writing transistor M2 and the additional transistor M4 are NMOS, the second scan signal Scan2 is at a high level.

[0083] Similarly, the setting methods of the first scan signal line S1, the light emission control signal line EM1, and the second light emission control signal line EM2 are similar to those of the second scan signal line S2, that is, one signal line is correspondingly arranged and electrically connected to the pixel driving circuit 111 of one row of sub-pixels 11, so as to provide corresponding scan signals to the pixel driving circuit 111 of the corresponding row of sub-pixels 11.

[0084] Therefore, the driving processes of the pixel driving circuits 111 of the sub-pixels 11 in the same row are carried out simultaneously, that is, the initialization stage T1, the data signal voltage writing stage T2, and the light emission stage T3 (including the first light emission sub-stage T31 and the second light emission sub-stage T32) of the sub-pixels 11 in the same row are all carried out synchronously.

[0085] Continue to refer to Figure 1, in a row of sub-pixels 111, there may be at least two sub-pixels 11 of different colors, and the capacitance values of the pixel capacitors of the light-emitting elements 112 in the sub-pixels 11 of different colors are different. Among them, in a row of sub-pixels 111, the sub-pixel 11 with the largest capacitance value of the pixel capacitor of the light-emitting element 112 is the sub-pixel with the largest capacitance in this row of sub-pixels 111. As mentioned above, the larger the capacitance value of the pixel capacitor of the light-emitting element 112, the longer the time required to charge the pixel capacitor of the light-emitting element 112 during the light-emitting stage T3. Therefore, the sub-pixel 11 with the largest capacitance value of the pixel capacitor of the light-emitting element 112 is the sub-pixel 11 that requires the longest charging time during the light-emitting stage T3.

[0086] In this embodiment, the charging time of the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance is t1. During the light-emitting stage T3 of any row of sub-pixels 11, the duration by which the start time of the effective pulse of the second light-emitting control signal Emit2 of the second light-emitting control signal line EM2 corresponding to the sub-pixel 11 lags behind the start time of the effective pulse of the first light-emitting control signal Emit1 of the first light-emitting control signal line EM1 corresponding to the sub-pixel 11 is the delay time △t. Among them, as Figure 4 shown, the delay time △t is the duration of the first light-emitting sub-stage T31.

[0087] By setting the delay time △t to be greater than or equal to the charging time t1 of the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance, it can be ensured that during the first light-emitting sub-stage T31, the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance can complete the charging. It can be understood that in a row of sub-pixels 111, since the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance is the largest and requires the longest charging time during the light-emitting stage T3, the charging time required for the pixel capacitors of the light-emitting elements 112 in the sub-pixels 111 other than the sub-pixel with the largest capacitance in this row of sub-pixels 111 is less than the charging time required for the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance. Therefore, during the first light-emitting sub-stage T31 of this row of sub-pixels 111, if the pixel capacitor of the light-emitting element 112 in the sub-pixel with the largest capacitance can complete the charging, then the pixel capacitors of the light-emitting elements 112 in the sub-pixels 111 other than the sub-pixel with the largest capacitance in this row of sub-pixels 111 will definitely be able to complete the charging process of the pixel capacitors in the light-emitting elements 112 during the first light-emitting sub-stage T31.

[0088] Therefore, in this embodiment, for any row of sub-pixels 11, by setting the delay time Δt to be greater than or equal to the charging time t1 of the pixel capacitance of the light-emitting element 112 in the maximum capacitance sub-pixel, it is possible to enable any row of sub-pixels 11 to complete the charging process of the pixel capacitance of the light-emitting element 112 in all the sub-pixels 11 in this row within the first light-emitting sub-stage T31. Thus, it can be ensured that each row of sub-pixels 11 emits light simultaneously when the cathode switching transistor M0 corresponding to the sub-pixels 11 in this row is turned on (i.e., at the start time of the effective pulse of the second light-emitting control signal Emit2 of the second light-emitting control signal line EM2, or at the start time of the second light-emitting sub-stage T32), without the need to charge the pixel capacitance of the light-emitting element 112 again. As a result, the light-emitting elements 112 that emit different colors of light in the same row of sub-pixels 11 have the same light-emitting start time in the light-emitting stage T3, and the light-emitting duration of the light-emitting elements 112 that emit different colors of light in the light-emitting stage T3 will tend to be the same, so that the light-emitting efficiency of the light-emitting element 112 tends to be the same, solving the color cast problem caused by the difference in pixel capacitance among the light-emitting elements 112 that emit different colors of light.

[0089] Continuing to refer to Figures 1 - 4 , optionally, the multiple sub-pixels 11 include a first-color sub-pixel 11a, a second-color sub-pixel 11b, and a third-color sub-pixel 11c. The capacitance value of the pixel capacitance of the light-emitting element 112 in the first-color sub-pixel 11a is greater than the capacitance value of the pixel capacitance of the light-emitting element 112 in the second-color sub-pixel 11b, and the capacitance value of the pixel capacitance of the light-emitting element 112 in the second-color sub-pixel 11b is greater than the capacitance value of the pixel capacitance of the light-emitting element 112 in the third-color sub-pixel 11c; the charging time of the pixel capacitance of the light-emitting element 112 in the first-color sub-pixel 11a is t2, where Δt ≥ t2.

[0090] Specifically, as Figure 1 shown, the display panel includes three types of sub-pixels 11 that emit different colors of light, namely a first-color sub-pixel 11a, a second-color sub-pixel 11b, and a third-color sub-pixel 11c, to achieve color image display.

[0091] Among them, the first-color sub-pixel 11a is the sub-pixel 11 with the largest capacitance value of the pixel capacitance of the light-emitting element 112 among the three types of sub-pixels 11 that emit different colors of light, that is, the first-color sub-pixel 11a is the sub-pixel 11 with the largest capacitance value of the pixel capacitance of the light-emitting element 112 in the entire display panel. Then, the first-color sub-pixel 11a is the sub-pixel 11 in the entire display panel that requires the longest charging time in the light-emitting stage T3.

[0092] In this embodiment, by setting the delay time Δt to be greater than or equal to the charging time t2 of the pixel capacitor of the light-emitting element 112 in the first color sub-pixel 11a, regardless of the sub-pixels 11 of various colors included in each row of sub-pixels 11, it can be ensured that the pixel capacitors of the light-emitting elements 112 in each row of sub-pixels 11 are charged within the first light-emitting sub-stage T31. Thus, it can be ensured that each row of sub-pixels 11 emits light simultaneously when the cathode switching transistor M0 corresponding to each row of sub-pixels 11 is turned on (i.e., at the start time of the effective pulse of the second light-emitting control signal Emit2 of the second light-emitting control signal line EM2, or at the start time of the second light-emitting sub-stage T32), without the need to charge the pixel capacitors of the light-emitting elements 112 again, so that the light-emitting elements 112 emitting different colors of light in the same row of sub-pixels 11 have the same light-emitting start time in the light-emitting stage T3. Then, the light-emitting durations of the light-emitting elements 112 emitting different colors of light tend to be the same in the light-emitting stage T3, and the light-emitting efficiencies of the light-emitting elements 112 tend to be the same, solving the color cast problem caused by the differences in pixel capacitors among the light-emitting elements 112 emitting different colors of light.

[0093] Optionally, the delay time Δt corresponding to each row of sub-pixels 11 is equal.

[0094] As described above, when the delay time Δt is greater than or equal to the charging time t2 of the pixel capacitor of the light-emitting element 112 in the first color sub-pixel 11a, regardless of the sub-pixels 11 of various colors included in each row of sub-pixels 11, it can be ensured that the pixel capacitors of the light-emitting elements 112 in each row of sub-pixels 11 are charged within the first light-emitting sub-stage T31.

[0095] On this basis, by setting the delay time Δt corresponding to each row of sub-pixels 11 to be equal, that is, the durations of the first light-emitting sub-stage T31 in the driving process of each row of sub-pixels 11 are equal, the driving processes of the pixel driving circuits 111 in each row of sub-pixels 11 can be made consistent.

[0096] At this time, as Figure 4 shown, the second light-emitting control signal Emit2 of the second light-emitting control signal line EM2 can be a periodic pulse signal having the same waveform as the first light-emitting control signal Emit1 of the first light-emitting control signal line EM1. The second light-emitting control signal Emit2 can be provided to the second light-emitting control signal line EM2 by only one scanning driving circuit, and the scanning driving circuit providing the second light-emitting control signal Emit2 can have the same circuit structure as the scanning driving circuit providing the first light-emitting control signal Emit1. The output first light-emitting control signal Emit1 and the second light-emitting control signal Emit2 are only misaligned in time, thereby reducing the design difficulty of the scanning driving circuit providing the second light-emitting control signal Emit2 and being easy to implement.

[0097] Optionally, 2 μs ≤ Δt ≤ 4 μs.

[0098] Among them, the inventors have found through research that when the delay time Δt corresponding to each row of sub-pixels 11 is greater than or equal to 2 μs, regardless of the sub-pixels 11 that emit light of any color in each row of sub-pixels 11, it can ensure that the pixel capacitors of the light-emitting elements 112 in each row of sub-pixels 11 are charged within the first light-emitting sub-phase T31, so as to ensure that each row of sub-pixels 11 emits light simultaneously when the cathode switching transistor M0 corresponding to each row of sub-pixels 11 is turned on, without the need to charge the pixel capacitors of the light-emitting elements 112 again, making the light-emitting starting times of the light-emitting elements 112 that emit different colors of light in the same row of sub-pixels 11 consistent, the light-emitting durations of the light-emitting elements 112 in the light-emitting phase T3 tend to be consistent, and the light-emitting efficiencies of the light-emitting elements 112 tend to be consistent, solving the color cast problem caused by the differences in pixel capacitors among the light-emitting elements 112 that emit different colors of light.

[0099] At the same time, by setting the delay time Δt corresponding to each row of sub-pixels 11 to be less than or equal to 4 μs, the duration of the first light-emitting sub-phase T31 will not be too long to severely compress the light-emitting duration of the light-emitting element 112 in the light-emitting phase T3 (i.e., the duration of the second light-emitting sub-phase T32), thereby ensuring that the light-emitting element 112 has a long light-emitting time in the light-emitting phase T3 and ensuring that the light-emitting element 112 has a high light-emitting efficiency.

[0100] Figure 9 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 10 It is a schematic diagram of the driving timing of the pixel driving circuit in the first sub-pixel row provided by an embodiment of the present invention. Figure 11 It is a schematic diagram of the driving timing of the pixel driving circuit in the second sub-pixel row provided by an embodiment of the present invention. As Figures 9 - 11 shown, optionally, the multiple sub-pixels 11 include a first sub-pixel row 31 and a second sub-pixel row 32. The light-emitting colors of the maximum-capacitance sub-pixels in the first sub-pixel row 31 and the second sub-pixel row 32 are different, and the capacitance value of the pixel capacitor of the maximum-capacitance sub-pixel in the first sub-pixel row 31 is greater than the capacitance value of the pixel capacitor of the maximum-capacitance sub-pixel in the second sub-pixel row 32. The delay time Δt corresponding to the first sub-pixel row 31 is greater than the delay time Δt corresponding to the second sub-pixel row 32.

[0101] Among them, the display panel includes a first sub-pixel row 31 and a second sub-pixel row 32. The emission colors of the sub-pixels 11 included in the first sub-pixel row 31 and the sub-pixels 11 included in the second sub-pixel row 32 are at least partially different, resulting in different emission colors of the maximum capacitance sub-pixels in the first sub-pixel row 31 and the maximum capacitance sub-pixels in the second sub-pixel row 32.

[0102] Exemplarily, as Figure 9 shown, taking the display panel including a first color sub-pixel 11a, a second color sub-pixel 11b, and a third color sub-pixel 11c as an example, and the capacitance value of the pixel capacitance of the light-emitting element 112 in the first color sub-pixel 11a is greater than the capacitance value of the pixel capacitance of the light-emitting element 112 in the second color sub-pixel 11b, and the capacitance value of the pixel capacitance of the light-emitting element 112 in the second color sub-pixel 11b is greater than the capacitance value of the pixel capacitance of the light-emitting element 112 in the third color sub-pixel 11c. The first sub-pixel row 31 is formed by arranging the first color sub-pixel 11a and the second color sub-pixel 11b, and the second sub-pixel row 32 is formed by arranging the second color sub-pixel 11b and the third color sub-pixel 11c. Then, the maximum capacitance sub-pixel in the first sub-pixel row 31 is the first color sub-pixel 11a, and the maximum capacitance sub-pixel in the second sub-pixel row 32 is the second color sub-pixel 11b. At this time, the capacitance value of the pixel capacitance of the maximum capacitance sub-pixel (such as Figure 9 the first color sub-pixel 11a in Figure 9 ) in the first sub-pixel row 31 is greater than the capacitance value of the pixel capacitance of the maximum capacitance sub-pixel (such as

[0103] the second color sub-pixel 11b in Figure 9 ) in the second sub-pixel row 32. Figure 9 the second color sub-pixel 11b in

[0104] It can be understood that in order to enable the first sub-pixel row 31 to complete the charging process of the pixel capacitance of the light-emitting element 112 in all sub-pixels 11 in this row within the first light-emitting sub-stage T31, it is necessary to set the delay time △t corresponding to the first sub-pixel row 31 to be greater than or equal to the charging time required for the pixel capacitance of the light-emitting element 112 of the maximum capacitance sub-pixel in the first sub-pixel row 31 (such as Figure 9 the charging time required for the pixel capacitance of the light-emitting element 112 in the first color sub-pixel 11a in Figure 9 ), and set the delay time △t corresponding to the second sub-pixel row 32 to be greater than or equal to the charging time required for the pixel capacitance of the light-emitting element 112 of the maximum capacitance sub-pixel in the second sub-pixel row 32 (such as Figure 9 the charging time required for the pixel capacitance of the light-emitting element 112 in the second color sub-pixel 11b in

[0104] ). Figure 9 the first color sub-pixel 11a in Figure 9 ) and the capacitance value of the pixel capacitance of the maximum capacitance sub-pixel (such asFigure 9 the capacitance value of the pixel capacitor of the second color sub-pixel 11b) in Figure 9 such that the charging time required for the pixel capacitor of the light-emitting element 112 of the maximum capacitance sub-pixel in the first sub-pixel row 31 (e.g., Figure 9 the charging time required for the pixel capacitor of the light-emitting element 112 in the first color sub-pixel 11a in

[0105] Therefore, in this embodiment, as Figure 10 and Figure 11 shown, the delay time Δt corresponding to the first sub-pixel row 31 is set to be larger, so as to ensure that the delay time Δt corresponding to the first sub-pixel row 31 is greater than or equal to the charging time required for the pixel capacitor of the light-emitting element 112 of the maximum capacitance sub-pixel in the first sub-pixel row 31 (e.g., Figure 9 the charging time required for the pixel capacitor of the light-emitting element 112 in the first color sub-pixel 11a in

[0106] At the same time, the delay time Δt corresponding to the second sub-pixel row 32 is set to be smaller. While ensuring that the delay time Δt corresponding to the second sub-pixel row 32 is greater than or equal to the charging time required for the pixel capacitor of the light-emitting element 112 of the maximum capacitance sub-pixel in the second sub-pixel row 32 (e.g., Figure 9 the charging time required for the pixel capacitor of the light-emitting element 112 in the second color sub-pixel 11b in

[0107] Figure 12 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as Figures 9 - 12As shown, optionally, the first sub-pixel row 31 and the second sub-pixel row 32 are alternately arranged in the column direction. The multiple sub-pixels 11 include a first-color sub-pixel 11a, a second-color sub-pixel 11b, and a third-color sub-pixel 11c. The capacitance value of the pixel capacitor of the light-emitting element 112 in the first-color sub-pixel 11a is greater than the capacitance value of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b, and the capacitance value of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b is greater than the capacitance value of the pixel capacitor of the light-emitting element 112 in the third-color sub-pixel 11c. The first sub-pixel row 31 includes the first-color sub-pixel 11a and the second-color sub-pixel 11b, and the second sub-pixel row 32 includes the second-color sub-pixel 11b and the third-color sub-pixel 11c; alternatively, the first sub-pixel row 31 includes the first-color sub-pixel 11a and the third-color sub-pixel 11c, and the second sub-pixel row 32 includes the second-color sub-pixel 11b and the third-color sub-pixel 11c. Wherein, the delay time Δt corresponding to the first sub-pixel row 31 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the first-color sub-pixel 11a, and the delay time Δt corresponding to the second sub-pixel row 32 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b.

[0108] Exemplarily, as Figure 9 shown, the first sub-pixel row 31 and the second sub-pixel row 32 are alternately arranged in the column direction. The first sub-pixel row 31 may be formed by alternately arranging the first-color sub-pixel 11a and the second-color sub-pixel 11b in the row direction, and the second sub-pixel row 32 may be formed by alternately arranging the second-color sub-pixel 11b and the third-color sub-pixel 11c in the row direction. At the same time, the emission colors of two adjacent sub-pixels 11 in the column direction are different. For example, in Figure 9 it, the second-color sub-pixel 11b and the third-color sub-pixel 11c are alternately arranged in the column direction, and the first-color sub-pixel 11a and the second-color sub-pixel 11b are alternately arranged in the column direction.

[0109] At this time, as Figure 9 shown, a 2×2 sub-pixel matrix formed by two adjacent second-color sub-pixels 11b, one first-color sub-pixel 11a, and one third-color sub-pixel 11c can form a pixel repeating unit 10. When displaying, the second-color sub-pixel 11b can obtain the brightness by borrowing the brightness of each sub-pixel adjacent to it and having a different emission color from it. Through the above pixel arrangement and pixel borrowing technology (Pixel Rendering), by borrowing the brightness of surrounding sub-pixels, the display panel can achieve a higher resolution with a smaller number of sub-pixels 11.

[0110] Similarly, as Figure 12As shown, exemplarily, the first sub-pixel row 31 and the second sub-pixel row 32 are arranged alternately in the column direction. The first sub-pixel row 31 can be composed of the first color sub-pixels 11a and the third color sub-pixels 11c arranged alternately in the row direction, and the second sub-pixel row 32 can be composed of the second color sub-pixels 11b and the third color sub-pixels 11c arranged alternately in the row direction. At the same time, the emission colors of two adjacent sub-pixels 11 in the column direction are different. For example, in Figure 12 the first color sub-pixels 11a and the third color sub-pixels 11c are arranged alternately in the column direction, and the second color sub-pixels 11b and the third color sub-pixels 11c are arranged alternately in the column direction.

[0111] At this time, as Figure 12 shown, a 2×2 sub-pixel matrix formed by two adjacent third color sub-pixels 11c, one first color sub-pixel 11a and one second color sub-pixel 11b can form a pixel repeating unit 10. When displaying, the third color sub-pixels 11c can obtain the brightness by borrowing the brightness of each sub-pixel adjacent to it and having a different emission color from it. Through the above pixel arrangement and pixel borrowing technology (Pixel Rendering), by borrowing the brightness of surrounding sub-pixels, the display panel can achieve a higher resolution with a smaller number of sub-pixels 11.

[0112] In this embodiment, the maximum capacitance sub-pixel in the first sub-pixel row 31 is the first color sub-pixel 11a. By setting the delay time Δt corresponding to the first sub-pixel row 31 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the first color sub-pixel 11a, it can be ensured that the first sub-pixel row 31 completes the charging process of the pixel capacitance of the light-emitting element 112 in all sub-pixels 11 in this row within the first light-emitting sub-stage T31; the maximum capacitance sub-pixel in the second sub-pixel row 32 is the second color sub-pixel 11b. By setting the delay time Δt corresponding to the second sub-pixel row 32 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the second color sub-pixel 11b, it can be ensured that the second sub-pixel row 32 completes the charging process of the pixel capacitance of the light-emitting element 112 in all sub-pixels 11 in this row within the first light-emitting sub-stage T31, so as to ensure that all sub-pixels 11 in each row can emit light simultaneously when the cathode switching transistor M0 corresponding to the sub-pixels 11 in this row is turned on, making the emission durations of the light-emitting elements 112 emitting different colors of light in the same row of sub-pixels 11 consistent during the light-emitting stage T3, so that the light-emitting efficiencies of the light-emitting elements 112 tend to be consistent, and solving the color cast problem caused by the difference in pixel capacitance among the light-emitting elements 112 emitting different colors of light.

[0113] At the same time, as Figure 10 and Figure 11As shown, by setting the delay time Δt corresponding to the second sub-pixel row 32 to be less than the delay time Δt corresponding to the first sub-pixel row 31, while solving the color cast problem caused by the difference in pixel capacitance in the light-emitting elements 112 that emit different colors of light, the light-emitting duration of the light-emitting elements 112 of the sub-pixels 11 in the second sub-pixel row 32 during the light-emitting stage T3 can be increased, thereby improving the light-emitting efficiency of the sub-pixels 11 in the second sub-pixel row 32. Furthermore, a smaller operating current density can be adopted under the condition of achieving the same brightness, which helps to extend the service life of the sub-pixels 11 in the second sub-pixel row 32.

[0114] Figure 13 FIG. [4] is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 14 FIG. [5] is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 15 FIG. [6] is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as Figures 13 - 15 Note: The numbers in brackets in the translation of , , and should be filled with the corresponding figure numbers in the original Chinese text. Since the original text doesn't provide specific figure numbers, they are left as placeholders here.As shown, optionally, the first sub-pixel row 31 and the second sub-pixel row 32 are alternately arranged in the column direction. The multiple sub-pixels 11 include a first-color sub-pixel 11a, a second-color sub-pixel 11b, and a third-color sub-pixel 11c. The capacitance value of the pixel capacitor of the light-emitting element 112 in the first-color sub-pixel 11a is greater than the capacitance value of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b, and the capacitance value of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b is greater than the capacitance value of the pixel capacitor of the light-emitting element 112 in the third-color sub-pixel 11c. The first sub-pixel row 31 includes the first-color sub-pixel 11a and the second-color sub-pixel 11b, and the second sub-pixel row 32 includes the third-color sub-pixel 11c. The delay time Δt corresponding to the first sub-pixel row 31 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the first-color sub-pixel 11a, and the delay time Δt corresponding to the second sub-pixel row 32 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the third-color sub-pixel 11c. Alternatively, the first sub-pixel row 31 includes the first-color sub-pixel 11a and the third-color sub-pixel 11c, the second sub-pixel row 32 includes the second-color sub-pixel 11b, the delay time Δt corresponding to the first sub-pixel row 31 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the first-color sub-pixel 11a, and the delay time Δt corresponding to the second sub-pixel row 32 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b. Alternatively, the first sub-pixel row 31 includes the first-color sub-pixel 11a, the second sub-pixel row 32 includes the second-color sub-pixel 11b and the third-color sub-pixel 11c, the delay time Δt corresponding to the first sub-pixel row 31 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the first-color sub-pixel 11a, and the delay time Δt corresponding to the second sub-pixel row 32 is greater than or equal to the charging time of the pixel capacitor of the light-emitting element 112 in the second-color sub-pixel 11b.

[0115] Exemplarily, as Figure 13 shown, the first sub-pixel row 31 and the second sub-pixel row 32 are alternately arranged in the column direction. The first sub-pixel row 31 may be composed of the first-color sub-pixel 11a and the second-color sub-pixel 11b alternately arranged in the row direction, and the second sub-pixel row 32 may be composed of multiple third-color sub-pixels 11c arranged in the row direction. Among them, the adjacent first-color sub-pixel 11a, second-color sub-pixel 11b, and third-color sub-pixel 11c may form a pixel repeating unit 10. In a pixel repeating unit 10, in the column direction, the third-color sub-pixel 11c located in the second sub-pixel row 32 may at least partially overlap with the first-color sub-pixel 11a and the second-color sub-pixel 11b located in the first sub-pixel row 31. This arrangement makes the arrangement of the three pixels in the same pixel repeating unit 10 more compact. Compared withFigure 1 The arrangement in which the first color sub-pixel 11a, the second color sub-pixel 11b, and the third color sub-pixel 11c are arranged in the same row is conducive to improving the aperture ratio and the screen-to-body ratio of the display panel, and thus is conducive to improving the display quality.

[0116] In this embodiment, as Figure 10 , Figure 11 and Figure 13 shown, the maximum capacitance sub-pixel in the first sub-pixel row 31 is the first color sub-pixel 11a. By setting the delay time Δt corresponding to the first sub-pixel row 31 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the first color sub-pixel 11a, it can be ensured that the first sub-pixel row 31 completes the charging process of the pixel capacitances of the light-emitting elements 112 in all sub-pixels 11 in this row during the first light-emitting sub-stage T31; the maximum capacitance sub-pixel in the second sub-pixel row 32 is the third color sub-pixel 11c. By setting the delay time Δt corresponding to the second sub-pixel row 32 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the third color sub-pixel 11c, it can be ensured that the second sub-pixel row 32 completes the charging process of the pixel capacitances of the light-emitting elements 112 in all sub-pixels 11 in this row during the first light-emitting sub-stage T31, so as to ensure that all sub-pixels 11 in each row can emit light simultaneously when the cathode switching transistor M0 corresponding to the sub-pixels 11 in this row is turned on, so that the light-emitting elements 112 emitting different color lights in the same row of sub-pixels 11 have the same light-emitting duration during the light-emitting stage T3, so that the light-emitting efficiency of the light-emitting elements 112 tends to be consistent, and the color cast problem caused by the difference in pixel capacitance in the light-emitting elements 112 emitting different color lights is solved.

[0117] In another embodiment, as Figure 14 shown, the first sub-pixel row 31 and the second sub-pixel row 32 are alternately arranged in the column direction. The first sub-pixel row 31 may be composed of the first color sub-pixel 11a and the third color sub-pixel 11c alternately arranged in the row direction, and the second sub-pixel row 32 may be composed of a plurality of second color sub-pixels 11b arranged in the row direction. Among them, the adjacent first color sub-pixel 11a, second color sub-pixel 11b, and third color sub-pixel 11c may form a pixel repeating unit 10. In a pixel repeating unit 10, in the column direction, the second color sub-pixel 11b located in the second sub-pixel row 32 may at least partially overlap with the first color sub-pixel 11a and the third color sub-pixel 11c located in the first sub-pixel row 31. This arrangement makes the arrangement of the three pixels in the same pixel repeating unit 10 more compact. Compared with Figure 1 the arrangement in which the first color sub-pixel 11a, the second color sub-pixel 11b, and the third color sub-pixel 11c are arranged in the same row, it is conducive to improving the aperture ratio and the screen-to-body ratio of the display panel, and thus is conducive to improving the display quality.

[0118] In this embodiment, as Figure 10 , Figure 11 and Figure 14 shown, the maximum capacitance sub-pixel in the first sub-pixel row 31 is the first color sub-pixel 11a. By setting the delay time Δt corresponding to the first sub-pixel row 31 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the first color sub-pixel 11a, it can be ensured that the first sub-pixel row 31 completes the charging process of the pixel capacitances of all the sub-pixels 11 in this row for the light-emitting element 112 within the first light-emitting sub-phase T31; the maximum capacitance sub-pixel in the second sub-pixel row 32 is the second color sub-pixel 11b. By setting the delay time Δt corresponding to the second sub-pixel row 32 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the second color sub-pixel 11b, it can be ensured that the second sub-pixel row 32 completes the charging process of the pixel capacitances of all the sub-pixels 11 in this row for the light-emitting element 112 within the first light-emitting sub-phase T31, so as to ensure that all the sub-pixels 11 in each row can emit light simultaneously when the cathode switching transistor M0 corresponding to the sub-pixels 11 in this row is turned on, making the light-emitting durations of the light-emitting elements 112 emitting different color lights in the same row of sub-pixels 11 consistent during the light-emitting phase T3, so that the light-emitting efficiencies of the light-emitting elements 112 tend to be consistent, and solving the color cast problem caused by the differences in pixel capacitances among the light-emitting elements 112 emitting different color lights.

[0119] In another embodiment, as Figure 15 shown, the first sub-pixel row 31 and the second sub-pixel row 32 are arranged alternately in the column direction. The first sub-pixel row 31 can be composed of a plurality of first color sub-pixels 11a arranged in the row direction, and the second sub-pixel row 32 can be composed of the second color sub-pixels 11b and the third color sub-pixels 11c arranged alternately in the row direction. Among them, the adjacent first color sub-pixel 11a, second color sub-pixel 11b, and third color sub-pixel 11c can form a pixel repeating unit 10. In a pixel repeating unit 10, in the column direction, the first color sub-pixel 11a located in the first sub-pixel row 31 can at least partially overlap with the second color sub-pixel 11b and the third color sub-pixel 11c located in the second sub-pixel row 32. This arrangement makes the arrangement of the three pixels in the same pixel repeating unit 10 more compact. Compared with Figure 1 the way where the first color sub-pixel 11a, second color sub-pixel 11b, and third color sub-pixel 11c are arranged in the same row in

[0120] In this embodiment, as Figure 10 , Figure 11 and Figure 15As shown, the sub-pixel with the largest capacitance in the first sub-pixel row 31 is the first color sub-pixel 11a. By setting the delay time Δt corresponding to the first sub-pixel row 31 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the first color sub-pixel 11a, it can be ensured that the first sub-pixel row 31 completes the charging process of the pixel capacitance of the light-emitting element 112 in all sub-pixels 11 in this row within the first light-emitting sub-phase T31; the sub-pixel with the largest capacitance in the second sub-pixel row 32 is the second color sub-pixel 11b. By setting the delay time Δt corresponding to the second sub-pixel row 32 to be greater than or equal to the charging time of the pixel capacitance of the light-emitting element 112 in the second color sub-pixel 11b, it can be ensured that the second sub-pixel row 32 completes the charging process of the pixel capacitance of the light-emitting element 112 in all sub-pixels 11 in this row within the first light-emitting sub-phase T31, thereby ensuring that all sub-pixels 11 in each row can emit light simultaneously when the cathode switching transistor M0 corresponding to the sub-pixels 11 in this row is turned on, so that the light-emitting elements 112 emitting different colors of light in the same row of sub-pixels 11 have the same light-emitting duration during the light-emitting phase T3, making the light-emitting efficiency of the light-emitting element 112 tend to be consistent, and solving the color cast problem caused by the difference in pixel capacitance among the light-emitting elements 112 emitting different colors of light.

[0121] Meanwhile, as Figure 10 and Figure 11 shown, in the display panel shown in Figures 13 - 15 it is possible to set the delay time Δt corresponding to the second sub-pixel row 32 to be less than the delay time Δt corresponding to the first sub-pixel row 31. While solving the color cast problem caused by the difference in pixel capacitance among the light-emitting elements 112 emitting different colors of light, it is possible to increase the light-emitting duration of the light-emitting element 112 of the sub-pixel 11 in the second sub-pixel row 32 during the light-emitting phase T3, thereby improving the light-emitting efficiency of the sub-pixel 11 in the second sub-pixel row 32. Furthermore, it is possible to use a smaller operating current density under the condition of achieving the same brightness, which helps to extend the service life of the sub-pixel 11 in the second sub-pixel row 32.

[0122] It should be noted that in the above embodiments, only several exemplary setting methods of the delay time Δt corresponding to each row of sub-pixels 11 in several pixel arrangement methods are described, but it is not limited to the above embodiments. It can be understood that those skilled in the art can adjust the delay time Δt corresponding to each row of sub-pixels 11 according to the specific pixel arrangement method to achieve the results expected by the technical solution of the present invention.

[0123] Continuing to refer to Figure 1 and Figure 9 and Figures 12 - 15 optionally, the first color sub-pixel 11a is a green sub-pixel G, the second color sub-pixel 11b is a red sub-pixel R, and the third color sub-pixel 11c is a blue sub-pixel B.

[0124] Among them, the inventor further found through research that the capacitance value of the pixel capacitor of the light-emitting element 112 in the green sub-pixel G is greater than that of the pixel capacitor of the light-emitting element 112 in the red sub-pixel R, and the capacitance value of the pixel capacitor of the light-emitting element 112 in the red sub-pixel R is greater than that of the pixel capacitor of the light-emitting element 112 in the blue sub-pixel B. Thus, in the light-emitting stage T3, the time required for the blue sub-pixel B to charge the pixel capacitor of the light-emitting element 112 is shorter, and the time required for the green sub-pixel G to charge the pixel capacitor of the light-emitting element 112 is longer. Then, within the limited duration of the light-emitting stage T3 in one frame, the light-emitting duration of the light-emitting element 112 in the blue sub-pixel B is longer, and the light-emitting duration of the light-emitting element 112 in the green sub-pixel G is shorter, resulting in a higher light-emitting efficiency of the blue sub-pixel B and a lower light-emitting efficiency of the green sub-pixel G at low gray levels, and the image is bluish.

[0125] Therefore, in any of the above embodiments, by setting the green sub-pixel G as the first color sub-pixel 11a, the red sub-pixel R as the second color sub-pixel 11b, and the blue sub-pixel B as the third color sub-pixel 11c, the color cast problem caused by the capacitance values of the pixel capacitors of the light-emitting elements 112 in the green sub-pixel G, red sub-pixel R, and blue sub-pixel B decreasing in sequence can be solved.

[0126] It should be noted that the capacitance value of the pixel capacitor of the light-emitting element 112 depends on the material of the light-emitting layer 22 in the light-emitting element 112. Therefore, when other material systems are used for the light-emitting layers 22 of the light-emitting elements 112 in the green sub-pixel G, red sub-pixel R, and blue sub-pixel B, the capacitance values of the pixel capacitors of the light-emitting elements 112 in the green sub-pixel G, red sub-pixel R, and blue sub-pixel B may show a size relationship different from that in this embodiment, so that the green sub-pixel G, red sub-pixel R, and blue sub-pixel B have different corresponding relationships with the first color sub-pixel 11a, second color sub-pixel 11b, and third color sub-pixel 11c in the above embodiment, which will not be elaborated here.

[0127] Figure 16 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as Figure 16 shown. Optionally, the display panel provided by the embodiment of the present invention includes a display area 40 and a non-display area 41 located on at least one side of the display area 40. The non-display area 41 includes a first scan driving circuit 42 and a second scan driving circuit 43. The first light-emitting control signal line EM1 is electrically connected to the first scan driving circuit 42, and the second light-emitting control signal line EM2 is electrically connected to the second scan driving circuit 43.

[0128] Specifically, as Figure 16As shown, the first scan driving circuit 42 and the second scan driving circuit 43 are disposed in the non-display area 41 to prevent the first scan driving circuit 42 and the second scan driving circuit 43 from affecting the image display in the display area 40. Among them, the first scan driving circuit 42 is configured to sequentially provide a first light emission control signal Emit1 to each row of first light emission control signal lines EM1, thereby controlling the light emission control transistor M16 of the pixel driving circuit 111 in each row of sub-pixels 11 to conduct. The second scan driving circuit 43 is configured to provide a second light emission control signal Emit2 to each row of second light emission control signal lines EM2, thereby controlling the cathode switching transistor M0 of the pixel driving circuit 111 in each row of sub-pixels 11 to conduct.

[0129] In this embodiment, the first light emission control signal Emit1 of the first light emission control signal line EM1 and the second light emission control signal Emit2 of the second light emission control signal line EM2 are respectively provided by two different scan driving circuits (such as Figure 16 the first scan driving circuit 42 and the second scan driving circuit 43 in), and the conduction time of the light emission control transistor M16 and the conduction time of the cathode switching transistor M0 of each row of pixel driving circuits 111 can be independently controlled by the two different scan driving circuits, so that the delay time Δt corresponding to each row of sub-pixels 11 can be flexibly adjusted according to the specific capacitance value of the pixel capacitance of the light emitting element 112 in the sub-pixels 11 that emit different colors of light, so that the delay time Δt corresponding to each row of sub-pixels 11 has a large adjustable range, and thus it can be applied to light emitting elements 112 of various different material systems.

[0130] Continue to refer to Figure 16 , optionally, the first scan driving circuit 42 and the second scan driving circuit 43 can be located on different sides of the display area 40, which can reduce the width of the unilateral border, thereby facilitating the narrow border design of the display panel.

[0131] Figure 17 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as shown in Figure 17As shown, optionally, the first scan driving circuit 42 and the second scan driving circuit 43 may also be located on the same side of the display area 40. At this time, the first light emission control signal Emit1 provided by the first scan driving circuit 42 and the second light emission control signal Emit2 provided by the second scan driving circuit 43 are both transmitted from the same side of the display area 40 to the light emission control transistor M16 and the cathode switch transistor M0 at each position in the same row of the pixel driving circuit 111, so that the time difference (i.e., the delay time Δt, or in other words, the duration of the first light emission sub-phase T31) of the first light emission control signal Emit1 and the second light emission control signal Emit2 received by the pixel driving circuit 111 at each position in the same row can be kept consistent, ensuring that the duration of light emission of the sub-pixels 11 in the same row during the light emission phase T3 is consistent, and the light emission efficiency of the light emitting elements 112 is more consistent, further improving the color shift problem.

[0132] Figure 18 A schematic structural diagram of another display panel provided by an embodiment of the present invention is shown in Figure 18 As shown, optionally, the delay time Δt corresponding to each row of sub-pixels 11 is equal. The display panel includes N rows of sub-pixels 11. The first scan driving circuit 42 includes N cascaded first shift registers 421, and the second scan driving circuit 43 includes N cascaded second shift registers 431. The first light emission control signal line EM1 corresponding to the i-th row of sub-pixels 11 is electrically connected to the i-th first shift register 421, and the second light emission control signal line EM2 corresponding to the i-th row of sub-pixels 11 is electrically connected to the i-th second shift register 431, where 1 ≤ i ≤ N and i is a positive integer.

[0133] Exemplarily, as Figure 18As shown, taking N = 6 as an example for illustration, the display panel includes 6 rows of sub-pixels 11. The first scan driving circuit 42 includes 6 cascaded first shift registers 421, and the 6 first shift registers 421 are electrically connected to 6 first light emission control signal lines EM1 corresponding to the 6 rows of sub-pixels 11 one by one. Within one frame time, the first shift register 421 of the first stage outputs a first light emission control signal Emit1 to the first light emission control signal line EM1 of the first row, so that the light emission control transistor M16 of the pixel driving circuit 111 in the first row of sub-pixels 11 is turned on. At the same time, the first light emission control signal Emit1 output by the first shift register 421 of the first stage also serves as the shift control signal for the second shift register 421 of the second stage. That is, when the first shift register 421 of the first stage outputs the first light emission control signal Emit1 to the first light emission control signal line EM1 of the first row, it outputs a shift control signal to the second shift register 421 of the second stage. Then, under the drive of the shift control signal, the second shift register 421 of the second stage outputs the first light emission control signal Emit1 to the second light emission control signal line EM1, so that the light emission control transistor M16 of the pixel driving circuit 111 in the second row of sub-pixels 11 is turned on, and at the same time, it outputs a shift control signal to the third shift register 421 of the third stage,... and so on. Under the drive of the shift control signal, the first shift register 421 of the Nth stage outputs the first light emission control signal Emit1 to the Nth light emission control signal line EM1, so that the light emission control transistor M16 of the pixel driving circuit 111 in the Nth row of sub-pixels 11 is turned on, realizing the progressive turn-on of the light emission control transistors M16 in the N rows of sub-pixels 11.

[0134] Similarly, continue to refer to Figure 18, the second scan driving circuit 43 includes six cascaded second shift registers 431, and the six second shift registers 431 are electrically connected to six second light emission control signal lines EM2 corresponding to the six rows of sub-pixels 11 one by one. During one frame time, the first-stage second shift register 431 outputs a second light emission control signal Emit2 to the first second light emission control signal line EM2, so that the cathode switching transistor M0 corresponding to the first row of sub-pixels 11 is turned on. At the same time, the second light emission control signal Emit2 output by the first-stage second shift register 431 also serves as the shift control signal of the second-stage second shift register 431, that is, when the first-stage second shift register 431 outputs the second light emission control signal Emit2 to the first second light emission control signal line EM2, it outputs a shift control signal to the second-stage second shift register 431. Then, the second-stage second shift register 431 outputs the second light emission control signal Emit2 to the second second light emission control signal line EM2 under the drive of the shift control signal, so that the cathode switching transistor M0 corresponding to the second row of sub-pixels 11 is turned on, and at the same time, it outputs a shift control signal to the third-stage second shift register 431, ……, and so on. The Nth-stage second shift register 431 outputs the second light emission control signal Emit2 to the Nth second light emission control signal line EM2 under the drive of the shift control signal, so that the cathode switching transistor M0 corresponding to the Nth row of sub-pixels 11 is turned on, realizing the sequential turn-on of the cathode switching transistors M0 corresponding to the N rows of sub-pixels 11.

[0135] Among them, the turn-on time of the light emission control transistor M16 and the turn-on time of the cathode switching transistor M0 of each row of pixel driving circuits 111 can be independently controlled by the first scan driving circuit 42 and the second scan driving circuit 43 respectively. Thus, the delay time △t corresponding to each row of sub-pixels 11 can be flexibly adjusted according to the specific capacitance value of the pixel capacitor of the light emitting element 112 in the sub-pixels 11 emitting different colors of light, so that the delay time △t corresponding to each row of sub-pixels 11 has a large settable range, and thus it can be applicable to light emitting elements 112 of various different material systems.

[0136] It should be noted that when the delay time △t corresponding to each row of sub-pixels 11 is equal, only one set of N cascaded first shift registers 421 is needed to realize the output of the first light emission control signal Emit1. Similarly, only one set of N cascaded second shift registers 431 is needed to realize the output of the second light emission control signal Emit2. In this way, the sequential turn-on of the light emission control transistors M16 in the N rows of sub-pixels 11 and the sequential turn-on of the cathode switching transistors M0 corresponding to the N rows of sub-pixels 11 can be realized by using fewer shift registers, which can reduce the frame width and is beneficial to the narrow frame design of the display panel.

[0137] In addition, in practical applications, the display panel has more rows of sub-pixels 11, that is, N can have a larger value, wherein the value of N is related to the size and resolution of the display panel and can be set according to actual needs, which will not be repeated in subsequent embodiments.

[0138] Figure 19 A structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 19 As shown, optionally, the delay time △t corresponding to each row of sub-pixels 11 is equal. The display panel includes N rows of sub-pixels 11, the first scan drive circuit 42 and the second scan drive circuit 43 are the same scan drive circuit, the scan drive circuit includes N cascaded third shift registers 400, the first light control signal line EM1 corresponding to the i-th row of sub-pixels 11 is electrically connected to the i-th stage third shift register 400, the first light control signal line EM1 corresponding to the N-th row of sub-pixels 11 is electrically connected to the N-th stage third shift register 400, the second light control signal line EM2 corresponding to the i-th row of sub-pixels 11 is electrically connected to the i+1-th stage third shift register 400, and the second light control signal line EM2 corresponding to the N-th row of sub-pixels 11 is electrically connected to the 1st stage third shift register 400, wherein 1≤i≤N-1, and i is a positive integer.

[0139] For example, Figure 19 As shown, taking N=6 as an example, the display panel includes 6 rows of sub-pixels 11, the first scan drive circuit 42 and the second scan drive circuit 43 are the same scan drive circuit, that is, the first scan drive circuit 42 and the second scan drive circuit 43 share the same set of 6 cascaded third shift registers 400, the 6 third shift registers 400 are electrically connected to the 6 first light-emitting control signal lines EM1 corresponding to the 6 rows of sub-pixels 11, and the 6 third shift registers 400 are electrically connected to the 6 second light-emitting control signal lines EM2 corresponding to the 6 rows of sub-pixels 11, the first light-emitting control signal line EM1 corresponding to each row of sub-pixels 11 is electrically connected to the third shift register 400 of this level, the second light-emitting control signal line EM2 corresponding to the 1st to N-1st rows of sub-pixels 11 is electrically connected to the third shift register 400 of the next level, and the second light-emitting control signal line EM2 corresponding to the Nth row of sub-pixels 11 is electrically connected to the third shift register 400 of the 1st level.

[0140] Within one frame time, the first-stage third shift register 400 outputs a first light emission control signal Emit1 to the first light emission control signal line EM1 of the first row, so that the light emission control transistor M16 of the pixel driving circuit 111 in the first row of sub-pixels 11 is turned on. Then, under the drive of the first light emission control signal Emit1 (i.e., the shift control signal) output by the first-stage third shift register 400, the second-stage third shift register 400 outputs the first light emission control signal Emit1 to the first light emission control signal line EM1 of the second row, so that the light emission control transistor M16 of the pixel driving circuit 111 in the second row of sub-pixels 11 is turned on. At the same time, the first light emission control signal Emit1 output by the second-stage third shift register 400 also serves as the second light emission control signal Emit2 transmitted by the first light emission control signal line EM2 of the first row. That is, while the second-stage third shift register 400 outputs the first light emission control signal Emit1 to the first light emission control signal line EM1 of the second row, it outputs the second light emission control signal Emit2 to the first light emission control signal line EM2 of the first row, so that the cathode switching transistor M0 connected to the first row of sub-pixels 11 is turned on,... and so on. Under the drive of the first light emission control signal Emit1 (i.e., the shift control signal) output by the (N - 1)-stage third shift register 400, the N-stage third shift register 400 outputs the first light emission control signal Emit1 to the first light emission control signal line EM1 of the Nth row, so that the light emission control transistor M16 of the pixel driving circuit 111 in the Nth row of sub-pixels 11 is turned on. At the same time, it outputs the second light emission control signal Emit2 to the first light emission control signal line EM2 of the (N - 1)th row, so that the cathode switching transistor M0 connected to the (N - 1)th row of sub-pixels 11 is turned on.

[0141] It should be noted that the second light emission control signal line EM2 corresponding to the Nth row of sub-pixels 11 is electrically connected to the first-stage third shift register 400. That is, while the first-stage third shift register 400 outputs the first light emission control signal Emit1 to the first light emission control signal line EM1 of the first row, so that the light emission control transistor M16 of the pixel driving circuit 111 in the first row of sub-pixels 11 is turned on, it outputs the second light emission control signal Emit2 to the first light emission control signal line EM2 of the Nth row, so that the cathode switching transistor M0 connected to the Nth row of sub-pixels 11 is turned on. In this way, the row-by-row turn-on of the light emission control transistors M16 in the N rows of sub-pixels 11 and the row-by-row turn-on of the cathode switching transistors M0 connected to the N rows of sub-pixels 11 are realized.

[0142] In this embodiment, when the delay time Δt corresponding to each row of sub-pixels 11 is equal, only one set of N cascaded third shift registers 400 is required to output the first light emission control signal Emit1 and the second light emission control signal Emit2. In this way, the row-by-row turn-on of the light emission control transistors M16 in the N rows of sub-pixels 11 and the row-by-row turn-on of the cathode switch transistors M0 connected to the N rows of sub-pixels 11 can be achieved with fewer shift registers, thereby further reducing the border width and facilitating the narrow border design of the display panel.

[0143] Figure 20 FIG. is a schematic structural diagram of another display panel provided by an embodiment of the present invention, as Figure 20 shown. Optionally, the multiple sub-pixels 11 include a first sub-pixel row 31 and a second sub-pixel row 32. The light-emitting colors of the maximum-capacitance sub-pixels in the first sub-pixel row 31 and the second sub-pixel row 32 are different, and the capacitance value of the pixel capacitance of the maximum-capacitance sub-pixel in the first sub-pixel row 31 is greater than the capacitance value of the pixel capacitance of the maximum-capacitance sub-pixel in the second sub-pixel row 32. The delay time Δt corresponding to the first sub-pixel row 31 is greater than the delay time Δt corresponding to the second sub-pixel row 32. The second light emission control signal line EM2 includes a first sub-light emission control signal line EM21 and a second sub-light emission control signal line EM22. The gate of the cathode switch transistor M0 corresponding to the first sub-pixel row 31 is electrically connected to the first sub-light emission control signal line EM21, and the gate of the cathode switch transistor M0 corresponding to the second sub-pixel row 32 is electrically connected to the second sub-light emission control signal line EM22. The second scan driving circuit 43 includes a first sub-scan circuit 51 and a second sub-scan circuit 52. The first sub-scan circuit 51 is electrically connected to the first sub-light emission control signal line EM21, and the second sub-scan circuit 52 is electrically connected to the second sub-light emission control signal line EM22.

[0144] Among them, in a row of sub-pixels 11, the sub-pixel 11 with the largest capacitance value of the pixel capacitance of the light-emitting element 112 is the maximum-capacitance sub-pixel in that row of sub-pixels 11.

[0145] As described above, when the emission colors of the maximum capacitance sub-pixels in the first sub-pixel row 31 and the maximum capacitance sub-pixels in the second sub-pixel row 32 are different, and the capacitance value of the pixel capacitance of the maximum capacitance sub-pixel in the first sub-pixel row 31 is greater than the capacitance value of the pixel capacitance of the maximum capacitance sub-pixel in the second sub-pixel row 32, the delay time Δt corresponding to the first sub-pixel row 31 can be set to be greater than the delay time Δt corresponding to the second sub-pixel row 32. While ensuring that the charging process of the pixel capacitance of the light-emitting element 112 in the first sub-pixel row 31 is completed within the first light-emitting sub-phase T31, the light-emitting duration of the light-emitting element 112 of the sub-pixel 11 in the second sub-pixel row 32 during the light-emitting phase T3 can be made longer than the light-emitting duration of the light-emitting element 112 of the sub-pixel 11 in the first sub-pixel row 31. Thus, the light-emitting efficiency of the sub-pixel 11 in the second sub-pixel row 32 can be improved, and then a smaller operating current density can be adopted under the condition of achieving the same brightness, which helps to extend the service life of the sub-pixel 11 in the second sub-pixel row 32.

[0146] Continue to refer to Figure 20 , when the delay time Δt corresponding to the first sub-pixel row 31 is different from the delay time Δt corresponding to the second sub-pixel row 32, the second scan driving circuit 43 is set to include two sub-scan circuits, namely the first sub-scan circuit 51 and the second sub-scan circuit 52. Among them, the first sub-scan circuit 51 is electrically connected to the gate of the cathode switching transistor M0 corresponding to the first sub-pixel row 31 through the first sub-light-emitting control signal line EM21, so that the first sub-scan circuit 51 sequentially provides the second light-emitting control signal Emit2 for each first sub-pixel row 31, thereby controlling the cathode switching transistor M0 corresponding to each first sub-pixel row 31 to conduct; the second sub-scan circuit 52 is electrically connected to the gate of the cathode switching transistor M0 corresponding to the second sub-pixel row 32 through the second sub-light-emitting control signal line EM22, so that the second sub-scan circuit 52 sequentially provides the second light-emitting control signal Emit2 for each second sub-pixel row 32, thereby controlling the cathode switching transistor M0 corresponding to each second sub-pixel row 32 to conduct.

[0147] Among them, the second light-emitting control signal Emit2 received by the cathode switching transistor M0 corresponding to the first sub-pixel row 31 and the second light-emitting control signal Emit2 received by the cathode switching transistor M0 corresponding to the second sub-pixel row 32 are respectively passed through two independent sub-scan circuits (such as Figure 20It is provided by the first sub-scanning circuit 51 and the second sub-scanning circuit 52 in []. The conduction time of the cathode switching transistor M0 corresponding to the first sub-pixel row 31 and the second sub-pixel row 32 can be independently controlled by two different sub-scanning circuits respectively. Thus, the delay time Δt corresponding to the first sub-pixel row 31 and the second sub-pixel row 32 can be flexibly adjusted according to different pixel arrangements, so that the first sub-pixel row 31 and the second sub-pixel row 32 have different delay times Δt.

[0148] Continue to refer to Figure 20 , Exemplarily, the first sub-scanning circuit 51 may include a plurality of cascaded fourth shift registers 511. The number of the fourth shift registers 511 is the same as the number of the first sub-pixel rows 31, and the plurality of fourth shift registers 511 are electrically connected to the plurality of first sub-light emission control signal lines EM21 corresponding to the connection of the multiple rows of the first sub-pixel rows 31 one by one. The second sub-scanning circuit 52 may include a plurality of cascaded fifth shift registers 521. The number of the fifth shift registers 521 is the same as the number of the second sub-pixel rows 32, and the plurality of fifth shift registers 521 are electrically connected to the plurality of second sub-light emission control signal lines EM22 corresponding to the connection of the multiple rows of the second sub-pixel rows 32 one by one.

[0149] Among them, as Figure 20 shown, taking the example that the first sub-pixel row 31 and the second sub-pixel row 32 are alternately arranged in the column direction, within one frame time, the first-stage fourth shift register 511 outputs the second light emission control signal Emit2 to the first first sub-light emission control signal line EM21, so that the cathode switching transistor M0 corresponding to the connection of the first row of the first sub-pixel row 31 is turned on.

[0150] Then, the first-stage fifth shift register 521 outputs the second light emission control signal Emit2 to the first second sub-light emission control signal line EM22, so that the cathode switching transistor M0 corresponding to the connection of the first row of the second sub-pixel row 32 is turned on.

[0151] Then, the second-stage fourth shift register 511 is driven by the second light emission control signal Emit2 (i.e., the shift control signal) output by the first-stage fourth shift register 511, and outputs the second light emission control signal Emit2 to the second first sub-light emission control signal line EM21, so that the cathode switching transistor M0 corresponding to the connection of the second row of the first sub-pixel row 31 is turned on.

[0152] Then, the second-stage fifth shift register 521 is driven by the second light emission control signal Emit2 (i.e., the shift control signal) output by the first-stage fifth shift register 521, and outputs the second light emission control signal Emit2 to the second second sub-light emission control signal line EM22, so that the cathode switching transistor M0 corresponding to the connection of the second row of the second sub-pixel row 32 is turned on.

[0153] And so on, to realize the row-by-row turn-on of the cathode switching transistors M0 corresponding to the first sub-pixel row 31 and the second sub-pixel row 32.

[0154] Figure 21 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Figure 22 is Figure 21 a schematic cross-sectional structure diagram along the C-C' direction, as Figure 21 and Figure 22 shown. Optionally, the cathodes 23 of the light-emitting elements 112 in the same row of sub-pixels 11 are connected in series to form a cathode row 60. The cathode rows 60 between different rows of sub-pixels 11 are insulated. The cathode row 60 is electrically connected to the second power signal line PVEE through the corresponding cathode switching transistor M0.

[0155] Among them, as described above, the driving processes of the pixel driving circuits 111 of the sub-pixels 11 in the same row are carried out simultaneously, that is, the initialization stage T1, the data signal voltage writing stage T2, and the light-emitting stage T3 (including the first light-emitting sub-stage T31 and the second light-emitting sub-stage T32) of the sub-pixels 11 in the same row are all synchronized.

[0156] As Figure 21 and Figure 22 shown, in this embodiment, it is set that the cathodes 23 of the light-emitting elements 112 in the same row of sub-pixels 11 are connected in series to form a cathode row 60. Among them, one cathode row 60 is correspondingly set for each row of sub-pixels 11. Along the thickness direction of the display panel, the cathode row 60 covers the light-emitting layers 22 of the light-emitting elements 112 of all the sub-pixels 11 in the row where it is located.

[0157] A plurality of cathode rows 60 extend along the row direction and are arranged along the column direction, and there is a gap between two adjacent cathode rows 60 along the column direction, so that the two adjacent cathode rows 60 are insulated from each other.

[0158] Continue to refer to Figure 21 and Figure 22, each cathode row 60 is electrically connected to the second power supply signal line PVEE through a corresponding cathode switching transistor M0. When the cathode switching transistor M0 corresponding to a row of sub-pixels 11 is turned on, the conduction between the cathode row 60 corresponding to this row of sub-pixels 11 and the second power supply signal line PVEE is established. Since the cathode row 60 is formed by connecting the cathodes 23 of all the light-emitting elements 112 in this row of sub-pixels 11 in series, the conduction between the cathode row 60 and the second power supply signal line PVEE is equivalent to the conduction between the cathodes 23 of all the light-emitting elements 112 in this row of sub-pixels 11 and the second power supply signal line PVEE. With such a setting, at least two sub-pixels 11 in a row of sub-pixels 11 can share one cathode switching transistor M0, so that the conduction and cut-off between the cathodes 23 of the light-emitting elements 112 in a row of sub-pixels 11 and the second power supply signal line PVEE can be realized through a smaller number of cathode switching transistors M0, which helps to reduce the occupied space of the cathode switching transistors M0 and lower the cost.

[0159] Continue to refer to Figure 21 and Figure 22 As shown, optionally, one end of the cathode row 60 is electrically connected to the second power supply signal line PVEE through a cathode switching transistor M0. With such a setting, each row of sub-pixels 11 only needs one cathode switching transistor M0 to realize the conduction and cut-off between the cathodes 23 of the light-emitting elements 112 in this row of sub-pixels 11 and the second power supply signal line PVEE, which helps to reduce the occupied space of the cathode switching transistors M0 and lower the cost.

[0160] Figure 23 is a schematic structural diagram of another display panel provided by an embodiment of the present invention. As Figure 23 shown, optionally, a cathode switching transistor M0 is respectively connected between both ends of the cathode row 60 and the second power supply signal line PVEE. With such a setting, when the cathode switching transistor M0 is turned on, both ends of the cathode row 60 are conducted with the second power supply signal line PVEE, which can improve the transmission efficiency of the second power supply voltage from the second power supply signal line PVEE to the cathode row 60, so that the second power supply voltage on the second power supply signal line PVEE can be quickly transmitted to the light-emitting elements 112 at various positions in the same row of sub-pixels 11, which helps to make the light-emitting start times of the light-emitting elements 112 in the same row of sub-pixels 11 more consistent during the light-emitting stage T3.

[0161] Continue to refer to Figure 21 and Figure 23 , optionally, the shortest distance between adjacent cathode rows 60 is d, where d ≥ 2.5 μm. Among them, by setting a gap greater than or equal to 2.5 μm between adjacent cathode rows 60, while ensuring insulation between adjacent cathode rows 60, it is easy to implement in the manufacturing process.

[0162] Continue to refer toFigure 21 and Figure 23 Optionally, the cathode switching transistor M0 is disposed in the non-display area 41 to prevent the cathode switching transistor M0 from affecting the image display in the display area 40.

[0163] Figure 24 FIG. is a schematic partial cross-sectional structure diagram of a display panel provided by an embodiment of the present invention. Figure 25 FIG. is a schematic partial cross-sectional structure diagram of another display panel provided by an embodiment of the present invention. As shown in Figure 24 and Figure 25 shown, optionally, the cathode switching transistor M0 includes at least two sub-switching transistors M01, and the at least two sub-switching transistors M01 are connected in series, and / or the cathode switching transistor M0 includes a double-gate transistor.

[0164] Among them, as shown in Figure 24 shown, by setting the cathode switching transistor M0 to be composed of at least two sub-switching transistors M01 connected in series, when the cathode switching transistor M0 is turned off under the action of the second light emission control signal Emit2 of the second light emission control signal line EM2, all of the at least two sub-switching transistors M01 are turned off. In this way, the leakage current of the cathode switching transistor M0 when it is turned off can be made smaller, thereby avoiding the problem of light leakage of the light-emitting element 112 due to the leakage current between the cathode 23 and the second power supply signal line PVEE during the non-light-emitting stage.

[0165] In other embodiments, as shown in Figure 25 shown, the cathode switching transistor M0 can also be set as a double-gate transistor to reduce the leakage current of the cathode switching transistor M0 when it is turned off, thereby avoiding the problem of light leakage of the light-emitting element 112 due to the leakage current between the cathode 23 and the second power supply signal line PVEE during the non-light-emitting stage.

[0166] Continuing to refer to Figure 24 and Figure 25 shown, optionally, the gate of the cathode switching transistor M0 and the second light emission control signal line EM2 are located in the same film layer.

[0167] Among them, since the gate of the cathode switching transistor M0 needs to be electrically connected to the second light emission control signal line EM2, by setting the gate of the cathode switching transistor M0 and the second light emission control signal line EM2 on the same layer, the gate of the cathode switching transistor M0 and the second light emission control signal line EM2 can be directly connected within the same film layer without the need for a drilling process, which helps to reduce the process difficulty.

[0168] Meanwhile, the gate of the cathode switching transistor M0 is arranged on the same layer as the second light emission control signal line EM2, which can also reduce the setting of one metal layer, thereby achieving the purpose of reducing production costs and the substrate thickness. Moreover, the gate of the cathode switching transistor M0 can adopt the same material as the second light emission control signal line EM2, enabling the gate of the cathode switching transistor M0 and the second light emission control signal line EM2 to be fabricated in the same manufacturing process, thus shortening the manufacturing time.

[0169] Continue to refer to Figure 24 , optionally, the display panel further includes a substrate 00. The cathode switching transistor M0 and the driving transistor M3 are located on the same side of the substrate 00. The active layer of the cathode switching transistor M0 and the active layer 01 of the driving transistor M3 are located in the same film layer. The gate layer of the cathode switching transistor M0 and the gate layer 02 of the driving transistor M3 are located in the same film layer. The source-drain electrode layer of the cathode switching transistor and the source-drain electrode layer 03 of the driving transistor M3 are located in the same film layer.

[0170] Specifically, as Figure 2 , Figure 22 , Figure 24 and Figure 25 shown, the driving transistor M3 may include an active layer 01, a gate layer 02, and a source-drain electrode layer 03 that are stacked on the substrate 00.

[0171] As Figure 24 shown, in this embodiment, by arranging the cathode switching transistor M0 on the same layer as the driving transistor M3, it helps to reduce the number of film layers, thereby achieving the purpose of reducing production costs and the substrate thickness. Moreover, the cathode switching transistor M0 and the driving transistor M3 can be fabricated in the same manufacturing process, thus shortening the manufacturing time.

[0172] Continue to refer to Figure 24 and Figure 25 , optionally, the display panel further includes a substrate 00. The cathode switching transistor M0 and the second power supply signal line PVEE are located on the same side of the substrate 00. The source-drain electrode layer of the cathode switching transistor M0 and the second power supply signal line PVEE are located in the same film layer.

[0173] Among them, since the source-drain electrode layer of the cathode switching transistor M0 needs to be electrically connected to the second power supply signal line PVEE, by arranging the source-drain electrode layer of the cathode switching transistor M0 on the same layer as the second power supply signal line PVEE, the source-drain electrode layer of the cathode switching transistor M0 and the second power supply signal line PVEE can be directly connected within the same film layer without the need for a drilling process, which helps to reduce the process difficulty.

[0174] Meanwhile, by arranging the source-drain electrode layer of the cathode switching transistor M0 on the same layer as the second power supply signal line PVEE, one less metal layer can be provided, thereby reducing production costs and the substrate thickness. Moreover, the source-drain electrode layer of the cathode switching transistor M0 can adopt the same material as the second power supply signal line PVEE, enabling the source-drain electrode layer of the cathode switching transistor M0 and the second power supply signal line PVEE to be fabricated in the same manufacturing process, thus shortening the manufacturing time.

[0175] Continuing to refer to Figure 24 and Figure 25 , optionally, the display panel further includes a substrate 00. The cathode switching transistor M0 and the light-emitting element 112 are located on the same side of the substrate 00, and the light-emitting element 112 is located on the side of the cathode switching transistor M0 away from the substrate 00. The cathode 23 of the light-emitting element 112 is located on the side of the anode 21 away from the substrate 00. The source-drain electrode layer of the cathode switching transistor M0 is electrically connected to the cathode 23 of the light-emitting element 112 through a bridging metal layer 70, and the bridging metal layer 70 is located between the source-drain electrode layer of the cathode switching transistor M0 and the cathode 23 of the light-emitting element 112.

[0176] Among them, by arranging the source-drain electrode layer of the cathode switching transistor M0 to be electrically connected to the cathode 23 of the light-emitting element 112 through the bridging metal layer 70 located between the source-drain electrode layer of the cathode switching transistor M0 and the cathode 23 of the light-emitting element 112, the deep via process can be avoided when the source-drain electrode layer of the cathode switching transistor M0 is electrically connected to the cathode 23 of the light-emitting element 112, ensuring that the electrical connection process between the source-drain electrode layer of the cathode switching transistor M0 and the cathode 23 of the light-emitting element 112 is simple.

[0177] Continuing to refer to Figure 24 and Figure 25 , optionally, the bridging metal layer 70 and the anode 21 are located in the same film layer.

[0178] Among them, by arranging the bridging metal layer 70 and the anode 21 on the same layer, one less metal layer can be provided, thereby reducing production costs and the substrate thickness. Moreover, the bridging metal layer 70 can adopt the same material as the anode 21, enabling the bridging metal layer 70 and the anode 21 to be fabricated in the same manufacturing process, thus shortening the manufacturing time.

[0179] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 26 is a schematic structural diagram of a display device provided by an embodiment of the present invention, as Figure 26As shown, the display device 80 includes the display panel 81 described in any embodiment of the present invention. Therefore, the display device 80 provided by the embodiment of the present invention has the technical effects of the technical solutions in any of the above embodiments, and the explanations of the same or corresponding structures and terms as those in the above embodiments will not be repeated here.

[0180] The display device 80 provided by the embodiment of the present invention can be Figure 26 the mobile phone shown in the figure, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical device, industrial control device, touch interaction terminal, etc. The embodiment of the present invention does not make special limitations on this.

[0181] Based on the same inventive concept, the embodiment of the present invention also provides a driving method for a display panel. This driving method can be used to drive any display panel provided by the above embodiment, and the explanations of the same or corresponding structures and terms as those in the above embodiment will not be repeated here.

[0182] Among them, the display panel includes a cathode switching transistor and a plurality of sub-pixels arranged in an array. The sub-pixels include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit includes a driving transistor and at least one light-emitting control transistor. The driving transistor, the light-emitting control transistor, the light-emitting element, and the cathode switching transistor are connected in series between a first power supply signal line and a second power supply signal line. The light-emitting control transistor is connected in series between the anode of the light-emitting element and the first power supply signal line, and the cathode switching transistor is connected in series between the cathode of the light-emitting element and the second power supply signal line. The gate of the light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the cathode switching transistor is electrically connected to a second light-emitting control signal line.

[0183] The structural description and term explanation of the above display panel can be referred to the above embodiment, and will not be repeated here.

[0184] Figure 27 It is a schematic flowchart of a driving method for a display panel provided by the embodiment of the present invention. As Figure 27 shown, the driving method includes:

[0185] S110. Apply a first light-emitting control signal to the first light-emitting control signal line.

[0186] S120. Apply a second light-emitting control signal to the second light-emitting control signal line.

[0187] Among them, within at least one light-emitting stage, the start time of the effective pulse of the second light-emitting control signal lags behind the start time of the effective pulse of the first light-emitting control signal.

[0188] The driving method of the display panel provided by the embodiment of the present invention, in the light-emitting stage, first applies a first light-emitting control signal to the first light-emitting control signal line, so that the light-emitting control transistor is first turned on to charge the pixel capacitor of the light-emitting element. After the pixel capacitors of the light-emitting elements emitting different colors of light are charged, then a second light-emitting control signal is applied to the second light-emitting control signal line, so that the cathode switch transistor is turned on, so that the light-emitting elements emitting different colors of light emit light simultaneously when the cathode switch transistor is turned on, so that the light-emitting durations of the light-emitting elements emitting different colors of light in the light-emitting stage tend to be the same, and the light-emitting efficiency tends to be the same, solving the color cast problem caused by the difference in pixel capacitors in the light-emitting elements emitting different colors of light.

[0189] Optionally, at least some of the sub-pixels have different light-emitting colors; the light-emitting elements in the sub-pixels have corresponding pixel capacitors, and the capacitance values of the pixel capacitors of the light-emitting elements in the sub-pixels with different light-emitting colors are different. In at least one row of sub-pixels, the sub-pixel with the largest capacitance value of the pixel capacitor of the light-emitting element is the sub-pixel with the largest capacitance, and the charging time of the pixel capacitor of the light-emitting element in the sub-pixel with the largest capacitance is t1. For at least one row of sub-pixels, in the light-emitting stage, the duration by which the start time of the effective pulse of the second light-emitting control signal of the second light-emitting control signal line corresponding to the sub-pixel lags behind the start time of the effective pulse of the first light-emitting control signal of the first light-emitting control signal line corresponding to the sub-pixel is the delay time, where the delay time is △t, and △t≥t1.

[0190] Among them, the structure description of the above display panel and the explanation of the terms can be referred to the above embodiment, and will not be elaborated here.

[0191] In this embodiment, for any row of sub-pixels, by setting the delay time △t to be greater than or equal to the charging time t1 of the pixel capacitor of the light-emitting element in the sub-pixel with the largest capacitance, it is possible to complete the charging process of the pixel capacitors of the light-emitting elements in all sub-pixels of this row before the cathode switch transistor corresponding to this row of sub-pixels is turned on, so as to ensure that each row of sub-pixels emits light simultaneously when the cathode switch transistor corresponding to this row of sub-pixels is turned on (that is, at the start time of the effective pulse of the second light-emitting control signal of the second light-emitting control signal line), without having to charge the pixel capacitor of the light-emitting element again, so that the light-emitting start times of the light-emitting elements emitting different colors of light in the same row of sub-pixels in the light-emitting stage are the same, and then the light-emitting durations of the light-emitting elements emitting different colors of light in the light-emitting stage will tend to be the same, so that the light-emitting efficiency of the light-emitting elements tends to be the same, solving the color cast problem caused by the difference in pixel capacitors in the light-emitting elements emitting different colors of light.

[0192] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0193] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, It includes a cathode switching transistor and a plurality of sub-pixels arranged in an array; The sub-pixels include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit includes a driving transistor and at least one light-emitting control transistor; The driving transistor, the light-emitting control transistor, the light-emitting element, and the cathode switching transistor are connected in series between a first power signal line and a second power signal line. Among them, the light-emitting control transistor is connected in series between the anode of the light-emitting element and the first power signal line, and the cathode switching transistor is connected in series between the cathode of the light-emitting element and the second power signal line; The gate of the light-emitting control transistor is electrically connected to a first light-emitting control signal line, and the gate of the cathode switching transistor is electrically connected to a second light-emitting control signal line; within at least one light-emitting stage, the start time of the effective pulse of the second light-emitting control signal on the second light-emitting control signal line lags behind the start time of the effective pulse of the first light-emitting control signal on the first light-emitting control signal line; At least some of the sub-pixels have different light-emitting colors; the light-emitting elements in the sub-pixels have corresponding pixel capacitors, and the capacitance values of the pixel capacitors of the light-emitting elements in the sub-pixels with different light-emitting colors are different; In at least one row of the sub-pixels, the sub-pixel with the largest capacitance value of the pixel capacitor of the light-emitting element is the maximum capacitance sub-pixel, and the charging time of the pixel capacitor of the light-emitting element in the maximum capacitance sub-pixel is t1; For at least one row of the sub-pixels, within the light-emitting stage, the duration by which the start time of the effective pulse of the second light-emitting control signal on the second light-emitting control signal line corresponding to the sub-pixel lags behind the start time of the effective pulse of the first light-emitting control signal on the first light-emitting control signal line corresponding to the sub-pixel is the delay time, where the delay time is Δt, and Δt≥t1.

2. The display panel according to claim 1, characterized in that, The plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The capacitance value of the pixel capacitor of the light-emitting element in the first color sub-pixel is greater than the capacitance value of the pixel capacitor of the light-emitting element in the second color sub-pixel, and the capacitance value of the pixel capacitor of the light-emitting element in the second color sub-pixel is greater than the capacitance value of the pixel capacitor of the light-emitting element in the third color sub-pixel; The charging time of the pixel capacitor of the light-emitting element in the first color sub-pixel is t2, where Δt≥t2.

3. The display panel according to claim 2, characterized in that, The delay times corresponding to each row of the sub-pixels are all equal.

4. The display panel according to claim 1, characterized in that, 2 μs≤Δt≤4 μs.

5. The display panel according to claim 1, characterized in that, The plurality of sub-pixels include a first sub-pixel row and a second sub-pixel row; The light-emitting colors of the maximum capacitance sub-pixels in the first sub-pixel row and the second sub-pixel row are different, and the capacitance value of the pixel capacitor of the maximum capacitance sub-pixel in the first sub-pixel row is greater than the capacitance value of the pixel capacitor of the maximum capacitance sub-pixel in the second sub-pixel row; The delay time corresponding to the first sub-pixel row is greater than the delay time corresponding to the second sub-pixel row.

6. The display panel according to claim 5, characterized in that, The first sub-pixel row and the second sub-pixel row are alternately arranged in the column direction; The plurality of sub-pixels include a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel. The capacitance value of the pixel capacitance of the light-emitting element in the first-color sub-pixel is greater than the capacitance value of the pixel capacitance of the light-emitting element in the second-color sub-pixel, and the capacitance value of the pixel capacitance of the light-emitting element in the second-color sub-pixel is greater than the capacitance value of the pixel capacitance of the light-emitting element in the third-color sub-pixel; The first sub-pixel row includes the first-color sub-pixel and the second-color sub-pixel, and the second sub-pixel row includes the second-color sub-pixel and the third-color sub-pixel; or, the first sub-pixel row includes the first-color sub-pixel and the third-color sub-pixel, and the second sub-pixel row includes the second-color sub-pixel and the third-color sub-pixel; The delay time corresponding to the first sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the first-color sub-pixel, and the delay time corresponding to the second sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the second-color sub-pixel.

7. The display panel according to claim 5, characterized in that, The first sub-pixel row and the second sub-pixel row are alternately arranged in the column direction; The plurality of sub-pixels include a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel. The capacitance value of the pixel capacitance of the light-emitting element in the first-color sub-pixel is greater than the capacitance value of the pixel capacitance of the light-emitting element in the second-color sub-pixel, and the capacitance value of the pixel capacitance of the light-emitting element in the second-color sub-pixel is greater than the capacitance value of the pixel capacitance of the light-emitting element in the third-color sub-pixel; The first sub-pixel row includes the first-color sub-pixel and the second-color sub-pixel, and the second sub-pixel row includes the third-color sub-pixel; the delay time corresponding to the first sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the first-color sub-pixel, and the delay time corresponding to the second sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the third-color sub-pixel; Or, The first sub-pixel row includes the first-color sub-pixel and the third-color sub-pixel, and the second sub-pixel row includes the second-color sub-pixel; the delay time corresponding to the first sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the first-color sub-pixel, and the delay time corresponding to the second sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the second-color sub-pixel; Or, The first sub-pixel row includes the first color sub-pixels, and the second sub-pixel row includes the second color sub-pixels and the third color sub-pixels; the delay time corresponding to the first sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the first color sub-pixels, and the delay time corresponding to the second sub-pixel row is greater than or equal to the charging time of the pixel capacitance of the light-emitting element in the second color sub-pixels.

8. The display panel according to claim 2 or 6, characterized in that, The first color sub-pixels are green sub-pixels, the second color sub-pixels are red sub-pixels, and the third color sub-pixels are blue sub-pixels.

9. The display panel according to any one of claims 1-7, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area; the non-display area includes a first scan driving circuit and a second scan driving circuit. The first light-emitting control signal line is electrically connected to the first scan driving circuit, and the second light-emitting control signal line is electrically connected to the second scan driving circuit.

10. The display panel according to claim 9, wherein, The delay time corresponding to each row of the sub-pixels is equal. The display panel includes N rows of the sub-pixels. The first scan driving circuit includes N cascaded first shift registers, and the second scan driving circuit includes N cascaded second shift registers. The first light-emitting control signal line corresponding to the sub-pixels in the i-th row is electrically connected to the i-th stage of the first shift register. The second light-emitting control signal line corresponding to the sub-pixels in the i-th row is electrically connected to the i-th stage of the second shift register. Wherein, 1 ≤ i ≤ N, and i is a positive integer.

11. The display panel according to claim 9, wherein, The delay time corresponding to each row of the sub-pixels is equal. The display panel includes N rows of the sub-pixels. The first scan driving circuit and the second scan driving circuit are the same scan driving circuit, and the scan driving circuit includes N cascaded third shift registers. The first light-emitting control signal line corresponding to the sub-pixels in the i-th row is electrically connected to the i-th stage of the third shift register, and the first light-emitting control signal line corresponding to the sub-pixels in the N-th row is electrically connected to the N-th stage of the third shift register. The second light-emitting control signal line corresponding to the sub-pixels in the i-th row is electrically connected to the (i + 1)-th stage of the third shift register, and the second light-emitting control signal line corresponding to the sub-pixels in the N-th row is electrically connected to the first stage of the third shift register. Wherein, 1 ≤ i ≤ N - 1, and i is a positive integer.

12. The display panel according to claim 9, wherein, The multiple sub-pixels include a first sub-pixel row and a second sub-pixel row. The light-emitting colors of the maximum capacitance sub-pixels in the first sub-pixel row and the maximum capacitance sub-pixels in the second sub-pixel row are different, and the capacitance value of the pixel capacitance of the maximum capacitance sub-pixels in the first sub-pixel row is greater than the capacitance value of the pixel capacitance of the maximum capacitance sub-pixels in the second sub-pixel row. The delay time corresponding to the first sub-pixel row is greater than the delay time corresponding to the second sub-pixel row. The second light-emitting control signal line includes a first sub-light-emitting control signal line and a second sub-light-emitting control signal line. The gate of the cathode switching transistor corresponding to the first sub-pixel row is electrically connected to the first sub-light-emitting control signal line, and the gate of the cathode switching transistor corresponding to the second sub-pixel row is electrically connected to the second sub-light-emitting control signal line; The second scanning driving circuit includes a first sub-scanning circuit and a second sub-scanning circuit. The first sub-scanning circuit is electrically connected to the first sub-light-emitting control signal line, and the second sub-scanning circuit is electrically connected to the second sub-light-emitting control signal line.

13. The display panel according to claim 1, wherein, The cathodes of the light-emitting elements in the same row of the sub-pixels are connected in series to form a cathode row; The cathode rows of the sub-pixels in different rows are insulated from each other; The cathode row is electrically connected to the second power supply signal line through the corresponding cathode switching transistor.

14. The display panel according to claim 1, wherein, The cathode switching transistor includes at least two sub-switching transistors, and at least two of the sub-switching transistors are connected in series, and / or the cathode switching transistor includes a dual-gate transistor.

15. A display device, wherein, A display panel according to any one of claims 1-14.

16. A driving method for a display panel, wherein, The display panel includes a cathode switching transistor and a plurality of sub-pixels arranged in an array; the sub-pixels include a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit, and the pixel driving circuit includes a driving transistor and at least one light-emitting control transistor; the driving transistor, the light-emitting control transistor, the light-emitting element, and the cathode switching transistor are connected in series between a first power supply signal line and a second power supply signal line. Among them, the light-emitting control transistor is connected in series between the anode of the light-emitting element and the first power supply signal line, and the cathode switching transistor is connected in series between the cathode of the light-emitting element and the second power supply signal line; the gate of the light-emitting control transistor is electrically connected to the first light-emitting control signal line, and the gate of the cathode switching transistor is electrically connected to the second light-emitting control signal line; The driving method includes: Applying a first light-emitting control signal to the first light-emitting control signal line; Applying a second light-emitting control signal to the second light-emitting control signal line; Wherein, within at least one light-emitting stage, the start time of the effective pulse of the second light-emitting control signal lags behind the start time of the effective pulse of the first light-emitting control signal; At least some of the sub-pixels have different light-emitting colors; the light-emitting elements in the sub-pixels have corresponding pixel capacitors, and the capacitance values of the pixel capacitors of the light-emitting elements in the sub-pixels with different light-emitting colors are different; In at least one row of the sub-pixels, the sub-pixel with the largest capacitance value of the pixel capacitor of the light-emitting element is the maximum capacitance sub-pixel, and the charging time of the pixel capacitor of the light-emitting element in the maximum capacitance sub-pixel is t1; For at least one row of the sub-pixels, during the light-emitting stage, the duration by which the start time of the effective pulse of the second light-emitting control signal on the second light-emitting control signal line corresponding to the sub-pixel lags behind the start time of the effective pulse of the first light-emitting control signal on the first light-emitting control signal line corresponding to the sub-pixel is the delay time, where the delay time is Δt and Δt ≥ t1.

Images