Display system and operating method thereof

Abstract

A display system and an operating method thereof. The display system includes a display panel, a source driver, and a timing controller. The source driver is coupled to the display panel to provide multiple pixel voltages to the display panel. The timing controller has a transmission interface circuit and is coupled to the source driver. The timing controller detects whether the operating timing of the display system enters a vertical blanking period. When the operating timing of the display system enters the vertical blanking period, the timing controller turns off the transmission interface circuit and puts the source driver into an idle mode. When the operating timing of the display system is within a preset time before the end of the vertical blanking period, the timing controller turns on the transmission interface circuit and wakes up the source driver.

Description

Technical Field

[0001] The present invention relates to a display system, and more particularly to a display system and an operating method thereof. Background Art

[0002] A variable refresh rate (VRR) panel automatically and continuously adjusts its refresh rate based on the actual content being displayed, rather than being fixed at 90 or 120 Hz like current mainstream mobile phones. With a fixed refresh rate, even when displaying static content (such as images), the screen will constantly refresh at a fixed frequency, increasing power consumption. However, with variable refresh rate panel technology, power consumption can be significantly reduced.

[0003] Correspondingly, Intel has also proposed a low refresh rate (LRR) panel technology to control the display panel to operate at different refresh rates to save power. Among them, the low refresh rate panel technology requires the display panel to switch the screen refresh rate by changing the vertical total amount. In other words, the active display time transmitted to the display panel by the system side remains unchanged, and only the length of the vertical blanking (VBK) period is changed. As the screen refresh rate frequency decreases, the vertical blanking period accounts for a longer proportion of the time in a screen period. However, as the screen refresh rate frequency decreases, the power consumption is reduced, but the control circuit that drives the display panel still operates at the original frequency, thus limiting the power saving benefits of the display system. Summary of the Invention

[0004] The present invention provides a display system and an operating method thereof, which can improve the power saving efficiency of the display system under the condition of variable refresh rate.

[0005] The display system of the present invention includes a display panel, a source driver, and a timing controller. The source driver is coupled to the display panel to provide multiple pixel voltages to the display panel. The timing controller has a transmission interface circuit and is coupled to the source driver. The timing controller detects whether the operating timing of the display system enters a vertical blanking period. When the operating timing of the display system enters the vertical blanking period, the timing controller turns off the transmission interface circuit and puts the source driver into an idle mode. When the operating timing of the display system is within a preset time before the end of the vertical blanking period, the timing controller turns on the transmission interface circuit and wakes up the source driver.

[0006] The present invention provides a method for operating a display system, comprising the following steps: A timing controller of the display system detects whether an operating sequence of the display system enters a vertical blanking period. When the operating sequence of the display system enters the vertical blanking period, the timing controller shuts down a transmission interface circuit within the timing controller and places a source driver of the display system into an idle mode. When the operating sequence of the display system falls within a predetermined time before the end of the vertical blanking period, the timing controller turns on the transmission interface circuit and wakes up the source driver.

[0007] Based on the above, the display system and operating method of the embodiment of the present invention can improve the power saving efficiency of the display system by shutting down the transmission interface circuit and making the source driver enter idle (or sleep) during the vertical blank period through the timing controller.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a schematic diagram of a display system according to an embodiment of the present invention.

[0010] Figure 2 FIG. 1 is a schematic diagram of driving waveforms of a display system according to an embodiment of the present invention.

[0011] Figure 3 FIG. 4 is a flow chart of an operating method of a display system according to an embodiment of the present invention.

[0012] Description of reference numerals:

[0013] 100: Display system

[0014] 110: Timing controller

[0015] 120: Source driver

[0016] 130: Gate Driver

[0017] 140: Display panel

[0018] CT: Training code

[0019] Data-P: Display data

[0020] LDA: data line

[0021] LGA: Gate Line

[0022] Lock: Lock signal

[0023] PACT: Active display time

[0024] PFR: Picture duration

[0025] PVB: Vertical Blank Period

[0026] PX: Pixel

[0027] SET: Set parameters

[0028] SGA: Gate signal

[0029] Tx: Transmit interface circuit

[0030] VBB: Back Porch Period

[0031] VBF: Front Porch Period

[0032] Vpx: pixel voltage

[0033] Wake: wake-up signal

[0034] XSC: control signal

[0035] S110, S120, S130, S140: Steps DETAILED DESCRIPTION

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0037] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a "first element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0038] The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and / or "including" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, components and / or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or combinations thereof.

[0039] Figure 1 This is a schematic diagram of a display system according to an embodiment of the present invention. Figure 1 In this embodiment, the display system 100 includes at least a timing controller 110, a source driver 120, a gate driver 130, and a display panel 140. The gate driver 130 is coupled to the display panel 140 to provide a plurality of gate signals SGA that are sequentially enabled (e.g., at a high voltage level) to the display panel 140. The source driver 120 is coupled to the display panel 140 to provide a plurality of pixel voltages Vpx to the display panel 140. The timing controller 110 is coupled to the source driver 120 and the gate driver 130, and has a transmission interface circuit Tx.

[0040] The timing controller 110 outputs a wake-up signal Wake to the source driver 120 to control the source driver 120 to enter an idle mode or to wake up the source driver 120 from the idle mode. Furthermore, the timing controller 110 receives a lock signal Lock from the source driver 120 to determine whether the source driver 120 is ready. If the source driver 120 is ready, the timing controller 110 transmits data to the source driver 120 via the transmission interface circuit Tx.

[0041] Furthermore, the timing controller 110 can detect whether the operation timing of the display system 100 enters a vertical blank period (eg, Figure 2The timing controller 110 can determine the operating timing of the display system 100 using a vertical synchronization signal (V-sync) or similar signal and a counter during the horizontal scanning period. Then, when the operating timing of the display system 100 enters the vertical blanking period, the timing controller 110 shuts down the transmission interface circuit Tx and causes the source driver 120 to enter an idle mode. When the operating timing of the display system 100 is a predetermined time before the end of the vertical blanking period (e.g., entering the back corridor period of the vertical blanking period), the timing controller 110 can turn on the transmission interface circuit Tx and wake up the source driver 120. Therefore, by idling (or sleeping) and waking up the transmission interface circuit Tx and the source driver 120, the power saving efficiency of the display system 100 can be improved.

[0042] In this embodiment, the timing controller 110 may transmit a plurality of control signals XSC to the gate driver 130 to control the timing of the gate driver 130 outputting the gate signal SGA.

[0043] In this embodiment, the display panel 140 includes a plurality of pixels PX, a plurality of gate lines LGA, and a plurality of data lines LDA. The pixels PX are arranged in an array, for example. The gate lines LGA are coupled to the gate driver 130 and are arranged in parallel, for example, along the vertical direction of the drawing. The data lines LDA are coupled to the source driver 120 and are arranged in parallel, for example, along the horizontal direction of the drawing. Each pixel PX is coupled to one of the gate lines LGA to receive a corresponding gate signal SGA via the gate line LGA, and is coupled to one of the data lines LDA to receive a corresponding pixel voltage Vpx via the data line LDA.

[0044] In this embodiment, the transmission interface circuit Tx may be a differential signal output circuit, but the embodiment of the present invention is not limited thereto.

[0045] Figure 2 Schematic diagram of driving waveforms of a display system according to an embodiment of the present invention. Figure 1 and Figure 2 In this embodiment, a single picture period PFR includes at least an active display period PACT and a vertical blanking period PVB. The vertical blanking period PVB can be divided into at least a front porch period VBF and a back porch period VBB. A single vertical blanking period PVB can be formed by combining the front porch period VBF of the current picture period PFR and the back porch period VBB of the next picture period PFR.

[0046] When entering the vertical blank period (PVB), the timing controller 110 directly shuts down the transmit interface circuit Tx to stop data transmission (i.e., the data field is blanked), and sets the wake-up signal Wake to a disabled level (e.g., a low voltage level) to place the source driver 120 in an idle mode. When entering the idle mode, the source driver 120 sets the lock signal Lock to a disabled level to inform the timing controller 110 that the timing needs to be relocked.

[0047] At a preset time (taking the back corridor period VBB as an example) before the end of the vertical blank period PVB, the timing controller 110 can directly turn on the transmission interface circuit Tx, and the timing controller 110 sets the wake-up signal Wake to an enable level (e.g., a high voltage level) to wake up the source driver 120.

[0048] When the timing controller 110 turns on the transmission interface circuit Tx, the transmission interface circuit Tx outputs a training code CT to the source driver 120. The source driver 120 then relocks the transmission timing of the data transmitted by the transmission interface circuit Tx based on the training code CT. When the source driver 120 locks the transmission timing based on the training code CT, it sets the lock signal Lock provided to the timing controller 110 to an enabled level, indicating that it can receive and output data.

[0049] When the lock signal Lock is at an enable level, the timing controller 110 sequentially transmits the setting parameter SET and the display data Data-P to the source driver 120 through the transmission interface circuit Tx during the active display time PACT, wherein the source driver 120 sets its operating state based on the setting parameter SET and provides the pixel voltages Vpx based on the display data Data-P.

[0050] In this embodiment, the preset time before the end of the vertical blank period PVB is taken as the back corridor period VBB. However, in the embodiment of the present invention, the preset time can be any number of horizontal scanning periods, which depends on the circuit design and is not limited to this embodiment of the present invention.

[0051] Figure 3 This is a flow chart of an operating method of a display system according to an embodiment of the present invention. Figure 3 In this embodiment, the operating method of the display system includes the following steps. In step S110, the timing controller of the display system detects whether the operating timing of the display system has entered a vertical blanking period. If the operating timing of the display system has not entered the vertical blanking period, that is, the determination result of step S110 is "no", the process returns to step S110. If the operating timing of the display system is about to enter the vertical blanking period, that is, the determination result of step S110 is "yes", the process proceeds to step S120.

[0052] In step S120, the timing controller shuts down the transmission interface circuit in the timing controller and places the source driver of the display system into idle mode. In step S130, the timing controller of the display system detects whether the operation timing of the display system is within a preset time before the end of the vertical blanking period. If the operation timing of the display system is not within the preset time before the end of the vertical blanking period, that is, the judgment result of step S130 is "no", the process returns to step S130. If the operation timing of the display system is within the preset time before the end of the vertical blanking period, that is, the judgment result of step S130 is "yes", the process proceeds to step S140.

[0053] In step S140, the transmission interface circuit is turned on and the source driver is awakened via the timing controller. The order of steps S110, S120, S130 and S140 is for illustration only and the present invention is not limited thereto. Figure 1 and Figure 2 The embodiments are described in detail and will not be repeated here.

[0054] In summary, the display system and operating method according to the embodiment of the present invention can improve the power saving efficiency of the display system by shutting down the transmission interface circuit and making the source driver enter idle (or sleep) mode during the vertical blank period through the timing controller.

[0055] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A display system comprising: a display panel; a source driver coupled to the display panel and configured to provide a plurality of pixel voltages to the display panel; as well as A timing controller has a transmission interface circuit and is coupled to the source driver. The timing controller detects whether an operation timing of the display system enters a vertical blank period. When the operation timing of the display system enters the vertical blank period, the timing controller turns off the transmission interface circuit and causes the source driver to enter an idle mode. When the operation timing of the display system is a preset time before the end of the vertical blank period, the timing controller turns on the transmission interface circuit and wakes up the source driver. The preset time is the back corridor period of the vertical blank period, When the timing controller turns on the transmission interface circuit, the transmission interface circuit outputs a training code to the source driver, and When the source driver locks a transmission timing based on the training code, a lock signal is set to an enable level, wherein the lock signal is provided to the timing controller, When entering the idle mode, the source driver sets the lock signal to a disable level to inform the timing controller that the timing needs to be re-locked.

2. The display system of claim 1 , wherein when the lock signal is at the enable level, the timing controller sequentially transmits a setting parameter and display data to the source driver through the transmission interface circuit, wherein the source driver provides the pixel voltages based on the display data. 3 . The display system as claimed in claim 1 , wherein the timing controller outputs a wake-up signal to the source driver, and sets the wake-up signal to an enable level to wake up the source driver. 4 . The display system as claimed in claim 3 , wherein during the vertical blank period, the wake-up signal is set to a disable level to enable the source driver to enter the idle mode.

5. A method for operating a display system, comprising: Detecting, via a timing controller of the display system, whether an operation timing of the display system enters a vertical blank period; When the operation timing of the display system enters the vertical blank period, shutting down a transmission interface circuit in the timing controller via the timing controller and causing a source driver of the display system to enter an idle mode; When the operation timing of the display system is at a preset time before the end of the vertical blank period, the transmission interface circuit is turned on and the source driver is awakened via the timing controller. The preset time is the back corridor period of the vertical blank period, When the timing controller turns on the transmission interface circuit, a training code is output to the source driver via the transmission interface circuit; as well as When the source driver locks a transmission timing based on the training code, a lock signal is set to an enable level via the source driver, wherein the lock signal is provided to the timing controller, When entering the idle mode, the source driver sets the lock signal to a disable level to inform the timing controller that the timing needs to be re-locked.

6. The operating method according to claim 5, further comprising: When the lock signal is at the enable level, a setting parameter and display data are sequentially transmitted to the source driver via the timing controller through the transmission interface circuit, wherein the source driver provides a plurality of pixel voltages to a display panel of the display system based on the display data.

7. The operating method according to claim 5, further comprising: Outputting a wake-up signal to the source driver via the timing controller; as well as The timing controller sets the awakening signal to an enable level to wake up the source driver.

8. The operating method according to claim 7, further comprising: During the vertical blank period, the wake-up signal is set to a disable level via the timing controller to enable the source driver to enter the idle mode.

Images