Preparation method of metal wiring structure and semiconductor device

Abstract

The present invention provides a method for preparing a metal interconnect structure, comprising: filling a through-hole structure with metal tungsten to form an initial tungsten interconnect structure not lower than the upper surface of the through-hole layer; removing a portion of the dielectric material of the through-hole layer so that the upper surface of the formed second dielectric layer is lower than the upper surface of the initial tungsten interconnect structure; depositing an adhesive layer so that the adhesive layer covers the initial tungsten interconnect structure exposed in the second dielectric layer; depositing a tungsten sacrificial layer; performing a chemical mechanical planarization process until the adhesive layer located on the upper surface of the second dielectric layer is exposed; and removing the adhesive layer until the second dielectric layer is exposed to form a tungsten interconnect structure. This method avoids the infiltration of abrasive liquid into the zero-layer cobalt interconnect structure and solves the problem of cobalt deficiency in the metal interconnect structure. Furthermore, the obtained metal interconnect structure does not require an adhesive layer, which greatly reduces contact resistance. The present invention also provides a semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit technology, and in particular to a method for preparing a metal wiring structure and a semiconductor device. Background Art

[0002] As semiconductor device sizes shrink, the contact via diameter (CD) requirements become increasingly smaller. To reduce interconnect resistance, the resistivity of the contact via material must be further reduced. Currently, the internationally accepted practice is to replace traditional tungsten with cobalt, a metal with lower sheet resistance (RS), in the zero-level interconnect layer. Furthermore, a selective tungsten deposition process (selective W deposition) without a bonding layer (Ti / TiN) is used in the contact via layer, replacing the traditional chemical vapor deposition (CVDW) process. Because the selective tungsten deposition process does not require a bonding layer (Ti / TiN), it significantly reduces contact resistance.

[0003] However, the difficulty of this selective tungsten deposition process lies in the fact that if the via layer is deposited using a selective metal tungsten deposition process without a bonding layer, the metal tungsten structure and the sidewall dielectric layer will not be tightly bonded due to the lack of a bonding layer. This will cause the metal tungsten polishing solution in the via layer to seep into the underlying interconnect layer through the weak contact between the metal tungsten structure and the dielectric layer sidewall during the subsequent tungsten chemical mechanical polishing process. Because cobalt and tungsten have opposite potential-pH characteristics, the acidic tungsten polishing solution will rapidly corrode the cobalt metal, resulting in cobalt-missing defects.

[0004] Therefore, it is necessary to provide a novel method for preparing a metal wiring structure and a semiconductor device to solve the above problems existing in the prior art. Summary of the Invention

[0005] The present invention aims to provide a method for preparing a metal interconnect structure and a semiconductor device, thereby preventing abrasive liquid from penetrating into a zero-layer cobalt interconnect structure through a weak interface between a second dielectric layer and an initial tungsten interconnect structure, thereby avoiding corrosion of the zero-layer cobalt interconnect structure by the abrasive liquid, solving the problem of cobalt deficiency in the metal interconnect structure, and eliminating the need for an adhesive layer in the prepared metal interconnect structure, thereby greatly reducing contact resistance.

[0006] To achieve the above-mentioned object, the method for preparing the metal wiring structure of the present invention comprises the following steps:

[0007] S1: providing a first dielectric layer having a zero-layer cobalt interconnect structure;

[0008] S2: forming a patterned through-hole layer on the upper surface of the first dielectric layer, and allowing the through-hole structure in the through-hole layer to penetrate the through-hole layer to the surface of the zero-layer cobalt interconnect structure;

[0009] S3: filling metal tungsten into the through-hole structure to form an initial tungsten interconnection structure, and making the upper surface of the initial tungsten interconnection structure no lower than the upper surface of the through-hole layer;

[0010] S4: removing a portion of the dielectric material of the through-hole layer to form a second dielectric layer, and making the upper surface of the second dielectric layer lower than the upper surface of the initial tungsten interconnect structure;

[0011] S5: depositing an adhesive layer on the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure, and allowing the adhesive layer to cover the initial tungsten interconnect structure exposed on the second dielectric layer;

[0012] S6: depositing metal tungsten on the upper surface of the bonding layer to form a tungsten sacrificial layer;

[0013] S7: removing the tungsten sacrificial layer, a portion of the bonding layer, and a portion of the initial tungsten interconnect structure using a chemical mechanical planarization process until the bonding layer located on the upper surface of the second dielectric layer is exposed;

[0014] S8: removing the adhesive layer on the upper surface of the second dielectric layer until the second dielectric layer is exposed, thereby forming a tungsten interconnect structure.

[0015] The method for preparing a metal interconnect structure of the present invention has the following beneficial effects: S3: filling metal tungsten within the through-hole structure to form an initial tungsten interconnect structure, with the upper surface of the initial tungsten interconnect structure being no lower than the upper surface of the through-hole layer; S4: removing a portion of the dielectric material of the through-hole layer to form a second dielectric layer, with the upper surface of the second dielectric layer being lower than the upper surface of the initial tungsten interconnect structure. This facilitates the bonding layer completely covering the initial tungsten interconnect structure exposed in the second dielectric layer in step S5. The bonding layer acts as a barrier layer, blocking the connection between the weak interface between the second dielectric layer and the initial tungsten interconnect structure and the space above the bonding layer. Thus, during the chemical mechanical planarization process in step S7, the grinding liquid can be effectively prevented from penetrating into the zero-layer cobalt interconnect structure through the weak interface, thereby avoiding corrosion of the zero-layer cobalt interconnect structure by the grinding liquid. This solves the problem of cobalt deficiency in the metal interconnect structure. Furthermore, the resulting metal interconnect structure does not require a bonding layer, significantly reducing contact resistance.

[0016] Optionally, the step of removing the tungsten sacrificial layer, a portion of the bonding layer, and a portion of the initial tungsten interconnect structure by using a chemical mechanical planarization process in step S7 until the bonding layer located on the upper surface of the second dielectric layer is exposed includes:

[0017] S71: performing a first chemical mechanical planarization process, and stopping at a first position in a time-controlled manner to remove a portion of the tungsten sacrificial layer and a portion of the bonding layer, wherein the first position is a position where the initial tungsten interconnect structure is exposed;

[0018] S72: Perform a second step of chemical mechanical planarization treatment and stop at a second position using an endpoint control method to remove the remaining portion of the tungsten sacrificial layer, part of the bonding layer and part of the initial tungsten interconnect structure. The second position is a position where the bonding layer located on the upper surface of the second dielectric layer is exposed.

[0019] Optionally, in step S71, the distance between the first position and the upper surface of the adhesive layer located on the second dielectric layer is 150-200 Å.

[0020] Optionally, the step of removing the bonding layer on the upper surface of the second dielectric layer in step S8 includes: controlling the ratio of the removal rate of the bonding layer to the removal rate of metal tungsten to be greater than 5:1, and making the thickness of the etched second dielectric layer less than 50A.

[0021] Optionally, the step of removing part of the dielectric material of the through-hole layer in step S4 includes: controlling the ratio of the removal rate of the dielectric material and the removal rate of metal tungsten to be greater than 50:1, and making the height difference between the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure 200-300A.

[0022] Optionally, in step S3, a height difference between an upper surface of the initial tungsten interconnect structure and an upper surface of the through-hole layer is 0-200 Å.

[0023] Optionally, the step of performing the first chemical mechanical planarization treatment in step S71 includes controlling the ratio of the removal rate of the metal tungsten to the removal rate of the bonding layer to be 0.7:1 to 1:1.

[0024] Optionally, the step of performing the second chemical mechanical planarization treatment in step S72 includes controlling the ratio of the removal rate of the metal tungsten to the removal rate of the bonding layer to be greater than 10:1.

[0025] Optionally, in step S6, the thickness of the formed tungsten sacrificial layer is 1000-2000 Å.

[0026] Optionally, in step S5, the bonding layer is deposited on the upper surface of the second dielectric layer and the surface of the initial tungsten interconnect structure by using a corner filling method.

[0027] Optionally, the semiconductor device of the present invention includes a substrate, a metal wiring structure is provided on the upper surface of the substrate, and the metal wiring structure is prepared by using the preparation method of the metal wiring structure.

[0028] The beneficial effect of the semiconductor device of the present invention is that: the metal wiring structure is prepared using the metal wiring structure preparation method, so that during the chemical mechanical planarization process, the grinding liquid can be effectively prevented from penetrating into the zero-layer cobalt interconnect structure through the weak interface between the dielectric layer and the initial tungsten interconnect structure, thereby avoiding the grinding liquid from corroding the zero-layer cobalt interconnect structure, solving the problem of cobalt deficiency in the metal wiring structure of the semiconductor device, and no bonding layer is required in the metal wiring structure, thereby greatly reducing the contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A cross-sectional view of a metal wiring structure after chemical mechanical polishing in the prior art;

[0030] Figure 2 is a flow chart of a method for preparing a metal wiring structure according to an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of a structure obtained after forming a first dielectric layer having a zero-layer cobalt interconnect structure on a substrate according to an embodiment of the present invention;

[0032] Figure 4 For Figure 3 A schematic diagram of the structure obtained after a through-hole layer is formed on the structure shown;

[0033] Figure 5 For Figure 4 Schematic diagram of the structure obtained after forming an initial tungsten interconnect structure on the structure shown;

[0034] Figure 6 For Figure 5 A schematic diagram of a structure obtained after forming a second dielectric layer on the structure shown;

[0035] Figure 7 For Figure 6 A schematic diagram of the structure obtained after forming an adhesive layer on the structure shown;

[0036] Figure 8 For Figure 7 Schematic diagram of the structure obtained after forming a tungsten sacrificial layer on the structure shown;

[0037] Figure 9 For Figure 8 Schematic diagram of the structure obtained after the first step of chemical mechanical planarization treatment of the structure shown;

[0038] Figure 10 For Figure 9 Schematic diagram of the structure obtained after the second step of chemical mechanical planarization treatment of the structure shown;

[0039] Figure 11 For Figure 10 Schematic diagram of the structure obtained after removing the bonding layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0041] Figure 1 This is a cross-sectional view of a metal wiring structure after chemical mechanical polishing in the prior art.

[0042] refer to Figure 1 In the prior art, the tungsten interconnect layer 11 prepared by the selective tungsten deposition process lacks a bonding layer, resulting in an insufficiently dense bond between the tungsten interconnect layer 11 and the dielectric layer 12. In the subsequent tungsten chemical mechanical polishing process, the metal tungsten polishing liquid 13 will penetrate into the cobalt interconnect layer 14 through the weak connection between the tungsten interconnect layer 11 and the dielectric layer 12. Since cobalt and tungsten have opposite potential-pH characteristics, the metal cobalt corrodes rapidly under the erosion of the acidic tungsten polishing liquid, resulting in cobalt deficiency in the cobalt interconnect layer 14. Figure 1 shown.

[0043] To overcome the problems existing in the prior art, embodiments of the present invention provide a method for preparing a metal wiring structure and a semiconductor device, thereby preventing the polishing liquid from penetrating into the zero-layer cobalt interconnect structure through the weak interface between the dielectric layer and the initial tungsten interconnect structure, avoiding the polishing liquid from corroding the zero-layer cobalt interconnect structure, solving the problem of cobalt deficiency in the metal wiring structure, and eliminating the need for an adhesive layer in the prepared metal wiring structure, thereby greatly reducing the contact resistance.

[0044] Figure 2 Flowchart of a method for preparing a metal wiring structure according to an embodiment of the present invention.

[0045] In some embodiments of the present invention, the method for preparing the metal wiring structure is as follows: Figure 2 , including the following steps:

[0046] S1: providing a first dielectric layer having a zero-layer cobalt interconnect structure;

[0047] S2: forming a patterned through-hole layer on the upper surface of the first dielectric layer, and allowing the through-hole structure in the through-hole layer to penetrate the through-hole layer to the surface of the zero-layer cobalt interconnect structure;

[0048] S3: filling metal tungsten into the through-hole structure to form an initial tungsten interconnection structure, and making the upper surface of the initial tungsten interconnection structure no lower than the upper surface of the through-hole layer;

[0049] S4: removing a portion of the dielectric material of the through-hole layer to form a second dielectric layer, and making the upper surface of the second dielectric layer lower than the upper surface of the initial tungsten interconnect structure;

[0050] S5: depositing an adhesive layer on the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure, and allowing the adhesive layer to cover the initial tungsten interconnect structure exposed on the second dielectric layer;

[0051] S6: depositing metal tungsten on the upper surface of the bonding layer to form a tungsten sacrificial layer;

[0052] S7: removing the tungsten sacrificial layer, a portion of the bonding layer, and a portion of the initial tungsten interconnect structure using a chemical mechanical planarization process until the bonding layer located on the upper surface of the second dielectric layer is exposed;

[0053] S8: removing the adhesive layer on the upper surface of the second dielectric layer until the second dielectric layer is exposed, thereby forming a tungsten interconnect structure.

[0054] Specifically, the present invention aims to provide a method for forming a metal cobalt interconnect layer and a contact hole layer, which is used to solve the problem of cobalt deficiency. The method partially fills the through-hole structure in the through-hole layer, and then exposes the initial tungsten interconnect structure within the partial through-hole structure through a dielectric layer etching back process. This facilitates the bonding layer deposited in step S5 to completely cover the initial tungsten interconnect structure exposed in the second dielectric layer. The bonding layer acts as a barrier layer, blocking the weak interface between the second dielectric layer and the initial tungsten interconnect structure from the space above the bonding layer. Consequently, during the chemical mechanical planarization process in step S7, the weak interface between the second dielectric layer and the initial tungsten interconnect structure is not exposed, effectively preventing the polishing fluid from penetrating the zero-layer cobalt interconnect structure through the weak interface, thus avoiding polishing fluid corrosion of the zero-layer cobalt interconnect structure. This solves the problem of cobalt deficiency in the metal wiring structure, and further eliminates the need for a bonding layer in the resulting metal wiring structure, significantly reducing contact resistance.

[0055] Figure 3 This is a schematic diagram of a structure obtained after forming a first dielectric layer having a zero-layer cobalt interconnect structure on a substrate according to an embodiment of the present invention.

[0056] In some specific embodiments of the present invention, the step of providing a first dielectric layer having a zero-layer cobalt interconnect structure in step S1 includes:

[0057] refer to Figure 3 , a first dielectric layer 120 is grown on the upper surface of the substrate 110; a zero-layer interconnection groove (not shown in the figure) is formed in the first dielectric layer 120 by dry etching; metal cobalt is deposited in the zero-layer interconnection groove (not shown in the figure), and a zero-layer cobalt interconnection structure 130 is formed by mechanical chemical polishing, and the upper surface of the zero-layer cobalt interconnection structure 130 is flush with the upper surface of the first dielectric layer 120. The obtained structure is as follows Figure 3 shown.

[0058] Figure 4 For Figure 3 Schematic diagram of the structure obtained after a through-hole layer is formed on the structure shown.

[0059] In some specific embodiments of the present invention, the step of forming a patterned via layer on the upper surface of the first dielectric layer in step S2, and allowing the via structure in the via layer to penetrate the via layer to the surface of the zero-layer cobalt interconnect structure includes:

[0060] refer to Figure 4, depositing an initial dielectric layer (not shown) on the upper surface of the zero-layer cobalt interconnect structure 130 and the upper surface of the first dielectric layer 120; performing a standard photolithography etching process on the initial dielectric layer (not shown) to form a patterned through-hole layer 140, and making the through-hole structure 141 in the through-hole layer 140 pass through the through-hole layer 140 to the upper surface of the zero-layer cobalt interconnect structure 130, and the obtained structure is as shown Figure 4 shown.

[0061] In some embodiments of the present invention, the dielectric material of the through-hole layer is at least one of silicon oxide and silicon nitride.

[0062] In some possible embodiments of the present invention, the initial dielectric layer is a single-layer structure or a multi-layer structure. Specifically, the initial dielectric layer includes any one of a silicon oxide layer, a silicon nitride layer, and a stacked layer of silicon oxide and silicon nitride.

[0063] In some specific embodiments of the present invention, reference Figure 4 The initial dielectric layer (not shown) includes a silicon nitride layer 142 and a silicon oxide layer 143 , and the through-hole structure 141 sequentially penetrates the silicon oxide layer 143 and the silicon nitride layer 142 until it abuts against the upper surface of the zero-layer cobalt interconnect structure 130 .

[0064] Figure 5 For Figure 4 Schematic diagram of the structure obtained after forming an initial tungsten interconnect structure on the structure shown.

[0065] In some specific embodiments of the present invention, the step of filling metal tungsten in the through-hole structure to form an initial tungsten interconnect structure, and making the upper surface of the initial tungsten interconnect structure no lower than the upper surface of the through-hole layer in step S3 includes:

[0066] refer to Figure 4 and Figure 5 , metal tungsten is deposited on the through-hole layer 140 so that the metal tungsten fills the through-hole structure 141 in the through-hole layer 140 to form an initial tungsten interconnect structure 150, and the upper surface of the initial tungsten interconnect structure 150 is not lower than the upper surface of the through-hole layer 140. The obtained structure is as follows Figure 5 There is a weak interface 145 between the initial tungsten interconnect structure 150 and either the silicon nitride layer 142 or the silicon oxide layer 143 .

[0067] In some possible embodiments of the present invention, in step S3, a selective tungsten deposition process is used to fill the through-hole structure with metal tungsten, so that an adhesive layer is not required in the obtained metal wiring structure, thereby greatly reducing contact resistance.

[0068] In some embodiments of the present invention, in step S3, a height difference between an upper surface of the initial tungsten interconnect structure and an upper surface of the through-hole layer is 0-200 Å.

[0069] In some specific embodiments of the present invention, reference Figure 5 The upper surface of the initial tungsten interconnect structure 150 is flush with the upper surface of the through-hole layer 140 .

[0070] Figure 6 For Figure 5 Schematic diagram of the structure obtained after forming a second dielectric layer on the structure shown.

[0071] In some specific embodiments of the present invention, reference Figure 5 and Figure 6 In step S4, a selective removal process is used to remove part of the dielectric material of the through-hole layer 140 to form a second dielectric layer 144. The resulting structure is as follows: Figure 6 Specifically, after removing a portion of the silicon oxide layer 143 , the second dielectric layer 144 formed includes the silicon nitride layer 142 and the remaining portion of the silicon oxide layer 143 . Furthermore, the upper surface of the second dielectric layer 144 is lower than the upper surface of the initial tungsten interconnect structure 150 .

[0072] In some possible embodiments of the present invention, the selective removal process includes a dry etching process, a wet etching process, an ion etching process, or the like.

[0073] In some possible embodiments of the present invention, the step of removing a portion of the dielectric material of the through-hole layer to form the second dielectric layer in step S4 includes:

[0074] The ratio of the dielectric material removal rate to the metal tungsten removal rate is controlled to be greater than 50:1, and the height difference between the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure is 200-300 Å. That is, the thickness of the dielectric material of the through-hole layer is controlled to be 200-300 Å, so that the height of the initial tungsten interconnect structure exposed in the second dielectric layer is greater than 200 Å, thereby facilitating the bonding layer to completely cover the initial tungsten interconnect structure exposed in the second dielectric layer, achieving a better covering effect, and enabling the bonding layer to better prevent the polishing liquid from penetrating into the weak interface between the second dielectric layer and the initial tungsten interconnect structure during chemical mechanical planarization.

[0075] Specifically, in step S4, the ratio of the removal rate of the dielectric material in the through-hole layer to the removal rate of the metal tungsten in the initial tungsten interconnect structure is controlled to be greater than 50:1.

[0076] In some specific embodiments of the present invention, in step S4, in which a portion of the dielectric material of the through-hole layer is removed to form the second dielectric layer, the ratio of the removal rate of the dielectric material to the removal rate of the metal tungsten is controlled to be 50:1.

[0077] Figure 7 For Figure 6 Schematic diagram of the structure obtained after forming a bonding layer on the structure shown.

[0078] In some specific embodiments of the present invention, in step S5, the step of depositing an adhesive layer on the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure, and allowing the adhesive layer to cover the initial tungsten interconnect structure exposed from the second dielectric layer includes:

[0079] refer to Figure 7 The bonding layer 160 is deposited on the upper surface of the second dielectric layer 144 and the surface of the initial tungsten interconnect structure 150 by using a corner filling method. The bonding layer 160 is deposited by using a corner filling method to completely cover the initial tungsten interconnect structure 150 exposed on the second dielectric layer 144. The resulting structure is as shown in FIG. Figure 7 As shown, the bonding layer 160 is also provided on the upper surface of the weak interface 145 between the second dielectric layer 144 and the initial tungsten interconnect structure 150. The bonding layer 160 acts as a barrier layer, preventing the polishing liquid from entering the weak interface 145 during the chemical mechanical planarization process in step S7, thereby protecting the zero-layer cobalt interconnect structure 130. Furthermore, the bonding layer 160 also serves as a bonding layer for the chemical vapor deposition of metal tungsten in step S6.

[0080] In some embodiments of the present invention, the corner filling method includes but is not limited to atomic layer deposition process, chemical vapor deposition process, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc.

[0081] In some embodiments of the present invention, the material of the bonding layer includes TiN, TaN, etc.

[0082] Figure 8 For Figure 7 Schematic diagram of the structure obtained after forming a tungsten sacrificial layer on the structure shown.

[0083] In some specific embodiments of the present invention, in step S6, the step of depositing metal tungsten on the upper surface of the bonding layer to form a tungsten sacrificial layer includes:

[0084] refer to Figure 8 , metal tungsten is deposited on the upper surface of the bonding layer 160 to form a tungsten sacrificial layer 170, and the resulting structure is as follows Figure 8The tungsten sacrificial layer 170 serves as a planarization layer in the subsequent chemical mechanical planarization process. Specifically, the deposition method of the deposited metal tungsten includes but is not limited to atomic layer deposition, chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation, etc.

[0085] In some possible embodiments of the present invention, in step S6, the thickness of the tungsten sacrificial layer formed is 1000-2000 Å, so as to facilitate subsequent chemical mechanical planarization treatment.

[0086] Figure 9 For Figure 8 Schematic diagram of the structure obtained after the first step of chemical mechanical planarization treatment of the structure shown; Figure 10 For Figure 9 Schematic diagram of the structure obtained after the second step of chemical mechanical planarization treatment of the structure shown.

[0087] In some embodiments of the present invention, in step S7, the step of removing the tungsten sacrificial layer, a portion of the bonding layer, and a portion of the initial tungsten interconnect structure by a chemical mechanical planarization process until the bonding layer located on the upper surface of the second dielectric layer is exposed includes: Figures 8 to 10 :

[0088] S71: Perform the first step of chemical mechanical planarization and stop at the first position 171 in a time-controlled manner to remove part of the tungsten sacrificial layer 170 and part of the bonding layer 160. The first position 171 is where the initial tungsten interconnect structure 150 is exposed. The resulting structure is as shown in FIG. Figure 9 As shown;

[0089] S72: Perform a second chemical mechanical planarization process, and use an endpoint control method to stop at the second position to remove the remaining portion of the tungsten sacrificial layer 170, part of the bonding layer 160 and part of the initial tungsten interconnect structure 150. The second position is the position where the bonding layer 160 on the upper surface of the second dielectric layer 144 is exposed. The resulting structure is as shown in FIG. Figure 10 shown.

[0090] During the entire chemical mechanical planarization process in step S7, the bonding layer 160 on the upper surface of the second dielectric layer 144 and the upper surface of the weak interface 145 will not be removed. The bonding layer 160 can well cover the upper surface of the weak interface 145, preventing the polishing liquid from entering the weak interface 145 during the chemical mechanical planarization process, thereby protecting the zero-layer cobalt interconnect structure 130.

[0091] In some embodiments of the present invention, in step S71, the distance between the first position 171 and the upper surface of the bonding layer 160 located on the second dielectric layer 144 is 150-200 Å. This facilitates the second step of chemical mechanical planarization and helps improve control accuracy. That is, in some embodiments, the first step of chemical mechanical planarization removes a portion of the initial tungsten interconnect structure.

[0092] In some specific embodiments of the present invention, in step S71, the first chemical mechanical planarization treatment removes all structures located above the first position 171, including part of the tungsten sacrificial layer 170 and the bonding layer 160 located on the upper surface of the initial tungsten interconnect structure 150.

[0093] In some other specific embodiments of the present invention, in step S71, the first chemical mechanical planarization treatment removes all structures located above the first position 171, including part of the tungsten sacrificial layer 170, the bonding layer 160 located on the upper surface of the initial tungsten interconnect structure 150, part of the initial tungsten interconnect structure 150, and the bonding layer 160 covering the side walls of the part of the initial tungsten interconnect structure 150.

[0094] In some possible embodiments of the present invention, the step of performing the first chemical mechanical planarization process in step S71 includes controlling the ratio of the removal rate of the metal tungsten to the removal rate of the bonding layer to be between 0.7:1 and 1:1. Specifically, in some embodiments, the metal tungsten is the metal tungsten in the tungsten sacrificial layer. In other embodiments, the metal tungsten is the metal tungsten in the tungsten sacrificial layer and the initial tungsten interconnect structure.

[0095] In some specific embodiments of the present invention, the step of performing the first step of chemical mechanical planarization in step S71 includes: controlling the ratio of the removal rate of metal tungsten to the removal rate of the bonding layer to be 1:1, and the distance between the first position and the upper surface of the bonding layer located on the second dielectric layer is 200A.

[0096] In some possible embodiments of the present invention, performing a second chemical mechanical planarization process in step S72 includes controlling a ratio of a removal rate of the metal tungsten to a removal rate of the bonding layer to be greater than 10:1. Specifically, the metal tungsten is the metal tungsten in the sacrificial tungsten layer and the initial tungsten interconnect structure. Removal of the bonding layer located on the upper surface of the second dielectric layer is avoided.

[0097] In some specific embodiments of the present invention, the step of performing the second chemical mechanical planarization process in step S72 includes controlling the ratio of the removal rate of the metal tungsten to the removal rate of the bonding layer to be 10:1. Specifically, a polishing slurry having a ratio of the removal rate of the metal tungsten to the removal rate of the bonding layer of 10:1 is used, and endpoint control is used to stop at a position where the bonding layer on the upper surface of the second dielectric layer is exposed.

[0098] Figure 11 For Figure 10 Schematic diagram of the structure obtained after removing the bonding layer.

[0099] In some specific embodiments of the present invention, in step S8, the step of removing the adhesive layer on the upper surface of the second dielectric layer until the second dielectric layer is exposed to form the tungsten interconnect structure includes:

[0100] refer to Figure 10 and Figure 11 , the adhesive layer 160 on the upper surface of the second dielectric layer 144 is removed by dry etching or wet etching to expose the second dielectric layer 144 and form a tungsten interconnect structure 151. The obtained structure is as shown in FIG. Figure 11 shown.

[0101] In some possible embodiments of the present invention, the step of removing the bonding layer on the upper surface of the second dielectric layer in step S8 includes controlling the ratio of the bonding layer removal rate to the metal tungsten removal rate to be greater than 5:1, and ensuring that the thickness of the etched second dielectric layer is less than 50 Å. Specifically, the metal tungsten is the metal tungsten in the initial tungsten interconnect structure. The bonding layer removal rate is greater than the metal tungsten removal rate, so that the upper surface of the prepared tungsten interconnect structure is equal to or slightly higher than the upper surface of the second dielectric layer, thereby facilitating a closer connection between the tungsten interconnect structure and the structural layer disposed on the upper surface of the tungsten interconnect structure, improving contact reliability, and reducing contact resistance.

[0102] In some specific embodiments of the present invention, the step of removing the bonding layer on the upper surface of the second dielectric layer in step S8 includes: controlling the ratio of the removal rate of the bonding layer to the removal rate of metal tungsten to be 5:1, and making the thickness of the etched second dielectric layer less than 50A.

[0103] In some embodiments of the present invention, the semiconductor device includes a substrate having a metal interconnect structure disposed on its upper surface, the metal interconnect structure being prepared using the metal interconnect structure preparation method described in the above embodiments. This method effectively prevents the polishing fluid from penetrating into the zero-layer cobalt interconnect structure through the weak interface between the dielectric layer and the initial tungsten interconnect structure during chemical mechanical planarization, thereby preventing the polishing fluid from corroding the zero-layer cobalt interconnect structure. This solves the problem of cobalt deficiency in the metal interconnect structure of the semiconductor device, eliminates the need for an adhesive layer in the metal interconnect structure, and significantly reduces contact resistance.

[0104] In some embodiments of the present invention, the semiconductor device is a fin field effect transistor, which includes a substrate containing a transistor device structure, and a metal wiring structure is provided on the upper surface of the substrate. The metal wiring structure is prepared using the preparation method of the metal wiring structure described in the above embodiment.

[0105] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A method for preparing a metal wiring structure, characterized in that: The following steps are involved: S1: providing a first dielectric layer having a zero-layer cobalt interconnect structure; S2: forming a patterned through-hole layer on the upper surface of the first dielectric layer, and allowing the through-hole structure in the through-hole layer to penetrate the through-hole layer to the surface of the zero-layer cobalt interconnect structure; S3: filling metal tungsten into the through-hole structure to form an initial tungsten interconnection structure, and making the upper surface of the initial tungsten interconnection structure no lower than the upper surface of the through-hole layer; S4: removing a portion of the dielectric material of the through-hole layer to form a second dielectric layer, and making the upper surface of the second dielectric layer lower than the upper surface of the initial tungsten interconnect structure; S5: depositing an adhesive layer on the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure, and allowing the adhesive layer to cover the initial tungsten interconnect structure exposed on the second dielectric layer; S6: depositing metal tungsten on the upper surface of the bonding layer to form a tungsten sacrificial layer; S7: removing the tungsten sacrificial layer, a portion of the bonding layer, and a portion of the initial tungsten interconnect structure using a chemical mechanical planarization process until the bonding layer located on the upper surface of the second dielectric layer is exposed; S8: removing the adhesive layer on the upper surface of the second dielectric layer until the second dielectric layer is exposed, thereby forming a tungsten interconnect structure.

2. The method for preparing a metal wiring structure according to claim 1, wherein: The step of removing the tungsten sacrificial layer, a portion of the bonding layer, and a portion of the initial tungsten interconnect structure by a chemical mechanical planarization process in step S7 until the bonding layer located on the upper surface of the second dielectric layer is exposed includes: S71: performing a first chemical mechanical planarization process, and stopping at a first position in a time-controlled manner to remove a portion of the tungsten sacrificial layer and a portion of the bonding layer, wherein the first position is a position where the initial tungsten interconnect structure is exposed; S72: Perform a second step of chemical mechanical planarization treatment and stop at a second position using an endpoint control method to remove the remaining portion of the tungsten sacrificial layer, part of the bonding layer and part of the initial tungsten interconnect structure. The second position is a position where the bonding layer located on the upper surface of the second dielectric layer is exposed.

3. The method for preparing a metal wiring structure according to claim 2, wherein: In step S71 , the distance between the first position and the upper surface of the adhesive layer on the second dielectric layer is 150-200 Å.

4. The method for preparing a metal wiring structure according to claim 1, wherein: The step of removing the bonding layer on the upper surface of the second dielectric layer in step S8 includes controlling the ratio of the bonding layer removal rate to the metal tungsten removal rate to be greater than 5:1, and making the thickness of the etched second dielectric layer less than 50 Å.

5. The method for preparing a metal wiring structure according to claim 1, wherein: The step of removing part of the dielectric material of the through-hole layer in step S4 includes: controlling the ratio of the removal rate of the dielectric material to the removal rate of the metal tungsten to be greater than 50:1, and making the height difference between the upper surface of the second dielectric layer and the upper surface of the initial tungsten interconnect structure 200-300A.

6. The method for preparing a metal wiring structure according to claim 1, wherein: In step S3, the height difference between the upper surface of the initial tungsten interconnect structure and the upper surface of the through-hole layer is 0-200 Å.

7. The method for preparing a metal wiring structure according to claim 2, wherein: The step of performing the first chemical mechanical planarization treatment in step S71 includes: controlling the ratio of the removal rate of metal tungsten to the removal rate of the bonding layer to be 0.7:1 to 1:1; the step of performing the second chemical mechanical planarization treatment in step S72 includes: controlling the ratio of the removal rate of metal tungsten to the removal rate of the bonding layer to be greater than 10:

1.

8. The method for preparing a metal wiring structure according to claim 1, wherein: In the step S6, the thickness of the formed tungsten sacrificial layer is 1000-2000 Å.

9. The method for preparing a metal wiring structure according to claim 1, wherein: In the step S5, an adhesive layer is deposited on the upper surface of the second dielectric layer and the surface of the initial tungsten interconnect structure by using a corner filling method.

10. A semiconductor device, characterized in that: The invention comprises a substrate, wherein a metal wiring structure is provided on the upper surface of the substrate, and the metal wiring structure is prepared by the preparation method of the metal wiring structure according to any one of claims 1 to 9.

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