Shielded gate trench structure and method of making the same

Abstract

The application provides a shield gate trench structure and a preparation method thereof. Since a plurality of SBR devices are simultaneously integrated in an epitaxial layer corresponding to an active region of the shield gate trench structure, when the shield gate trench structure is normally working, the opening voltage of the thin gate oxide layer of the SBR device is lower than that of the PN junction formed between the epitaxial layer and the body region, so that when the device is turned off, the current of the parasitic capacitor is rapidly released from the barrier MOS channel of the SBR device, and the current does not pass through the parasitic PN junction, thereby greatly improving the reverse recovery characteristic of the device compared with the conventional SGTMOSFET device, effectively reducing the loss caused by the high opening voltage, reducing the switching loss in the high-frequency switching process, and finally achieving the purpose of improving the conversion efficiency of the direct-current-direct-current conversion control circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a shielding gate trench structure and its fabrication method. Background Technology

[0002] Currently, power MOSFETs are commonly used for power supply and load control in circuits. The smaller the on-resistance of the device, the larger the current it can carry. It is currently the product with the largest market capacity and the fastest growing demand among power semiconductor switching devices. Trench MOSFET technology is one of the most important technological drivers for achieving this goal. Initially, the invention of Trench MOSFET technology was to increase the channel density of planar devices to improve the current handling capability of the devices. However, the improved new Trench MOSFET structure can not only reduce the channel density, but also further reduce the drift region resistance. The main goals of the development of Trench MOSFET technology are: (1) to reduce the forward on-resistance to reduce static power loss; (2) to increase the switching speed to reduce transient power loss.

[0003] Currently, in DC-DC conversion control circuits that include two MOSFETs (referred to as M1 and M2) as the core switching devices, DC-DC conversion is achieved through a control chip. However, M1 and M2 themselves suffer from parasitic diodes formed by the P-type well / drain regions surrounding their sources. Therefore, to effectively reduce high-frequency switching losses and improve the DC conversion efficiency of the DC-DC conversion control circuit, the existing technology involves connecting a Schottky diode (SBD) in parallel between the source (S) and drain (D) of MOSFET M1. This utilizes the characteristic that the threshold voltage of the Schottky diode (SBD) (around 0.3V) is lower than the threshold voltage of the parasitic diode (around 0.7V for PN junction diodes) to reduce losses caused by high turn-on voltage, thereby effectively reducing switching losses during high-frequency switching and improving conversion efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a shielded gate trench structure and its fabrication method. By integrating multiple gate oxide layers (thin oxide layers) in the active region to form a short-channel SBR device that is thinner than the SGT MOSFET device, the turn-on voltage of the thin gate oxide layer of the SBR device is lower than the turn-on voltage of the PN junction formed between the epitaxial layer and the body region. This effectively reduces the losses caused by the high turn-on voltage, thereby effectively reducing the switching losses in the high-frequency switching process, and ultimately improving the conversion efficiency of the DC-DC conversion control circuit.

[0005] Firstly, to solve the above-mentioned technical problems, this invention provides a method for fabricating a shielded gate trench structure, which can be specifically applied to a DC-DC conversion control circuit where a MOSFET is used as a switching device. The fabrication method includes at least the following steps:

[0006] A semiconductor substrate having an epitaxial layer is provided, the semiconductor substrate including at least an active region;

[0007] In the epitaxial layer corresponding to the active region, at least a gate trench, a first short channel trench, a MOS transistor trench, and a second short channel trench are formed sequentially from left to right. A shielding gate dielectric layer, a shielding gate filling the lower space, and an isolation dielectric layer covering the shielding gate dielectric layer and the top surface of the shielding gate are formed on the inner surface of the lower space of all the formed trenches.

[0008] A thick oxide layer and a gate polysilicon layer filling the remaining space of the gate trench and the MOS trench are formed on the inner walls of the upper space exposed by the gate trench and the MOS trench; and a thin oxide layer and a polysilicon layer filling the remaining space of the first short channel trench and the second short channel trench are formed on the two inner walls of the upper space exposed by the first short channel trench and the second short channel trench.

[0009] Furthermore, the thickness range of the thin oxide layer can specifically be: In this embodiment, the preferred thickness of the thin oxide layer is...

[0010] Furthermore, the thickness range of the thick oxide layer can specifically be: In this embodiment, the preferred thickness of the thick oxide layer is...

[0011] Furthermore, the polysilicon layer formed in the first short channel trench and the second short channel trench can specifically serve as an SBR device.

[0012] Furthermore, after forming the polycrystalline silicon layer in the remaining space of the first short trench and the second short trench, the preparation method provided in this embodiment of the invention may further include the following steps:

[0013] An ion implantation process is performed on the epitaxial layer between two adjacent trenches to form a bulk region within the epitaxial layer;

[0014] An ion implantation process is performed on the surface layer of the body region between the first short channel trench, the MOS transistor trench, and the second short channel trench to form the source of the MOS transistor in the body region on both sides of the MOS transistor trench.

[0015] Furthermore, the conductivity type of the epitaxial layer needs to be opposite to that of the body region.

[0016] Furthermore, after forming the source electrode, the preparation method provided in this embodiment of the invention may further include the following steps:

[0017] An interlayer dielectric layer is formed on the surface of the semiconductor substrate;

[0018] The interlayer dielectric layer is etched to form first conductive plugs within the interlayer dielectric layer for electrically connecting the source, the first short-channel trench, and the second short-channel trench to the polysilicon layer.

[0019] A metal layer is formed on the top surface of the interlayer dielectric layer corresponding to the first short-channel trench, the MOS trench, and the second short-channel trench, so as to connect the first conductive plugs for electrically externally connecting the polysilicon layer in the source, the first short-channel trench, and the second short-channel trench in parallel.

[0020] Furthermore, the ratio of the number of short-channel trenches formed in the epitaxial layer corresponding to the active region for forming the SBR device to the total number of trenches formed in the epitaxial layer corresponding to the active region can specifically be 10% to 15%.

[0021] Furthermore, after forming the isolation medium layer located within all the trenches, the preparation method provided in this embodiment of the invention may further include the following steps:

[0022] Stacked thin oxide layers, silicon nitride layers, and first oxide layers are formed on the inner surface of the upper space exposed by all the trenches and on the surface of the epitaxial layer between adjacent trenches;

[0023] A photoresist layer is formed to shield the epitaxial layers corresponding to the first short channel trench and the second short channel trench, so as to remove the exposed gate trench and the first oxide layer in the MOS transistor trench;

[0024] Remove the photoresist layer and etch away the silicon nitride layer and thin oxide layer in the gate trench and the MOS trench to expose the inner surface of the upper space of the gate trench and the MOS trench;

[0025] The thick oxide layer is formed on the two sidewalls of the exposed upper space.

[0026] Furthermore, while etching away the silicon nitride layer and thin oxide layer in the gate trench and the MOS transistor trench, the first oxide layer formed in the first short channel trench and the second short channel trench can also be etched away.

[0027] Furthermore, after forming the thick oxide layer on the two sidewalls of the exposed upper space, the preparation method provided in this embodiment of the invention may further include the following steps: removing the silicon nitride layer exposed in the first short channel trench and the second short channel trench.

[0028] Furthermore, while etching the interlayer dielectric layer to form the first conductive plug, a second conductive plug for electrically connecting the gate polysilicon layer in the gate trench can also be formed in the interlayer dielectric layer, and the formed metal layer can also extend to cover the top surface of the interlayer dielectric layer corresponding to the gate trench.

[0029] Furthermore, after forming the metal layer, the preparation method provided in this embodiment of the invention may further include the following steps: etching away the metal layer on the surface of the interlayer dielectric layer corresponding to the gate trench and the first short channel trench, so that the metal layer covering the gate trench electrically leads out only the second conductive plug.

[0030] Secondly, based on the same inventive concept as the method for preparing the shielded gate trench structure, the present invention also provides a shielded gate trench structure for use in DC-DC conversion control circuits where MOS transistors are used as switching devices. Specifically, it can be prepared using the method for preparing the shielded gate trench structure as described above, and the specific preparation method will not be repeated here.

[0031] In this context, multiple SBR devices are also integrated within the epitaxial layer corresponding to the active region that forms the shielding gate trench structure.

[0032] Furthermore, the ratio of the number of short-channel trenches used to form SBR devices in the epitaxial layer corresponding to the active region to the total number of trenches formed in the epitaxial layer corresponding to the active region is 10% to 15%.

[0033] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0034] This invention proposes a shielded gate trench structure, wherein multiple SBR devices are simultaneously integrated within the epitaxial layer corresponding to the active region forming the shielded gate trench structure. This allows the shielded gate trench structure provided by this invention to utilize the characteristic that the turn-on voltage of the thin gate oxide layer of the SBR device is lower than the turn-on voltage of the PN junction formed between the epitaxial layer and the body region during normal operation. This ensures that when the device is turned off, the parasitic capacitance current is rapidly released from the barrier MOS channel of the SBR device without passing through the parasitic PN junction. Consequently, the reverse recovery characteristics of the device are significantly superior to those of traditional SGT MOSFET devices, effectively reducing losses caused by high turn-on voltage, lowering switching losses during high-frequency switching, and ultimately improving the conversion efficiency of the DC-DC conversion control circuit.

[0035] Furthermore, in the shielding gate trench structure of the short-channel SBR device that integrates multiple gate oxide layers (thin oxide layers) in the active region of the present invention, which is thinner than the SGTMOSFET device, the ratio of the number of short-channel trenches used to form the SBR device in the epitaxial layer corresponding to the active region to the total number of trenches formed in the epitaxial layer corresponding to the active region is 10% to 15%. This achieves a reduction in switching losses during high-frequency switching without affecting the functionality of the shielding gate trench structure itself.

[0036] Furthermore, the present invention also provides a method for fabricating a shielded gate trench structure. This involves first forming multiple short-channel trenches in the epitaxial layer corresponding to the active region for subsequent SBR device formation. Then, a thin oxide layer is formed on the inner walls of both sides of the upper space of the short-channel trench. This thin oxide layer is thinner than the gate oxide layer on the inner walls of the upper space of the gate trench in the active region, which serves to lead out the gate of the MOS transistor. This allows the use of the characteristic that the turn-on voltage of the thin gate oxide layer of the SBR device is lower than the turn-on voltage of the PN junction formed between the epitaxial layer and the body region. This reduces losses caused by high turn-on voltage, thereby lowering switching losses during high-frequency switching, ultimately improving the conversion efficiency of the DC-DC conversion control circuit. Attached Figure Description

[0037] Figure 1 This is a schematic flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention.

[0038] Figures 2 to 10 This is a schematic diagram of the semiconductor structure fabrication method in one embodiment of the present invention during its fabrication process.

[0039] The reference numerals in the attached figures are as follows:

[0040] 100 - Semiconductor substrate; 110 - Epitaxial layer;

[0041] 120 - Shielding barrier dielectric layer; 130 - Shielding barrier;

[0042] 140 - Isolation dielectric layer; 150 - Thin oxide layer;

[0043] 160 - Silicon nitride layer; 170 - First oxide layer;

[0044] 180 - Photoresist layer; 190 - Thick oxide layer;

[0045] 200 - Interlayer dielectric layer; 210 - Metal layer

[0046] AA - Active region; S - Source electrode;

[0047] 101 - Gate trench; 102 - First short channel trench;

[0048] 103 - MOS transistor trench; 104 - Second short channel trench;

[0049] G-gate polysilicon layer; Polysilicon layer of Spoly-SBR device;

[0050] CT1 - First conductive plug; CT2 - Second conductive plug. Detailed Implementation

[0051] As described in the background section, in current DC-DC conversion control circuits that include two MOSFETs (M1 and M2) as core switching devices, DC-DC conversion is achieved through a control chip. However, M1 and M2 themselves suffer from parasitic diodes formed by the P-type well / drain regions surrounding their sources. Therefore, to effectively reduce high-frequency switching losses and improve the DC conversion efficiency of the DC-DC conversion control circuit, the existing approach is to connect a Schottky diode (SBD) in parallel between the source (S) and drain (D) of MOSFET M1. This utilizes the fact that the threshold voltage of the Schottky diode (SBD) (around 0.3V) is lower than the threshold voltage of the parasitic diode (around 0.7V for PN junction diodes) to reduce losses caused by high turn-on voltage, thereby effectively reducing switching losses during high-frequency switching and improving conversion efficiency.

[0052] To this end, the present invention provides a shielded gate trench structure and its fabrication method. By integrating multiple gate oxide layers (thin oxide layers) in the active region to form a short-channel SBR device that is thinner than the SGT MOSFET device, the turn-on voltage of the thin gate oxide layer of the SBR device is lower than the turn-on voltage of the PN junction formed between the epitaxial layer and the body region. This effectively reduces the losses caused by the high turn-on voltage, thereby effectively reducing the switching losses in the high-frequency switching process, and ultimately achieving the goal of improving the conversion efficiency of the DC-DC conversion control circuit.

[0053] See Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for fabricating a shielding trench structure according to an embodiment of the present invention. Figure 1 As shown, the method for preparing the shielding trench structure provided by the present invention may include at least the following steps:

[0054] Step S101: Provide a semiconductor substrate with an epitaxial layer, wherein the semiconductor substrate includes at least an active region.

[0055] In step S102, at least a gate trench, a first short channel trench, a MOS transistor trench, and a second short channel trench are formed sequentially from left to right in the epitaxial layer corresponding to the active region. A shielding gate dielectric layer, a shielding gate filling the lower space, and an isolation dielectric layer covering the shielding gate dielectric layer and the top surface of the shielding gate are formed on the inner surface of the lower space of all the formed trenches.

[0056] Step S103: A thick oxide layer and a gate polysilicon layer filling the remaining space of the gate trench and the MOS trench are formed on the inner walls of both sides of the upper space exposed by the gate trench and the MOS trench; and a thin oxide layer and a polysilicon layer filling the remaining space of the first short channel trench and the second short channel trench are formed on the inner walls of the upper space exposed by the first short channel trench and the second short channel trench.

[0057] The shielding trench structure and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0058] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0059] The following section first describes in detail the method for preparing a shielding grid trench structure provided by the present invention. Among other things, Figures 2 to 10 This is a schematic diagram of the fabrication process of the shielding trench structure in one embodiment of the present invention.

[0060] refer to Figure 2 In step S101 above, a semiconductor substrate 100 can be provided first. The semiconductor substrate 100 is used to provide an operating platform for the subsequent process to generate an SGT device with a shielded gate trench structure that integrates multiple SBR devices in the active region. The semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz, or a glass substrate. Exemplarily, in this embodiment, the semiconductor substrate 100 is, for example, a silicon wafer.

[0061] Next, an epitaxial process can be performed on the surface of the semiconductor substrate 100 to form an epitaxial layer 110 having a first conductivity type on the semiconductor substrate 100. As an example, the first conductivity type of the epitaxial layer 110 is N-type, and a region corresponding to the epitaxial layer 110 is used as the active region AA of the core device of the DC-DC conversion control circuit for forming the switching device.

[0062] See Figure 3In step S102 above, the epitaxial layer 110 can be etched using a process such as wet etching, dry etching, or a combination of both, to form multiple trenches within the epitaxial layer 110. Specifically, these trenches can be arranged from left to right as a gate trench 101, a first short-channel trench 102, a MOS transistor trench 103, and a second short-channel trench 104. Then, a shielding gate dielectric layer 120, a shielding gate 130 filling the lower space, and an isolation dielectric layer 140 covering the top surfaces of the shielding gate dielectric layer 120 and the shielding gate 130 are formed using a deposition process on the inner surfaces of the lower spaces of the gate trench 101, the first short-channel trench 102, the MOS transistor trench 103, and the second short-channel trench 104. The shielding gate dielectric layer 120 is made of silicon dioxide, the shielding gate 130 is made of polysilicon, and the isolation dielectric layer 140 is made of silicon dioxide.

[0063] It is understood that, in the embodiments of the present invention, only in order to simplify the drawings, are the figures shown. Figures 2 to 10 The image shows a portion of the integrated device corresponding to the active region AA. In other embodiments, the epitaxial layer 110 may also include a peripheral logic region (not shown) and a plurality of other gate trenches 101, first short channel trenches 102, MOS trenches 103 and second short channel trenches 104 formed within the epitaxial layer 110 corresponding to the active region AA.

[0064] It should be noted that, in this embodiment of the invention, the gate trench 101 is used to form the equivalent gate polysilicon layer of the MOS transistor, and then leads it out through an independent conductive plug (the second conductive plug), while the first short channel trench 102 and the second short channel trench 104 are used to form the SBR device, and the MOS transistor trench is used to form a MOS transistor with a shielded gate structure at the top and bottom.

[0065] As a preferred example, in this embodiment of the invention, the ratio of the number of short-channel trenches (102 and 104) formed in the epitaxial layer 110 corresponding to the active region AA for forming the SBR device to the number of all trenches (101, 102, 103, 104, etc.) formed in the epitaxial layer 110 corresponding to the active region AA is 10% to 15%, specifically 10%, 11%, 12%, 13%, 14%, 15%, etc.; in other words, the number of short-channel trenches forming the SBR device integrated on the active region AA accounts for only 10% to 15% of the total number of trenches formed on the active region AA. Obviously, in the shielding trench structure formed in the embodiment of the present invention, the ratio of the number of short channel trenches (102 and 104) used to form SBR devices in the epitaxial layer 110 corresponding to the active region AA to the total number of trenches formed in the epitaxial layer 110 corresponding to the active region AA is 10% to 15%, thereby reducing the switching loss in the high-frequency switching process without affecting the functionality that the shielding trench structure itself can achieve.

[0066] refer to Figure 4 After forming the isolation dielectric layer 140 within all the trenches in step S102, stacked thin oxide layers 150, silicon nitride layers 160, and first oxide layers 170 can be formed on the inner surfaces of the exposed upper spaces of all the trenches (101, 102, 103, and 104) and on the surfaces of the epitaxial layers 110 between adjacent trenches (101, 102, 103, and 104). The thin oxide layer 150 is made of silicon dioxide, and the first oxide layer 170 is also made of silicon dioxide.

[0067] The thickness range of the thin oxide layer 150 formed can be specifically as follows: Right now,

[0068] And the range formed by any two of the above numbers, including integers and decimals within it. As a preferred example, the thickness of the thin oxide layer 150 in the embodiment of the invention is...

[0069] refer to Figure 5 Next, a photoresist layer 180 is formed to shield the epitaxial layer 110 corresponding to the first short channel trench 102 and the second short channel trench 104, so as to remove the exposed first oxide layer 170 in the gate trench 101 and the MOS transistor trench 103.

[0070] refer to Figure 6The photoresist layer 180 is removed, and the silicon nitride layer 160 and thin oxide layer 150 in the gate trench 101 and the MOS transistor trench 103 are etched away to expose the inner surface of the upper space of the gate trench 101 and the MOS transistor trench 103.

[0071] It is understood that while etching away the silicon nitride layer 160 and the thin oxide layer 150 in the gate trench 101 and the MOS trench 103, the first oxide layer 170 formed in the first short channel trench 102 and the second short channel trench 104 is also etched away.

[0072] refer to Figure 7 A thick oxide layer 190 is formed on the two sidewalls of the exposed gate trench 101 and MOS transistor trench 103. The thickness of the thick oxide layer 190 can specifically be: Right now,

[0073] And the range formed by any two of the above numbers, including integers and decimals within it. As a preferred example, the thickness of the thick oxide layer 190 in the embodiment of the invention is...

[0074] refer to Figure 8 After forming the thick oxide layer 190 on the two sidewalls of the exposed upper space, the preparation method further includes removing the silicon nitride layer 160 exposed in the first short trench 102 and the second short trench 104.

[0075] See Figure 9 ,exist Figure 8 The structure shown deposits polysilicon to form a gate polysilicon layer G in the remaining space of the gate trench 101 and the MOS trench 103; and forms a polysilicon layer Spoly as an SBR device in the remaining space of the first short channel trench 102 and the second short channel trench 104, thus obtaining the structure described after the above step S103 is performed.

[0076] See Figure 10 After forming the polysilicon layer Spoly in the remaining space of the first short trench 102 and the second short trench 104 in step S103, the preparation method provided in this embodiment of the invention may further include: performing an ion implantation process on the epitaxial layer 110 between two adjacent trenches (101, 102, 103 and 104) to form a bulk region b in the epitaxial layer 110;

[0077] Next, an ion implantation process is performed on the surface layer of the body region b between the first short channel trench 102, the MOS transistor trench 103 and the second short channel trench 104 to form the source S of the MOS transistor in the body region b on both sides of the MOS transistor trench 103.

[0078] The conductivity type of the epitaxial layer 110 is opposite to that of the body region b. As a preferred example, in this embodiment of the invention, the conductivity type of the epitaxial layer 110 is N-type, and the conductivity type of the body region b is P-type.

[0079] Continue reading Figure 10 After forming the source S, the fabrication method provided in this embodiment of the invention may further include: forming an interlayer dielectric layer 200 on the surface of the semiconductor substrate 100; etching the interlayer dielectric layer 200 to form first conductive plugs CT1 within the interlayer dielectric layer 200 for electrically connecting the source S, the first short-channel trench 102, and the second short-channel trench 104 to the polysilicon layer Spoly; and...

[0080] At least on the top surface of the interlayer dielectric layer 200 corresponding to the first short channel trench 102, the MOS trench 103 and the second short channel trench 104, a metal layer 210 is formed to connect the first conductive plug CT1 of the polysilicon layer Spoly for electrically externally connecting the source S, the first short channel trench 102 and the second short channel trench 104 in parallel.

[0081] It is understood that, in the embodiments of the present invention, while etching the interlayer dielectric layer 200 to form the first conductive plug CT1, a second conductive plug CT2 for electrically connecting the gate polysilicon layer G in the gate trench 101 can also be formed in the interlayer dielectric layer 200, and the formed metal layer 210 also extends to cover the top surface of the interlayer dielectric layer 200 corresponding to the gate trench 101.

[0082] Subsequently, after forming the metal layer 210 covering the surfaces of the interlayer dielectric layer 200 corresponding to the gate trench 101, the first short-channel trench 102, the MOS trench 103, and the second short-channel trench 104, the metal layer 210 on the surface of the interlayer dielectric layer 200 between the gate trench 101 and the first short-channel trench 102 can be etched away. This allows the metal layer 210 covering the gate trench 101 to electrically lead out only the second conductive plug CT2, thereby enabling the shielding of the integrated multiple SBR devices to... When the MOS transistor in the active region of the gate trench structure is forward-biased, the forward turn-on voltage of the SBR device integrated on the active region AA is lower (or faster) than the turn-on voltage of the PN junction formed between the epitaxial layer 110 and the body region b. That is, the parasitic PN junction barrier voltage between the epitaxial layer 110 and the body region b is not reached, and the parasitic PN junction is not fully turned on. This effectively reduces the losses caused by the high turn-on voltage, thereby effectively reducing the switching losses in the high-frequency switching process, and ultimately achieving the goal of improving the conversion efficiency of the DC-DC conversion control circuit.

[0083] Furthermore, based on the same inventive concept as the fabrication method of the shielded gate trench structure, this invention also provides a shielded gate trench structure, specifically applied in a DC-DC conversion control circuit where a MOSFET is used as a switching device, and its fabrication method is as described above. Figures 2 to 10 The shielding trench structure shown is prepared using the same method.

[0084] Specifically, in the epitaxial layer corresponding to the active region of the shielding gate trench structure formed in the embodiments of the present invention, multiple SBR devices are also integrated simultaneously, such as... Figure 10 As shown, where Figure 10 The diagram shown is merely an example of a structural schematic of integrating two SBR devices within the active region AA.

[0085] In other embodiments, the ratio of the number of short-channel trenches used to form SBR devices in the epitaxial layer corresponding to the active region to the total number of trenches formed in the epitaxial layer corresponding to the active region specifically satisfies a relationship of 10% to 15%, which is within the protection scope of the embodiments of the present invention.

[0086] In summary, this invention proposes a shielded gate trench structure, wherein multiple SBR devices are simultaneously integrated within the epitaxial layer corresponding to the active region forming the shielded gate trench structure. This allows the shielded gate trench structure provided by this invention to utilize the characteristic that the turn-on voltage of the thin gate oxide layer of the SBR device is lower than the turn-on voltage of the PN junction formed between the epitaxial layer and the body region during normal operation. This ensures that when the device is turned off, the parasitic capacitance current is rapidly released from the barrier MOS channel of the SBR device without passing through the parasitic PN junction. Consequently, the reverse recovery characteristics of the device are significantly superior to those of traditional SGTMOSFET devices, effectively reducing losses caused by high turn-on voltage, lowering switching losses during high-frequency switching, and ultimately improving the conversion efficiency of the DC-DC conversion control circuit.

[0087] Furthermore, in the shielding gate trench structure of the short-channel SBR device that integrates multiple gate oxide layers (thin oxide layers) in the active region of the present invention, which is thinner than the SGTMOSFET device, the ratio of the number of short-channel trenches used to form the SBR device in the epitaxial layer corresponding to the active region to the total number of trenches formed in the epitaxial layer corresponding to the active region is 10% to 15%. This achieves a reduction in switching losses during high-frequency switching without affecting the functionality of the shielding gate trench structure itself.

[0088] Furthermore, the present invention also provides a method for fabricating a shielded gate trench structure. This involves first forming multiple short-channel trenches in the epitaxial layer corresponding to the active region for subsequent SBR device formation. Then, a thin oxide layer is formed on the inner walls of both sides of the upper space of the short-channel trench. This thin oxide layer is thinner than the gate oxide layer on the inner walls of the upper space of the gate trench in the active region, which serves to lead out the gate of the MOS transistor. This allows the use of the characteristic that the turn-on voltage of the thin gate oxide layer of the SBR device is lower than the turn-on voltage of the PN junction formed between the epitaxial layer and the body region. This reduces losses caused by high turn-on voltage, thereby lowering switching losses during high-frequency switching, ultimately improving the conversion efficiency of the DC-DC conversion control circuit.

[0089] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0090] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0091] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for preparing a shielding grid trench structure, characterized in that, The fabrication method, applied in DC-DC conversion control circuits using MOSFETs as switching devices, includes at least the following steps: A semiconductor substrate having an epitaxial layer is provided, the semiconductor substrate including at least an active region; In the epitaxial layer corresponding to the active region, at least a gate trench, a first short channel trench, a MOS transistor trench, and a second short channel trench are formed sequentially from left to right. A shielding gate dielectric layer, a shielding gate filling the lower space, and an isolation dielectric layer covering the shielding gate dielectric layer and the top surface of the shielding gate are formed on the inner surface of the lower space of all the formed trenches. A thick oxide layer and a gate polysilicon layer filling the remaining space of the gate trench and the MOS trench are formed on the inner walls of the upper space exposed by the gate trench and the MOS trench; and a thin oxide layer and a polysilicon layer filling the remaining space of the first short channel trench and the second short channel trench are formed on the two inner walls of the upper space exposed by the first short channel trench and the second short channel trench. The ratio of the number of the first short-channel trenches and the second short-channel trenches formed in the epitaxial layer corresponding to the active region for forming the SBR device to the total number of trenches formed in the epitaxial layer corresponding to the active region is 10% to 15%.

2. The method for preparing the shielding trench structure as described in claim 1, characterized in that, The thickness of the thin oxide layer ranges from 90 Å to 150 Å.

3. The method for preparing the shielding trench structure as described in claim 1, characterized in that, The thickness of the thick oxide layer ranges from 350 Å to 650 Å.

4. The method for preparing the shielding trench structure as described in claim 1, characterized in that, The polysilicon layer formed in the first short trench and the second short trench serves as the SBR device.

5. The method for preparing the shielding trench structure as described in claim 1, characterized in that, After forming a polycrystalline silicon layer in the remaining space of the first short-channel trench and the second short-channel trench, the fabrication method further includes: An ion implantation process is performed on the epitaxial layer between two adjacent trenches to form a bulk region within the epitaxial layer; An ion implantation process is performed on the surface layer of the body region between the first short channel trench, the MOS transistor trench, and the second short channel trench to form the source of the MOS transistor in the body region on both sides of the MOS transistor trench.

6. The method for preparing the shielding trench structure as described in claim 5, characterized in that, The conductivity type of the epitaxial layer is opposite to that of the body region.

7. The method for preparing the shielding trench structure as described in claim 5, characterized in that, After forming the source electrode, the preparation method further includes: An interlayer dielectric layer is formed on the surface of the semiconductor substrate; The interlayer dielectric layer is etched to form first conductive plugs within the interlayer dielectric layer for electrically connecting the source, the first short-channel trench, and the second short-channel trench to the polysilicon layer. A metal layer is formed on the top surface of the interlayer dielectric layer corresponding to the first short-channel trench, the MOS trench, and the second short-channel trench, so as to connect the first conductive plugs for electrically externally connecting the polysilicon layer in the source, the first short-channel trench, and the second short-channel trench in parallel.

8. The method for preparing the shielding trench structure as described in claim 1, characterized in that, After forming the insulating medium layer located within all the trenches, the preparation method further includes: Stacked thin oxide layers, silicon nitride layers, and first oxide layers are formed on the inner surface of the upper space exposed by all the trenches and on the surface of the epitaxial layer between adjacent trenches; A photoresist layer is formed to shield the epitaxial layers corresponding to the first short channel trench and the second short channel trench, so as to remove the exposed gate trench and the first oxide layer in the MOS transistor trench; Remove the photoresist layer and etch away the silicon nitride layer and thin oxide layer in the gate trench and the MOS trench to expose the inner surface of the upper space of the gate trench and the MOS trench; The thick oxide layer is formed on the two sidewalls of the exposed upper space.

9. The method for preparing the shielding trench structure as described in claim 8, characterized in that, While etching away the silicon nitride layer and thin oxide layer in the gate trench and the MOS transistor trench, the first oxide layer formed in the first short channel trench and the second short channel trench is also etched away.

10. The method for preparing the shielding trench structure as described in claim 9, characterized in that, After forming the thick oxide layer on the two sidewalls of the exposed upper space, the preparation method further includes: removing the silicon nitride layer exposed in the first short trench and the second short trench.

11. The method for preparing the shielding trench structure as described in claim 7, characterized in that, While etching the interlayer dielectric layer to form the first conductive plug, a second conductive plug for electrically connecting the gate polysilicon layer in the gate trench is also formed in the interlayer dielectric layer, and the formed metal layer extends to cover the top surface of the interlayer dielectric layer corresponding to the gate trench.

12. The method for preparing the shielding trench structure as described in claim 11, characterized in that, After forming the metal layer, the fabrication method further includes: etching away the metal layer on the surface of the interlayer dielectric layer corresponding to the gate trench and the first short channel trench, so that the metal layer covering the gate trench electrically leads out only the second conductive plug.

13. A shielding grid trench structure, characterized in that, It is applied in DC-DC conversion control circuits where MOSFETs are used as switching devices, and is fabricated using the method for fabricating a shielded gate trench structure as described in any one of claims 1 to 12, wherein multiple SBR devices are also integrated in the epitaxial layer corresponding to the active region forming the shielded gate trench structure.

14. The shielding trench structure as described in claim 13, characterized in that, The ratio of the number of the first short-channel trench and the second short-channel trench used to form the SBR device in the epitaxial layer corresponding to the active region to the total number of trenches formed in the epitaxial layer corresponding to the active region is 10% to 15%.

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