Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The forming method includes: providing a substrate including an adjacent first device region and a second device region, a stacked structure being formed on the substrates of the first device region and the second device region, the stacked structure including one or more stacked channel stacks, the channel stack including a channel layer and a sacrificial layer located on the channel layer; forming an isolation wall protruding from the substrate at the junction of the first device region and the second device region, the isolation wall including an isolation vertical portion protruding from the substrate and an isolation horizontal portion located at the top of the isolation vertical portion, the isolation vertical portion covering opposite sidewalls of the stacked structures of the first device region and the second device region, the isolation horizontal portion extending onto the stacked structures on both sides of the isolation vertical portion; after forming the isolation wall, removing the sacrificial layer; forming a gate structure spanning the channel layer and the isolation wall; forming a first partition opening penetrating the gate structure at the top of the isolation wall; and forming a first gate partition structure in the first partition opening. The present invention increases the process window for forming the first gate partition structure at the top of the isolation wall.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration, and semiconductor process nodes are continuously reduced following Moore's law. To better meet the requirements of proportional reduction of device size, semiconductor processes have gradually started to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors and forksheet transistors.

[0003] Moreover, in the current process of forming a gate, the gate cut technology is usually used to cut a strip-shaped gate. The cut gate corresponds to different transistors, which can improve the integration of transistors. In addition, when multiple gates are arranged in a column along the extension direction, through the gate cut technology, the pitch in the docking direction (Gate Cut CD) between the cut gates can be accurately reduced. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a substrate including adjacent first and second device regions; a channel layer structure respectively located on the substrate of the first and second device regions, and along the normal direction of the substrate surface, the channel layer structure includes one or more spaced channel layers; an isolation wall protruding on the substrate at the junction of the first and second device regions, the isolation wall includes an isolation vertical portion protruding on the substrate and an isolation horizontal portion located at the top of the isolation vertical portion, the isolation vertical portion covers the opposite sidewalls of the channel layer structures in the first and second device regions, the isolation horizontal portion extends above the channel layer structures on both sides of the isolation vertical portion, and there is a gap between the bottom of the isolation horizontal portion and the topmost channel layer; a gate structure located on the substrate and spanning the channel layer structure and the isolation wall, the gate structure covers the exposed top, bottom, and sidewalls of the channel layer; a gate partition structure including a first gate partition structure located on the top of the isolation wall and penetrating the gate structure, and the gate partition structure divides the gate structure along the extension direction of the gate structure.

[0006] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate including an adjacent first device region and second device region, a stacked structure being formed on the substrates of the first device region and the second device region respectively, the stacked structure including one or more stacked channel stacks, and each channel stack including a channel layer and a sacrificial layer located on the channel layer; forming a spacer on the substrate at the junction of the protruding first device region and the second device region, the spacer including a spacer vertical portion protruding from the substrate and a spacer horizontal portion located at the top of the spacer vertical portion, the spacer vertical portion covering opposite sidewalls of the stacked structures of the first device region and the second device region, and the spacer horizontal portion extending onto the stacked structures on both sides of the spacer vertical portion; after forming the spacer, removing the sacrificial layer to expose the top and bottom of the channel layer; forming a gate structure spanning the channel layer and the spacer, the gate structure covering the exposed top, bottom, and sidewalls of the channel layer; forming a first partition opening penetrating the gate structure at the top of the spacer, the first partition opening partitioning the gate structure along the extension direction of the gate structure; and forming a first gate partition structure in the first partition opening.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] The semiconductor structure provided by the embodiment of the present invention includes a spacer protruding on the substrate at the junction of the first device region and the second device region. The spacer includes a spacer vertical portion protruding from the substrate and a spacer horizontal portion located at the top of the spacer vertical portion. The spacer vertical portion covers opposite sidewalls of the channel layer structures of the first device region and the second device region, and the spacer horizontal portion extends above the channel layer structures on both sides of the spacer vertical portion. As the feature size of the integrated circuit continues to decrease and adjacent devices get closer and closer, in the embodiment of the present invention, the spacer isolates the first device region and the second device region. Thus, while ensuring a good isolation effect on adjacent devices, the adjacent first device region and the second device region can be as close as possible, which is beneficial to reducing the distance between the adjacent channel layer structures of the first device region and the second device region, thereby forming a more compact and smaller-sized device. At the same time, the first gate partition structure is located at the top of the spacer and penetrates the gate structure. The spacer horizontal portion extends above the channel layer structures on both sides of the spacer vertical portion, which is beneficial to increasing the contact area of the top of the spacer for contacting the first gate partition structure, thereby increasing the process window for forming the first gate partition structure at the top of the spacer, and being beneficial to reducing the probability of damaging the film layer on the side of the spacer (for example, the work function layer covering the channel layer or the channel layer) when forming the first gate partition structure, thereby improving the performance of the semiconductor structure.

[0009] In the forming method provided by the embodiments of the present invention, an isolation wall is formed on the substrate at the junction of the convex first device region and the second device region. The isolation wall includes an isolation vertical portion protruding from the substrate and an isolation horizontal portion located at the top of the isolation vertical portion. The isolation vertical portion covers the opposite sidewalls of the stacked structures of the first device region and the second device region, and the isolation horizontal portion extends onto the stacked structures on both sides of the isolation vertical portion. As the feature size of the integrated circuit continues to decrease and adjacent devices get closer and closer, in the embodiments of the present invention, the isolation wall isolates the first device region and the second device region, so that while better ensuring the isolation effect on adjacent devices, the adjacent first device region and the second device region are as close as possible, which is beneficial to reducing the distance between the adjacent stacked structures of the first device region and the second device region, thereby forming a more compact and smaller device. At the same time, a first partition opening penetrating the gate structure is formed at the top of the isolation wall, and a first gate partition structure is formed in the first partition opening. Then, the isolation horizontal portion extends onto the stacked structures on both sides of the isolation vertical portion, which is beneficial to increasing the area of the top of the isolation wall for contacting the first gate partition structure, thereby increasing the process window for forming the first partition opening at the top of the isolation wall, and being beneficial to reducing the probability of damaging the film layer on the side of the isolation wall (for example, the work function layer or the channel layer covering the channel layer) when forming the first gate partition opening, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 are schematic structural diagrams corresponding to each step in a forming method of a semiconductor structure;

[0011] Figure 4 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention;

[0012] Figures 5 to 16 are schematic structural diagrams corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] Currently, the performance of semiconductor structures needs to be improved. The reason for the need to improve the performance is analyzed in combination with a forming method of a semiconductor structure.

[0014] Refer to Figure 1 , a substrate 10 is provided, including an adjacent first device region 10A and a second device region 10B. Channel layer structures 20 are respectively formed on the substrate 10 of the first device region 10A and the second device region 10B. The channel layer structure 20 includes one or more spaced channel layers 21. At the junction of the first device region 10A and the second device region 10B, an isolation wall 30 covering the opposite sidewalls of the channel layer structure 20 is formed on the substrate 10 between adjacent channel layer structures 20; a gate structure 40 spanning the channel layer structure 20 and the isolation wall 30 is formed, and the gate structure 40 covers the exposed top, bottom, and sidewalls of the channel layer 21.

[0015] Reference Figure 2 , a partition opening 43 penetrating through the gate structure 40 is formed at the top of the isolation wall 30, and the partition opening 43 divides the gate structure 40 along the extending direction of the gate structure 30.

[0016] Reference Figure 3 , a gate partition structure 44 is formed in the partition opening 43.

[0017] Currently, in order to make the spacing between adjacent channel structures 20 smaller at the junction of the first device region 10A and the second device region 10B, an isolation wall 30 covering the sidewalls of the channel structures 20 is formed at the junction of the first device region 10A and the second device region 10B. The isolation wall 30 ensures the isolation effect on adjacent devices when the adjacent first device region 10A and second device region 10B are as close as possible.

[0018] As the feature size of the integrated circuit continues to decrease, adjacent devices are getting closer and closer. In order to occupy less space, the size of the isolation wall 30 along the extending direction of the channel layer 21 is small, that is to say, the top surface area of the isolation wall 30 is small. And since the partition structure 44 is formed on the top of the isolation wall 30, the process window for forming the partition opening 43 is small, resulting in difficulty in accurately positioning the formation of the partition opening 43. Moreover, when forming the partition opening 43, it is easy to etch into the side of the isolation wall 30 due to etching deviation, thereby damaging other film layers on the side of the isolation wall 30, such as the work function layer covering the channel layer 21 or the channel layer 21, thus affecting the performance of the semiconductor structure.

[0019] To solve the technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including adjacent first and second device regions, and stacked structures are respectively formed on the substrates of the first and second device regions, the stacked structure including one or more stacked channel stacks, the channel stack including a channel layer and a sacrificial layer located on the channel layer; forming an isolation wall on the substrate at the junction of the protruding first and second device regions, the isolation wall including an isolation vertical portion protruding from the substrate and an isolation horizontal portion located at the top of the isolation vertical portion, the isolation vertical portion covering the opposite sidewalls of the stacked structures in the first and second device regions, and the isolation horizontal portion extending onto the stacked structures on both sides of the isolation vertical portion; after forming the isolation wall, removing the sacrificial layer to expose the top and bottom of the channel layer; forming a gate structure spanning the channel layer and the isolation wall, the gate structure covering the exposed top, bottom and sidewalls of the channel layer; forming a first partition opening penetrating through the gate structure at the top of the isolation wall, the first partition opening dividing the gate structure along the extending direction of the gate structure; forming a first gate partition structure in the first partition opening.

[0020] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In the embodiments of the present invention, the isolation wall isolates the first device region and the second device region, so that the adjacent first device region and the second device region are as close as possible while ensuring a good isolation effect on adjacent devices, which is beneficial to reducing the distance between the adjacent stacked structures of the first device region and the second device region, thereby forming a more compact and smaller-sized device. At the same time, a first partition opening penetrating the gate structure is formed at the top of the isolation wall, and a first gate partition structure is formed in the first partition opening. Then, the isolation horizontal part extends onto the stacked structures on both sides of the isolation vertical part, which is beneficial to increasing the area of the top of the isolation wall for contacting the first gate partition structure, thereby increasing the process window for forming the first partition opening at the top of the isolation wall, and is beneficial to reducing the probability of damaging the film layer on the side of the isolation wall (for example, the work function layer or the channel layer covering the channel layer) when forming the first gate partition opening, thereby improving the performance of the semiconductor structure.

[0021] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0022] Figure 4 It is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0023] The semiconductor structure includes: a substrate 101, including adjacent first device region 101A and second device region 101B; a channel layer structure 201, respectively located on the substrate 101 of the first device region 101A and the second device region 101B, along the normal direction of the surface of the substrate 101 (such as Figure 4 shown by the Y direction in the figure), the channel layer structure 201 includes one or more spaced channel layers 221; an isolation wall 511, protruding on the substrate 101 at the junction of the first device region 101A and the second device region 101B, the isolation wall 511 includes an isolation vertical part 521 protruding on the substrate 101 and an isolation horizontal part 531 located at the top of the isolation vertical part 521. The isolation vertical part 521 covers the opposite sidewalls of the channel layer structure 201 of the first device region 101A and the second device region 101B, and the isolation horizontal part 531 extends above the channel layer structure 201 on both sides of the isolation vertical part 521. There is a gap between the bottom of the isolation horizontal part 531 and the topmost channel layer 221; a gate structure 401, located on the substrate 101 and spanning the channel layer structure 201 and the isolation wall 511, the gate structure 401 covers the exposed top, bottom, and sidewalls of the channel layer 221; a gate partition structure (not labeled), including a first gate partition structure 461 located at the top of the isolation wall 511 and penetrating the gate structure 401, and the gate partition structure divides the gate structure 401 along the extension direction of the gate structure 401.

[0024] The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. Among them, the semiconductor structure includes a Forksheet transistor.

[0025] The substrate 101 includes a substrate 111.

[0026] In this embodiment, the material of the substrate 111 is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for the process requirements or easy to integrate.

[0027] It should be noted that the substrate 101 further includes: a bottom fin 131, located on the substrate 111. In this embodiment, the bottom fin 131 and the substrate 111 are an integral structure.

[0028] In this embodiment, the substrate 101 further includes: an isolation layer 121, located on the substrate 121. The isolation layer 121 is used to achieve insulation between different devices. For example, in the CMOS manufacturing process, an isolation layer 121 is usually formed between an NMOS transistor and a PMOS transistor.

[0029] In this embodiment, the isolation layer 121 covers the sidewalls of the bottom fin 131.

[0030] In this embodiment, taking the semiconductor structure as a Forksheet transistor as an example, the substrate 101 includes an adjacent first device region 101A and a second device region 101B. The first device region 101A is used to form a first device, and the second device region 101B is used to form a second device.

[0031] In this embodiment, the first device region 101A includes an NMOS region, and the second device region 101B includes a PMOS region. The NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor.

[0032] As the device feature size continues to shrink, by adopting a Forksheet transistor, a smaller pitch between adjacent NMOS transistors and PMOS crystals can be allowed, thereby obtaining better area scalability.

[0033] In this embodiment, the NMOS transistor formed in the first device region 101A and the PMOS transistor formed in the first device region 101B constitute a Forksheet transistor.

[0034] Correspondingly, the first device region 101B and the second device region 101B constitute a third device region 101C, and the third device region 101C is used to form a Forksheet transistor.

[0035] The channel layer structure 201 includes one or more spaced channel layers 221, which are used as the channels of the semiconductor structure.

[0036] In this embodiment, the material of the channel layer 221 includes silicon, germanium, silicon germanide, or group III-V semiconductor materials. As an example, the material of the channel layer 221 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0037] It should be noted that, in this embodiment, the materials of the channel layer 221 and the substrate 111 are the same. In other embodiments, the materials of the channel layer and the substrate may also be different.

[0038] The isolation wall 511 is used to isolate the devices near the first device region 101A and the second device region 101B.

[0039] As the feature size of the integrated circuit continues to decrease, adjacent devices are getting closer and closer. In this embodiment, the isolation wall 511 isolates the first device region 101A and the second device region 101B. Thus, while ensuring a good isolation effect on adjacent devices, the adjacent first device region 101A and the second device region 101B are made as close as possible, which is beneficial to reducing the distance between the adjacent channel layer structures 201 of the first device region 101A and the second device region 101B, thereby forming a more compact and smaller-sized device. At the same time, the first gate isolation structure 461 is located on top of the isolation wall 511 and penetrates the gate structure 401, and the isolation horizontal part 531 extends above the channel layer structures 201 on both sides of the isolation vertical part 521, which is beneficial to increasing the area of the top of the isolation wall 511 for contacting the first gate isolation structure 461, thereby increasing the process window for forming the first gate isolation structure 461 on the top of the isolation wall 511, and is beneficial to reducing the probability of damaging the film layer (for example, the work function layer covering the channel layer 221 or the channel layer 221) on the side of the isolation wall 511 when forming the first gate isolation structure 461, thereby improving the performance of the semiconductor structure.

[0040] In this embodiment, the top of the isolation vertical part 521 is higher than the top of the channel layer structure 201, so as to improve the isolation effect on adjacent devices and also be used as a support part for the isolation horizontal part 531.

[0041] In this embodiment, there is a gap between the bottom of the isolation horizontal part 531 and the topmost channel layer 221, so that the influence of the isolation horizontal part 531 on forming the gate structure 401 on the surface of the topmost channel layer 221 is relatively small. While increasing the process window for forming the first gate isolation structure 461 on the top of the isolation wall 511, the formation quality of the gate structure 401 is ensured.

[0042] In this embodiment, in the step of forming the isolation vertical portion 521, the isolation horizontal portion 531 is formed together. Therefore, the isolation vertical portion 521 and the isolation horizontal portion 531 are of an integral structure, thereby improving the process efficiency and also being beneficial to improving the process compatibility of forming the isolation horizontal portion 531.

[0043] In other embodiments, the isolation vertical portion and the isolation horizontal portion can also be formed separately, that is to say, the isolation vertical portion and the isolation horizontal portion can also be of a separated structure.

[0044] In this embodiment, protrusions are respectively formed at both ends of the isolation horizontal portion 531.

[0045] In the step of forming the first gate isolation structure 461, first, a isolation opening is formed on the top of the isolation wall 511. Then, in the step of forming the isolation opening, the protrusions at both ends of the isolation horizontal portion 531 are beneficial to ensuring that the etching direction of the isolation opening along the normal direction does not deviate, thereby being beneficial to ensuring that the bottom of the first gate isolation structure 461 is located on the top of the isolation wall 511.

[0046] It should be noted that in this embodiment, the size of the isolation horizontal portion 531 protruding from the isolation vertical portion 521 should not be too large or too small. If the size of the isolation horizontal portion 531 protruding from the isolation vertical portion 521 is too large, the isolation horizontal portion 531 is too thick and heavy, which is likely to affect the connection quality between the isolation horizontal portion 531 and the isolation vertical portion 521. If the size of the isolation horizontal portion 531 protruding from the isolation vertical portion 521 is too small, the area of the top of the isolation wall 511 for contacting the first gate isolation structure 461 increases too little, so that the process window for forming the first gate isolation structure 461 on the top of the isolation wall 511 is still small, which is likely to cause damage to the film layer on the side of the isolation wall 511 (for example, the work function layer covering the channel layer 221 or the channel layer 221) when forming the first gate isolation structure 461, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the size of the isolation horizontal portion 531 protruding from the isolation vertical portion 521 is 10 nm to 26 nm.

[0047] In this embodiment, the material of the isolation wall 511 includes SiBCN or SiN.

[0048] SiBCN or SiN has good insulation, which can enable better isolation between the devices in the first device region 101A and the second device region 101B.

[0049] The gate structure 401 is used to control the opening or closing of the channel of the transistor.

[0050] In this embodiment, the gate structure 401 includes a gate dielectric layer 411 and a gate electrode layer 421 located on the gate dielectric layer 411.

[0051] The gate dielectric layer 411 is used to isolate the gate structure 401 from the channel layer 221. The material of the gate dielectric layer 411 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the material of the gate dielectric layer 411 includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the materials of the high-k gate dielectric layer include HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0052] The gate electrode layer 421 includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor. For PMOS transistors, the work function layer is a P-type work function layer, and the materials of the P-type work function layer include one or several of TiN, TaN, TaSiN, TaAlN, and TiAlN; for NMOS transistors, the work function layer is an N-type work function layer, and the materials of the N-type work function layer include one or two of TiAl and TiAlC. The electrode layer is used to lead out the electrical property of the gate electrode layer. In this embodiment, the materials of the electrode layer include one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

[0053] In other embodiments, according to process requirements, the gate structure can also be a polysilicon gate structure.

[0054] The gate isolation structure is used to insulate the gate structures 401 from each other. Among them, the first gate isolation structure 461 is used to insulate the gate structures 401 of the adjacent first device region 101A and the second device region 101B from each other.

[0055] In this embodiment, the gate isolation structure further includes: a second gate isolation structure 471, which is located on the substrate 101 at the junction of the adjacent third device regions 101C and penetrates the gate structure 401.

[0056] The second gate isolation structure 471 is used to insulate the gate structures 401 of the adjacent third device regions 101C from each other.

[0057] The material of the gate isolation structure has a high hardness and density, thereby reducing the probability of damage to the gate isolation structure during the formation of the semiconductor structure, and further ensuring the isolation performance of the gate isolation structure.

[0058] For this reason, in this embodiment, the material of the gate isolation structure is silicon nitride, and it also has good isolation performance. In other embodiments, the gate isolation structure can also be other nitrogen-containing dielectric materials.

[0059] Figures 5 to 16 These are schematic diagrams of structures corresponding to the steps in an embodiment of the method for forming a semiconductor structure of the present invention.

[0060] Referring to Figure 5 , a substrate 100 is provided, which includes an adjacent first device region 100A and a second device region 100B. On the substrate 100 of the first device region 100A and the second device region 100B, a stacked structure 200 is respectively formed. The stacked structure 200 includes one or more stacked channel stacks 210, and the channel stack 210 includes a channel layer 220 and a sacrificial layer 230 located on the channel layer 220.

[0061] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Among them, the semiconductor structure includes a finFET.

[0062] The substrate 100 includes a substrate 110.

[0063] In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, etc. The substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for the process requirements or easy to integrate.

[0064] In this embodiment, the substrate 100 further includes a bottom fin 130 located between the stacked structure 200 and the substrate 110.

[0065] In this embodiment, the bottom fin 130 and the substrate 110 are an integral structure. In other embodiments, the bottom fin can also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the bottom fin.

[0066] Correspondingly, in this embodiment, the material of the bottom fin 130 is silicon.

[0067] In this embodiment, taking the semiconductor structure as a finFET as an example, the substrate 100 includes an adjacent first device region 100A and a second device region 100B. The first device region 100A is used to form a first device, and the second device region 100B is used to form a second device.

[0068] In this embodiment, the first device region 100A includes an NMOS region, and the second device region 100B includes a PMOS region. The NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor, thereby forming a finFET.

[0069] As the device feature size continues to shrink, by adopting a fork-shaped gate transistor, a smaller pitch between adjacent NMOS transistors and PMOS transistors can be allowed, thereby obtaining better area scalability.

[0070] In this embodiment, the NMOS transistor formed in the first device region 100A and the PMOS transistor formed in the first device region 100B constitute a fork-shaped gate transistor.

[0071] Correspondingly, the first device region 100B and the second device region 100B constitute a third device region 100C, and the third device region 100C is used to form a fork-shaped gate transistor.

[0072] The channel layer 220 in the stacked structure 200 is used as the channel of the transistor. The sacrificial layer 230 is used to provide a process basis for the subsequent suspension setting of the channel layer 220, and is also used to occupy the spatial position for the subsequent formed gate structure. In the subsequent manufacturing process, the sacrificial layer 230 is removed, so that the channel layer 220 is suspended, and a gate structure is formed between adjacent channel layers 220, so that the gate structure surrounds and covers the channel layer 220.

[0073] The top and side walls of the channel layer 220 covered by the gate structure are used as the channel. In this embodiment, the top, bottom, and side walls of the channel layer 220 can all be used as the channel, increasing the area of the channel layer 220 used as the channel, thereby increasing the working current of the semiconductor structure.

[0074] In this embodiment, the material of the channel layer 220 includes silicon, germanium, silicon germanide, or III-V semiconductor materials. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0075] In this embodiment, the material of the sacrificial layer 230 includes silicon, germanium, or silicon germanide, and there is an etching selectivity between the material of the channel layer 220 and the sacrificial layer 230, which is beneficial to the subsequent removal of the sacrificial layer 230 and reduces the damage to the channel layer 220.

[0076] In this embodiment, the material of the channel layer 220 is silicon. Therefore, the material of the sacrificial layer 230 is silicon germanide.

[0077] Silicon germanide and silicon can form a large etching selectivity, which is beneficial to the subsequent removal of the sacrificial layer 230 and reduces the damage to the channel layer 220.

[0078] In other embodiments, according to the material of the channel layer, a suitable material with an etching selectivity to the channel layer can be selected, so as to reduce the damage to the channel layer when the sacrificial layer is removed subsequently.

[0079] In this embodiment, a mask layer 300 is further formed on the stacked structure 200, and the mask layer 300 around the first device region 100A and the second device region 100B defines a first opening 400.

[0080] The mask layer 300 serves as an etching mask for forming the stacked structure 200, and the first opening 400 is used as a basis for subsequent process operations of removing a part of the width of the first mask layer.

[0081] In this embodiment, the material of the mask layer 300 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 300 can be a single-layer structure or a stacked structure. As an example, the material of the mask layer 300 is silicon oxide and silicon nitride, that is, the mask layer 300 is a multi-layer structure, including a silicon nitride layer 310 and a silicon oxide layer 320 covering the silicon nitride layer 310.

[0082] With reference to Figures 6 to 8 , an isolation wall 510 is formed on the substrate 100 at the junction of the protruding first device region 100A and the second device region 100B. The isolation wall 510 includes an isolation vertical portion 520 protruding from the substrate 100 and an isolation horizontal portion 530 located at the top of the isolation vertical portion 520. The isolation vertical portion 520 covers the opposite sidewalls of the stacked structure 200 of the first device region 100A and the second device region 100B, and the isolation horizontal portion 530 extends onto the stacked structure 200 on both sides of the isolation vertical portion 520.

[0083] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In this embodiment, the isolation wall 510 isolates the first device region 100A and the second device region 100B, so that the adjacent first device region 100A and the second device region 100B are as close as possible while ensuring a good isolation effect for adjacent devices, which is beneficial to reducing the distance between the adjacent stacked structures 200 of the first device region 100A and the second device region 100B, thereby forming a more compact and smaller-sized device. At the same time, a first partition opening penetrating the gate structure is formed on the top of the isolation wall 510, and a first gate partition structure is formed in the first partition opening. Then, the isolation horizontal portion 530 extends onto the stacked structure 200 on both sides of the isolation vertical portion 520, which is beneficial to increasing the area of the top of the isolation wall 510 for contacting the first gate partition structure, thereby increasing the process window for forming the first partition opening on the top of the isolation wall 510, and is beneficial to reducing the probability of damaging the film layer on the side of the isolation wall 510 (for example, the work function layer covering the channel layer 220 or the channel layer 220) when forming the first gate partition opening, thereby improving the performance of the semiconductor structure.

[0084] In this embodiment, the isolation horizontal portion 530 extends onto the stacked structure 200 on both sides of the isolation vertical portion 520. Then, after removing the sacrificial layer 230 subsequently, the top of the isolation vertical portion 520 is higher than the top of the topmost channel layer 220, thereby improving the isolation effect on adjacent devices and also serving as a support portion for the isolation horizontal portion 530.

[0085] Moreover, after removing the sacrificial layer 230 subsequently, there is a gap between the bottom of the isolation horizontal portion 530 and the topmost channel layer 220. Thus, the influence of the isolation horizontal portion 530 on forming the gate structure on the surface of the topmost channel layer 220 is relatively small. While increasing the process window for forming the first gate isolation structure on the top of the isolation wall 510, the formation quality of the gate structure is ensured.

[0086] In this embodiment, in the step of forming the isolation vertical portion 520, the isolation horizontal portion 530 is formed together. Therefore, the isolation vertical portion 520 and the isolation horizontal portion 530 are of an integral structure, thereby improving the process efficiency and also being beneficial to improving the process compatibility of forming the isolation horizontal portion 530.

[0087] In other embodiments, the isolation vertical portion and the isolation horizontal portion can also be formed separately, that is to say, the isolation vertical portion and the isolation horizontal portion can also be of a separated structure.

[0088] In this embodiment, the material of the isolation wall 510 includes SiBCN or SiN.

[0089] SiBCN or SiN has good insulation, and can enable better isolation between the devices in the first device region 100A and the second device region 100B.

[0090] Specifically, referring to Figure 6 , the steps of forming the isolation wall 510 include: removing a portion of the mask layer 300 with a certain width at the sidewall of the first opening 400 to form a second opening 410, and the second opening 410 exposes a part of the top of the stacked structure 200.

[0091] Removing a portion of the mask layer 300 with a certain width at the sidewall of the first opening 400 to form a second opening 410 provides a spatial position for forming the isolation horizontal portion 530.

[0092] In this embodiment, an anisotropic etching process is used to remove a portion of the mask layer 300 with a certain width at the sidewall of the first opening 400.

[0093] The anisotropic etching process includes an anisotropic dry etching process. By selecting the anisotropic dry etching process, it is beneficial to reduce the damage to the bottom stacked structure 200 of the mask layer 300. At the same time, the anisotropic dry etching process has more etching directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the second opening 410. Moreover, the anisotropic dry etching process can better control process parameters, has high process controllability, and is easy to obtain a more precisely controlled width of the mask layer 300 removed by etching.

[0094] It should be noted that the width w of the mask layer 300 with a partial width removed at the sidewall of the first opening 400 should not be too large or too small. If the width w of the mask layer 300 with a partial width removed at the sidewall of the first opening 400 is too large, the opening size of the second opening 410 is too large, and it is difficult for the subsequent formed first isolation material layer to fill a part of the depth of the second opening 410. Thus, in the step of etching the first isolation material layer, it is easy to remove the first isolation material layer covering the top of the stacked structure 200, resulting in difficulty in forming the isolation cross part 530. If the width w of the mask layer 300 with a partial width removed at the sidewall of the first opening 400 is too small, the size of the isolation cross part 530 protruding from the isolation vertical part 520 is too small, and the area of the top of the subsequent isolation wall 510 for contacting the first gate isolation structure increases too little. Thus, the process window for forming the first gate isolation structure on the top of the isolation wall 510 is still small, and it is easy to cause damage to the film layer on the side of the isolation wall 510 (for example, the work function layer covering the channel layer 220 or the channel layer 220) when forming the first gate isolation structure, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the width w of the mask layer 300 with a partial width removed at the sidewall of the first opening 400 is 10 nm to 26 nm.

[0095] Reference Figure 7 , a first isolation material layer 500 covering the sidewall of the second opening 410, a part of the top of the stacked structure 200 exposed by the second opening 410, and the top of the mask layer 300 is formed. The first isolation material layer 500 fills the gap between adjacent stacked structures 200 and a part of the depth of the second opening 410 at the junction of the first device region 100A and the second device region 100B.

[0096] The first isolation material layer 500 is used to directly form the isolation wall 510.

[0097] In this embodiment, the first isolation material layer 500 fills a part of the depth of the second opening 410. Thus, in the subsequent step of etching the first isolation material layer 500, a part of the isolation material layer 500 covering the top of the stacked structure 200 can be retained as the isolation cross part 530.

[0098] In this embodiment, the process of forming the first isolation material layer 500 covering the sidewall of the second opening 410, a part of the top of the stacked structure 200 exposed by the second opening 410, and the top of the mask layer 300 includes an atomic layer deposition process or a chemical vapor deposition process.

[0099] The atomic layer deposition process or the chemical vapor deposition process has good deposition effects and good step coverage ability, so that the first isolation material layer 500 can better cover the sidewall of the second opening 410, a part of the top of the stacked structure 200 exposed by the second opening 410, and the top of the mask layer 300.

[0100] It should be noted that in this embodiment, by forming the second opening 410 with an appropriate opening size, the first isolation material layer 500 can fill the gap between adjacent stacked structures 200 at the junction of the first device region 100A and the second device region 100B while filling a part of the depth of the second opening 410.

[0101] Correspondingly, in this embodiment, the material of the first isolation material layer 500 includes SiBCN or SiN.

[0102] It should be noted that in the step of forming the first isolation material layer 500, the first isolation material layer 500 also covers the substrate 110 on both sides of the third device region 100C and the sidewall of the stacked structure 200.

[0103] Reference Figure 8 , remove the first isolation material layer 500 located on the top of the mask layer 300 and a part of the thickness in the second opening 410, and retain the first isolation material layer 500 filled in the gap between adjacent stacked structures 200 and extending to cover a part of the top of the stacked structure 200 exposed by the second opening 410 as the isolation wall 510.

[0104] In this embodiment, the first isolation material layer 500 fills a part of the depth of the second opening 410, so that after etching the first isolation material layer 500, a part of the thickness of the first isolation material layer 500 can still be retained to extend and cover a part of the top of the stacked structure 200 exposed by the second opening 410.

[0105] In this embodiment, an anisotropic etching process is used to remove the isolation material layer 530 located on the top of the mask layer 300 and a part of the thickness in the second opening 410.

[0106] The anisotropic etching process includes an anisotropic dry etching process. The anisotropic dry etching process is more directional, so that the first isolation material layer 500 can be etched downward integrally from each top surface. Thus, while removing the first isolation material layer 500 located on top of the mask layer 300 and part of the thickness in the second opening 410, the first isolation material layer 500 filling the gaps between adjacent stacked structures 200 and extending to cover part of the top of the stacked structure 200 exposed by the second opening 410 is retained as the isolation wall 510. Moreover, the anisotropic dry etching process can better control the process parameters, has high process controllability, and is easy to obtain a more precisely controlled thickness of the first isolation material layer 500 that extends to cover part of the top of the stacked structure 200 exposed by the second opening 410.

[0107] Correspondingly, in this embodiment, during the process of etching the first isolation material layer 500, part of the thickness of the mask layer 300 is also etched.

[0108] In this embodiment, the first isolation material layer 500 also covers the sidewalls of the second opening 410. The height of the first isolation material layer 500 located on the sidewalls of the second opening 410 is greater than that of the first isolation material layer 500 filling part of the depth of the second opening 410. Therefore, after etching the first isolation material layer 500, the isolation wall 510 also extends to cover part of the sidewalls of the mask layer 300.

[0109] In the subsequent steps of forming the first gate partition structure, a partition opening is first formed on top of the isolation wall 510. Then, in the step of forming the partition opening, the isolation wall 510 also extends to cover part of the sidewalls of the mask layer 300 to form a raised part, which is beneficial to ensuring that the etching direction of the partition opening along the normal direction does not deviate, and thus is beneficial to ensuring that the bottom of the first gate partition structure is located on top of the isolation wall 510.

[0110] In this embodiment, after forming the isolation wall 510, the subsequent steps further include: removing the mask layer 300 to prepare for subsequent processes.

[0111] It should be noted that the first isolation material layer 500 covering the sidewalls of the substrate 110 and the stacked structure 200 on both sides of the third device region 100C is relatively thin. Therefore, in the step of removing the first isolation material layer 500 located on top of the mask layer 300 and part of the thickness in the second opening 410, the first isolation material layer 500 covering the sidewalls of the substrate 110 and the stacked structure 200 on both sides of the third device region 100C is removed together.

[0112] Reference Figure 9 , after forming the isolation wall 510 and before removing the mask layer 300 in the subsequent steps, the steps further include: forming a second isolation material layer 330 covering the stacked structure 200, the bottom fin 130, the isolation wall 510, and the mask layer 300.

[0113] The second isolation material layer 330 is used to form an isolation layer subsequently.

[0114] In this embodiment, the second isolation material layer 330 is formed by a chemical vapor deposition process.

[0115] In this embodiment, the material of the second isolation material layer 330 includes silicon oxide, so that the isolation performance of the formed isolation layer is better.

[0116] With reference to Figure 10 and Figure 11 , the second isolation material layer 330 is thinned, and the remaining second isolation material layer 330 covering the sidewall of the bottom fin 130 is retained as the isolation layer 120.

[0117] The isolation layer 120 is used to achieve insulation between different devices. For example, in the CMOS manufacturing process, an isolation layer 120 is usually formed between an NMOS transistor and a PMOS transistor.

[0118] Correspondingly, the material of the isolation layer 120 is silicon oxide.

[0119] Specifically, with reference to Figure 10 , the steps of thinning the second isolation material layer 330 include: planarizing the second isolation material layer 330 to expose the top of the isolation wall 510.

[0120] The top surface flatness of the deposited film layer is usually not good. Therefore, in order to form an isolation layer 120 with better top surface flatness, the second isolation material layer 330 is first planarized, so that the top surface flatness of the second isolation material layer 330 is better, which is beneficial to forming an isolation layer 120 with better top surface flatness.

[0121] In this embodiment, the second isolation material layer 330 is planarized by a chemical mechanical polishing process.

[0122] In this embodiment, by planarizing the second isolation material layer 330 to expose the top of the isolation wall 510, the second isolation material layer 330 higher than the top of the isolation wall 510 can be removed through planarization, making it easier to remove the second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200 subsequently.

[0123] In the step of planarizing the second isolation material layer 330 in this embodiment, a part of the thickness of the mask layer 300 is also removed.

[0124] As an example, in the step of planarizing the second isolation material layer 330, the silicon oxide layer 320 is removed.

[0125] With reference to Figure 11, the second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200 is removed, and the second isolation material layer 330 covering the sidewalls of the bottom fins 130 is retained as the isolation layer 120.

[0126] The second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200 is removed to prepare for the subsequent removal of the sacrificial layer 230.

[0127] In this embodiment, a wet etching process is used to remove the second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200.

[0128] The cost of the wet etching process is relatively low, the operation steps are simple, and a large etching selectivity can be achieved, which is beneficial to reducing the damage to the isolation wall 510 and the stacked structure 200 during the process of removing the second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200.

[0129] In this embodiment, in the step of removing the second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200, the remaining part of the mask layer 300 is also removed.

[0130] As an example, in the step of removing the second isolation material layer 330 covering the isolation wall 510 and the stacked structure 200, the silicon nitride layer 310 is also removed.

[0131] Therefore, in this embodiment, in the step of thinning the second isolation material layer 330, the mask layer 300 is removed, which saves the process flow and improves the process efficiency.

[0132] Reference Figure 12 , after the isolation wall 510 is formed, the sacrificial layer 230 is removed to expose the top and bottom of the channel layer 220.

[0133] Removing the sacrificial layer 230 to expose the top and bottom of the channel layer 220 prepares for the subsequent formation of a gate structure surrounding and covering the channel layer 220.

[0134] It should be noted that after the isolation wall 510 is formed and before the sacrificial layer 230 is removed, it further includes: forming a dummy gate structure spanning the channel layer 220 and the isolation wall 510; forming source / drain doping layers in the stacked structure 200 on both sides of the dummy gate structure; forming an interlayer dielectric layer covering the source / drain doping layers and the sidewalls of the dummy gate structure; removing the dummy gate structure to form a gate opening in the interlayer dielectric layer, and the gate opening exposes part of the top and part of the sidewalls of the stacked structure 200; removing the sacrificial layer 230 through the gate opening.

[0135] In this embodiment, a wet etching process is used to remove the sacrificial layer 230. The wet etching process has relatively low cost, simple operation steps, and can also achieve a large etching selectivity ratio, which is beneficial to reducing the damage to the channel layer 220 during the process of removing the sacrificial layer 230.

[0136] Reference Figure 13 , a gate structure 400 is formed across the channel layer 220 and the isolation wall 510, and the gate structure 400 covers the top, bottom, and sidewalls of the exposed channel layer 220.

[0137] The gate structure 400 is used to control the opening or closing of the channel of the transistor.

[0138] In this embodiment, the gate structure 400 includes a gate dielectric layer 410 and a gate electrode layer 420 located on the gate dielectric layer 410.

[0139] The gate dielectric layer 410 is used to isolate the gate structure 400 from the channel layer 220.

[0140] The material of the gate dielectric layer 410 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the material of the gate dielectric layer 410 includes a high-k dielectric material. Among them, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the materials of the high-k gate dielectric layer include HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0141] The gate electrode layer 420 includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer.

[0142] The work function layer is used to adjust the threshold voltage of the transistor. For a PMOS transistor, the work function layer is a P-type work function layer, and the materials of the P-type work function layer include one or several of TiN, TaN, TaSiN, TaAlN, and TiAlN; for an NMOS transistor, the work function layer is an N-type work function layer, and the materials of the N-type work function layer include one or two of TiAl and TiAlC.

[0143] The electrode layer is used to lead out the electrical property of the gate electrode layer. In this embodiment, the materials of the electrode layer include one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

[0144] In some other embodiments, according to the process requirements, the gate structure can also be a polysilicon gate structure.

[0145] Reference Figure 14, a first partition opening 430 penetrating the gate structure 400 is formed at the top of the isolation wall 510, and the first partition opening 430 divides the gate structure 400 along the extending direction of the gate structure 400.

[0146] The first partition opening 430 is used to provide a spatial position for forming the first gate partition structure subsequently.

[0147] In this embodiment, an anisotropic etching process is used to form the first partition opening 430 penetrating the gate structure 400.

[0148] The anisotropic etching process includes an anisotropic dry etching process. The longitudinal etching rate of the anisotropic dry etching process is much greater than the lateral etching rate, and an equal-precision pattern conversion can be obtained, which is beneficial to accurately positioning the bottom of the first partition opening 430 at the top of the isolation wall 340. At the same time, the anisotropic dry etching process has good directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the first partition opening 430.

[0149] In this embodiment, in the step of forming the first partition opening 430, it further includes: removing a part of the thickness of the gate structure 400 at the junction of the adjacent third device regions 100C to form an initial partition opening 440.

[0150] The initial partition opening 440 is used to prepare for forming the second partition opening subsequently.

[0151] In this embodiment, a gate mask 600 is further formed on the top of the gate structure 400 and is used as an etching mask for etching the gate structure 400.

[0152] In this embodiment, the same photomask is used to form the first partition opening 430 and the initial partition opening 440, which simplifies the process flow and improves the process efficiency.

[0153] Reference Figure 15 , the remaining thickness of the gate structure 400 is removed through the initial partition opening 440 to form a second partition opening 450 penetrating the gate structure 400, and the second partition opening 450 divides the gate structure 400 along the extending direction of the gate structure 400.

[0154] The second partition opening 450 is used to provide a spatial position for forming the second gate partition structure subsequently.

[0155] In this embodiment, an anisotropic etching process is used to form the second partition opening 450 penetrating the gate structure 400.

[0156] Reference Figure 16 , a first gate partition structure 460 is formed in the first partition opening 430.

[0157] The first gate isolation structure 460 is used to insulate the gate structures 400 of the adjacent first device region 100A and second device region 100B from each other.

[0158] The material of the first gate isolation structure 460 has a high hardness and density, thereby reducing the probability of damage to the first gate isolation structure 460 during the formation of the semiconductor structure, and further ensuring the isolation performance of the first gate isolation structure 460.

[0159] For this reason, in this embodiment, the material of the first gate isolation structure 460 is silicon nitride, and it also has good isolation performance. In other embodiments, the first gate isolation structure can also be other nitrogen-containing dielectric materials.

[0160] In this embodiment, in the step of forming the first gate isolation structure 460 in the first isolation opening 430, it further includes: forming a second gate isolation structure 470 in the second isolation opening 450.

[0161] The second gate isolation structure 470 is used to insulate the gate structures 400 of the adjacent third device regions 100C from each other.

[0162] Correspondingly, in this embodiment, the material of the second gate isolation structure 470 is silicon nitride, and it also has good isolation performance. In other embodiments, the second gate isolation structure can also be other nitrogen-containing dielectric materials.

[0163] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate including an adjacent first device region and second device region; A channel layer structure respectively located on the substrates of the first device region and the second device region. Along the normal direction of the substrate surface, the channel layer structure includes one or more spaced channel layers; A spacer wall protruding on the substrate at the junction of the first device region and the second device region. The spacer wall includes a spacer vertical portion protruding on the substrate and a spacer horizontal portion located at the top of the spacer vertical portion. The spacer vertical portion covers the opposite sidewalls of the channel layer structures in the first device region and the second device region. The spacer horizontal portion extends above the channel layer structures on both sides of the spacer vertical portion. There is a gap between the bottom of the spacer horizontal portion and the topmost channel layer; A gate structure located on the substrate and spanning the channel layer structure and the spacer wall. The gate structure covers the exposed top, bottom, and sidewalls of the channel layer; A gate partition structure including a first gate partition structure located on the top of the spacer wall and penetrating the gate structure. The gate partition structure divides the gate structure along the extension direction of the gate structure.

2. The semiconductor structure according to claim 1, wherein The spacer vertical portion and the spacer horizontal portion are of an integral structure.

3. The semiconductor structure according to claim 1, wherein Protrusions are respectively formed at both ends of the spacer horizontal portion.

4. The semiconductor structure according to claim 1, wherein, The size of the spacer horizontal portion protruding from the spacer vertical portion is 10 nm to 26 nm.

5. The semiconductor structure according to claim 1, wherein The first device region and the second device region constitute a third device region; The gate partition structure further includes: a second gate partition structure located on the substrate at the junction of adjacent third device regions and penetrating the gate structure.

6. The semiconductor structure according to claim 1, wherein The material of the spacer wall includes SiBCN or SiN.

7. The semiconductor structure according to claim 1, wherein The material of the gate partition structure includes SiN.

8. The semiconductor structure according to claim 1, wherein The material of the channel layer includes silicon, germanium, silicon germanide, or a III-V group semiconductor material.

9. The semiconductor structure according to claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including an adjacent first device region and second device region. A stacked structure is respectively formed on the substrates of the first device region and the second device region. The stacked structure includes one or more stacked channel stacks. The channel stack includes a channel layer and a sacrificial layer located on the channel layer; Forming a spacer wall protruding on the substrate at the junction of the first device region and the second device region. The spacer wall includes a spacer vertical portion protruding on the substrate and a spacer horizontal portion located at the top of the spacer vertical portion. The spacer vertical portion covers the opposite sidewalls of the stacked structures in the first device region and the second device region. The spacer horizontal portion extends onto the stacked structures on both sides of the spacer vertical portion; After forming the spacer wall, removing the sacrificial layer to expose the top and bottom of the channel layer; Form a gate structure across the channel layer and the isolation wall, the gate structure covering the exposed top, bottom, and sidewalls of the channel layer; Form a first partition opening through the gate structure at the top of the isolation wall, the first partition opening dividing the gate structure along the extension direction of the gate structure; Form a first gate partition structure in the first partition opening.

11. The method for forming a semiconductor structure as claimed in claim 10, wherein, In the step of providing the substrate, a mask layer is further formed on the stacked structure, and the mask layers in the first device region and the second device region enclose a first opening; The step of forming the isolation wall includes: removing a part of the width of the mask layer at the sidewall of the first opening to form a second opening, the second opening exposing a part of the top of the stacked structure; Form a first isolation material layer covering the sidewalls of the second opening, the part of the top of the stacked structure exposed by the second opening, and the top of the mask layer, the first isolation material layer filling the gap at the junction of the first device region and the second device region, the gap between adjacent stacked structures, and a part of the depth of the second opening; Remove the first isolation material layer at the top of the mask layer and a part of the thickness in the second opening, and retain the first isolation material layer filling the gap between adjacent stacked structures and extending to cover the part of the top of the stacked structure exposed by the second opening as the isolation wall; After forming the isolation wall, it further includes: removing the mask layer.

12. The method for forming a semiconductor structure according to claim 11, wherein, The isolation wall further extends to cover a part of the sidewall of the mask layer.

13. The method for forming a semiconductor structure according to claim 11, wherein In the step of providing the substrate, the substrate further includes a substrate and a bottom fin located between the stacked structure and the substrate; After forming the isolation wall and before removing the mask layer, it further includes: forming a second isolation material layer covering the stacked structure, the bottom fin, the isolation wall, and the first mask layer; Thin the second isolation material layer, and retain the remaining second isolation material layer covering the sidewall of the bottom fin as the isolation layer; In the step of thinning the second isolation material layer, remove the mask layer.

14. The method for forming a semiconductor structure according to claim 13, wherein, [[ID= ​ 15. The method for forming a semiconductor structure according to claim 10, wherein, ​ ​ ​ ​ 16. The method for forming a semiconductor structure according to claim 11, wherein ​ 17. The method for forming a semiconductor structure according to claim 11, wherein, The process of forming a first isolation material layer covering the sidewalls of the second opening, a part of the top of the stacked structure exposed by the second opening, and the top of the mask layer includes an atomic layer deposition process or a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 11, wherein, An anisotropic etching process is used to remove the isolation material layer located on the top of the mask layer and a part of the thickness in the second opening.

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