Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate comprising a first device region and a second device region adjacent to each other; forming a channel layer structure on the substrate of each of the first and second device regions, the channel layer structures comprising one or more spaced channel layers; forming an initial isolation wall covering opposite sidewalls of the channel layer structures at the junction of the first and second device regions; forming a cap layer on the sidewalls of the initial isolation wall, the cap layer covering a portion of the sidewall of the initial isolation wall that is higher than the top surface of the channel layer structure, a space being provided between the bottom of the cap layer and the topmost channel layer, the cap layer and the initial isolation wall acting together as an isolation wall; forming a gate structure spanning the channel layer structure and the isolation wall; forming a first isolation opening at the top of the isolation wall that penetrates the gate structure; and forming a first gate isolation structure in the first isolation opening. The present invention increases the process window for forming the first isolation opening at the top of the isolation wall.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. To better adapt to the requirements of device scaling, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as gate-all-around (GAA) transistors and forksheet transistors.

[0003] Currently, gate cutting technology is commonly used in the gate formation process to cut the strip gates. The cut gates correspond to different transistors, which can improve the integration density of transistors. In addition, when multiple gates are arranged in a row along the extension direction, gate cutting technology can accurately reduce the distance between the disconnected gates in the docking direction (Gate Cut CD) after the gate cutting. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a first device region and a second device region adjacent to each other; a channel layer structure, respectively located on the substrate of the first device region and the second device region, and along the normal direction of the substrate surface, the channel layer structure comprises one or more spaced channel layers; an initial isolation wall, protruding from the substrate at the junction of the first device region and the second device region, the initial isolation wall covering the opposite side walls of the channel layer structure of the first device region and the second device region; a cap layer, located on the side walls of the initial isolation wall and covering a portion of the side walls of the initial isolation wall that is higher than the top surface of the channel layer structure, a gap is provided between the bottom of the cap layer and the topmost channel layer, the cap layer and the initial isolation wall together serve as an isolation wall; a gate structure, located on the substrate and spanning the channel layer structure and the isolation wall, the gate structure covering the exposed top, bottom and side walls of the channel layer; a gate isolation structure, comprising a first gate isolation structure located on the top of the isolation wall and penetrating the gate structure, the gate isolation structure dividing the gate structure along the extension direction of the gate structure.

[0006] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region and a second device region adjacent to each other, channel layer structures being formed on the substrates of the first device region and the second device region, respectively, the channel layer structures comprising one or more spaced channel layers, and at the junction of the first device region and the second device region, an initial isolation wall covering the opposite side walls of the channel layer structure is formed on the substrate between adjacent channel layer structures; forming a cap layer on the side walls of the initial isolation wall, the cap layer covering a portion of the side walls of the initial isolation wall that is higher than the top surface of the channel layer structure, a gap being provided between the bottom of the cap layer and the topmost channel layer, the cap layer and the initial isolation wall serving together as an isolation wall; forming a gate structure spanning the channel layer structure and the isolation wall, the gate structure covering the exposed top, bottom and side walls of the channel layer; forming a first isolation opening penetrating the gate structure at the top of the isolation wall, the first isolation opening dividing the gate structure along the extension direction of the gate structure; and forming a first gate isolation structure in the first isolation opening.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] The semiconductor structure provided by the embodiment of the present invention includes an initial isolation wall protruding from the substrate at the junction of the first device area and the second device area, the initial isolation wall covers the opposite side walls of the channel layer structure of the first device area and the second device area, the cap layer is located on the side wall of the initial isolation wall and covers the part of the side wall of the initial isolation wall that is higher than the top surface of the channel layer structure, there is a gap between the bottom of the cap layer and the topmost channel layer, the cap layer and the initial isolation wall serve as an isolation wall together; as the feature size of the integrated circuit continues to decrease, adjacent devices are getting closer and closer, in the embodiment of the present invention, the isolation wall isolates the first device area and the second device area, thereby ensuring a better isolation effect on the adjacent devices, so that the adjacent first devices are The region and the second device region are as close as possible, which is beneficial to reducing the distance between the adjacent channel layer structures of the first device region and the second device region, thereby forming a more compact and smaller device. At the same time, the first gate isolation structure is located on the top of the isolation wall and passes through the gate structure. The cap layer covers the part of the side wall of the initial isolation wall that is higher than the top surface of the channel layer structure, which is beneficial to increasing the area of the top of the isolation wall for contacting with the first gate isolation structure, thereby increasing the process window for forming the first gate isolation structure on the top of the isolation wall, and is beneficial to reducing the probability of damage to the film layer on the side of the isolation wall (for example, the work function layer or channel layer covering the channel layer) when forming the first gate isolation structure, thereby improving the performance of the semiconductor structure.

[0009] In the formation method provided by an embodiment of the present invention, at the junction of the first device area and the second device area, an initial isolation wall covering the opposite side walls of the channel layer structure is formed on the substrate between the adjacent channel layer structures, and a cap layer is formed on the side wall of the initial isolation wall, the cap layer covers the part of the side wall of the initial isolation wall that is higher than the top surface of the channel layer structure, and there is a gap between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall serve as an isolation wall together; as the feature size of the integrated circuit continues to decrease, adjacent devices are getting closer and closer. In an embodiment of the present invention, the isolation wall isolates the first device area and the second device area, so that the adjacent first device area and the second device area are as close as possible while better ensuring the isolation effect of the adjacent devices. Being close to each other is beneficial to reducing the distance between the adjacent channel layer structures of the first device area and the second device area, thereby forming a more compact and smaller device. At the same time, a first isolation opening is formed on the top of the isolation wall to penetrate the gate structure, and a first gate isolation structure is formed in the first isolation opening. Then, the cap layer covers the part of the side wall of the initial isolation wall that is higher than the top surface of the channel layer structure, which is beneficial to increasing the area of the top of the isolation wall for contacting with the first gate isolation structure, thereby increasing the process window for forming the first isolation opening on the top of the isolation wall, and is beneficial to reducing the probability of causing damage to the film layer on the side of the isolation wall (for example, the work function layer or channel layer covering the channel layer) when forming the first gate isolation opening, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figure 4 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0012] Figures 5 to 18 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] The performance of current semiconductor structures needs to be improved. The reasons why the performance needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure.

[0014] Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1A substrate 10 is provided, including an adjacent first device area 10A and a second device area 10B. Channel layer structures 20 are respectively formed on the substrate 10 of the first device area 10A and the second device area 10B. The channel layer structure 20 includes one or more spaced channel layers 21. At the junction of the first device area 10A and the second device area 10B, an isolation wall 30 covering the opposite side walls of the channel layer structure 20 is formed on the substrate 10 between adjacent channel layer structures 20; a gate structure 40 is formed across the channel layer structure 20 and the isolation wall 30, and the gate structure 40 covers the exposed top, bottom and side walls of the channel layer 21.

[0016] refer to Figure 2 A partition opening 43 penetrating the gate structure 40 is formed on the top of the isolation wall 30 , and the partition opening 43 divides the gate structure 40 along the extending direction of the gate structure 30 .

[0017] refer to Figure 3 , a gate isolation structure 44 is formed in the isolation opening 43 .

[0018] At present, in order to make the distance between adjacent channel structures 20 smaller at the junction of the first device area 10A and the second device area 10B, an isolation wall 30 covering the sidewalls of the channel structure 20 is formed at the junction of the first device area 10A and the second device area 10B. The isolation wall 30 ensures the isolation effect of adjacent devices while the adjacent first device area 10A and the second device area 10B are as close as possible.

[0019] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In order to occupy less space, the size of the isolation wall 30 along the extension direction of the channel layer 21 is smaller. That is, the top surface area of the isolation wall 30 is smaller, and the isolation structure 44 is formed on the top of the isolation wall 30, so the process window for forming the isolation opening 43 is smaller, which makes it difficult to accurately position the isolation opening 43. Moreover, when forming the isolation opening 43, it is easy to etch to the side of the isolation wall 30 due to etching deviation, thereby damaging other film layers on the side of the isolation wall 30, such as the work function layer or the channel layer 21 covering the channel layer 21, thereby affecting the performance of the semiconductor structure.

[0020] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, including a first device area and a second device area adjacent to each other, channel layer structures are respectively formed on the substrates of the first device area and the second device area, the channel layer structure includes one or more spaced channel layers, and at the junction of the first device area and the second device area, an initial isolation wall covering the opposite side walls of the channel layer structure is formed on the substrate between the adjacent channel layer structures; forming a cap layer on the side wall of the initial isolation wall, the cap layer covering the portion of the side wall of the initial isolation wall that is higher than the top surface of the channel layer structure, there is a gap between the bottom of the cap layer and the topmost channel layer, the cap layer and the initial isolation wall serve as an isolation wall together; forming a gate structure spanning the channel layer structure, the isolation wall and the cap layer, the gate structure covering the exposed top, bottom and side walls of the channel layer; forming a first isolation opening penetrating the gate structure at the top of the isolation wall, the first isolation opening dividing the gate structure along the extension direction of the gate structure; forming a first gate isolation structure in the first isolation opening.

[0021] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In the formation method provided by an embodiment of the present invention, an isolation wall isolates the first device area and the second device area, so that the adjacent first device area and the second device area are as close as possible while better ensuring the isolation effect on the adjacent devices, which is beneficial to reducing the distance between the adjacent channel layer structures of the first device area and the second device area, thereby forming a tighter and smaller device. At the same time, a first isolation opening is formed at the top of the isolation wall to pass through the gate structure, and a first gate isolation structure is formed in the first isolation opening. The cap layer covers the part of the side wall of the initial isolation wall that is higher than the top surface of the channel layer structure, which is beneficial to increase the area of the top of the isolation wall for contact with the first gate isolation structure, thereby increasing the process window for forming the first isolation opening at the top of the isolation wall, and is beneficial to reducing the probability of damage to the film layer on the side of the isolation wall (for example, the work function layer or channel layer covering the channel layer) when forming the first gate isolation opening, thereby improving the performance of the semiconductor structure.

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0023] Figure 4 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0024] The semiconductor structure includes: a substrate 101, including a first device region 101A and a second device region 101B adjacent to each other; a channel layer structure 201, located on the substrate 101 in the first device region 101A and the second device region 101B, respectively, along the normal direction of the surface of the substrate 101 (such as Figure 4The channel layer structure 201 includes one or more spaced channel layers 211; an initial isolation wall 301 protrudes from the substrate 101 at the junction of the first device region 101A and the second device region 101B, and the initial isolation wall 301 covers the opposite side walls of the channel layer structure 201 of the first device region 101A and the second device region 101B; a cap layer 331 is located on the side wall of the initial isolation wall 301 and covers the side wall of the initial isolation wall 301 that is higher than the top surface of the channel layer structure 201, and the bottom of the cap layer 331 is adjacent to the top surface. There is a gap between the channel layer 211, and the cap layer 331 and the initial isolation wall 301 together serve as an isolation wall 341; the gate structure 401 is located on the substrate 101 and spans the channel layer structure 201 and the isolation wall 341, and the gate structure 401 covers the exposed top, bottom and sidewalls of the channel layer 211; the gate isolation structure (not marked) includes a first gate isolation structure 441 located on the top of the isolation wall 341 and passing through the gate structure 401, and the gate isolation structure divides the gate structure 401 along the extension direction of the gate structure 401.

[0025] The substrate 101 provides a process foundation for forming a semiconductor structure, wherein the semiconductor structure includes a forksheet transistor.

[0026] The base 101 includes a substrate 111 .

[0027] In this embodiment, the material of the substrate 111 is silicon. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0028] In this embodiment, the base 101 further includes an isolation layer 121 located on the substrate 121. The isolation layer 121 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, an isolation layer 121 is usually formed between an NMOS transistor and a PMOS transistor.

[0029] In this embodiment, taking the semiconductor structure as a fork-gate transistor as an example, the substrate 101 includes a first device region 101A and a second device region 101B adjacent to each other. The first device region 101A is used to form a first device, and the second device region 101B is used to form a second device.

[0030] In this embodiment, the first device region 101A includes an NMOS region, and the second device region 101B includes a PMOS region. The NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor.

[0031] As device feature sizes continue to shrink, the use of fork-gate transistors can allow for smaller spacing between adjacent NMOS transistors and PMOS transistors, thereby achieving better area scalability.

[0032] In this embodiment, the NMOS transistor formed in the first device region 101A and the PMOS transistor formed in the first device region 101B constitute a fork-gate transistor.

[0033] Accordingly, the first device region 101B and the second device region 101B constitute a third device region 101C, and the third device region 101C is used to form a fork-gate transistor.

[0034] The channel layer structure 201 includes one or more spaced channel layers 211 , and the channel layers 211 are used as channels of the semiconductor structure.

[0035] In this embodiment, the material of the channel layer 211 includes silicon, germanium, silicon germanium, or a III-V semiconductor material. As an example, the material of the channel layer 211 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0036] The initial isolation wall 301 is used to isolate the devices close to the first device area 101A and the second device area 101B, so that the devices in the adjacent first device area 101A and the second device area 101B are as close as possible while better ensuring the isolation effect on adjacent devices, which is beneficial to reducing the distance between the adjacent channel layer structures 201 of the first device area 101A and the second device area 101B, thereby forming a more compact and smaller device.

[0037] In this embodiment, the top of the initial isolation wall 301 is higher than the top of the channel layer structure 201 , thereby improving the isolation effect on adjacent devices and also serving as a support portion for the cap layer 331 .

[0038] In this embodiment, the material of the initial isolation wall 301 includes SiBCN or SiN.

[0039] SiBCN or SiN has good insulation properties, and can achieve good isolation between the devices in the first device region 101A and the second device region 101B.

[0040] The capping layer 331 is used together with the initial isolation wall 301 to serve as an isolation wall 341 to isolate the devices in the first device region 101A and the second device region 101B.

[0041] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In this embodiment, the isolation wall 341 isolates the first device area 101A and the second device area 101B, thereby ensuring a good isolation effect on the adjacent devices and making the adjacent first device area 101A and the second device area 101B as close as possible, which is conducive to reducing the distance between the adjacent channel layer structures 201 of the first device area 101A and the second device area 101B, thereby forming a more compact and smaller device. At the same time, the first gate isolation structure 441 is located on the top of the isolation wall 341. And it passes through the gate structure 401, then the cap layer 331 covers the part of the side wall of the initial isolation wall 301 that is higher than the top surface of the channel layer structure 201, which is beneficial to increase the area of the top of the isolation wall 341 for contact with the first gate isolation structure 441, thereby increasing the process window for forming the first gate isolation structure 441 on the top of the isolation wall 341, and is beneficial to reduce the probability of causing damage to the film layer on the side of the isolation wall 341 (for example, the work function layer covering the channel layer 211 or the channel layer 211) when forming the first gate isolation structure 441, thereby improving the performance of the semiconductor structure.

[0042] In this embodiment, the steps of forming the capping layer 331 include: forming a filling layer covering the channel layer structure 201 and a portion of the sidewalls of the initial isolation wall 301, wherein the top surface of the filling layer is lower than the top surface of the initial isolation wall 301; forming a capping material layer covering the filling layer and the initial isolation wall 301 exposed by the filling layer; removing the capping material layer covering the filling layer, and retaining the capping material layer covering the initial isolation wall 301 exposed by the filling layer as the capping layer 331; and removing the filling layer after forming the capping layer 331. By adjusting the process parameters for forming the capping material layer, the thickness of the capping material layer formed on the top of the initial isolation wall 301 can be adjusted. Therefore, by adjusting the thickness of the capping material layer formed on the top of the initial isolation wall 301 so as to be greater than the thickness of the capping material layer covering the filling layer, the capping material layer covering the top of the initial isolation wall 301 is retained during the step of removing the capping material layer covering the filling layer. For this reason, in this embodiment, the capping layer 331 also extends to cover the top surface of the initial isolation wall 301.

[0043] In other embodiments, the thickness of the capping material layer formed on the top of the initial isolation wall can be adjusted to be equal to the thickness of the capping material layer covering the filling layer. Then, in the step of removing the capping material layer covering the filling layer, the capping material layer covering the top of the initial isolation wall is also removed. For this purpose, the capping layer can also be located only on the side wall of the initial isolation wall.

[0044] In this embodiment, the material of the capping layer 331 includes SiC.

[0045] SiC has good insulation properties and can be used together with the initial isolation wall 301 as the isolation wall 341 , thereby achieving a good isolation effect between the devices in the first device region 101A and the second device region 101B.

[0046] It should be noted that, in this embodiment, the width of the capping layer 331 located on the sidewall of the initial isolation wall 301 should not be too large or too small. If the width of the capping layer 331 located on the sidewall of the initial isolation wall 301 is too large, the thickness of the capping material layer formed is too large, which increases the difficulty of removing the capping material layer covering the filling layer. Moreover, while appropriately increasing the area of the top of the isolation wall 341 for contact with the first gate isolation structure 441, unnecessary waste is caused. If the width of the capping layer 331 located on the sidewall of the initial isolation wall 301 is too small, the area of the top of the isolation wall 341 for contact with the first gate isolation structure 441 is increased too little, so that the process window for forming the first gate isolation structure 441 on the top of the isolation wall 341 is still small, which can easily lead to damage to the film layer on the side of the isolation wall 341 (for example, the work function layer covering the channel layer 211 or the channel layer 211) when forming the first gate isolation structure 441, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the width of the capping layer 331 located on the sidewall of the initial isolation wall 301 is 10 nm to 26 nm.

[0047] The gate structure 401 is used to control the opening or closing of the channel of the transistor.

[0048] In this embodiment, the gate structure 401 includes a gate dielectric layer 411 and a gate electrode layer 421 located on the gate dielectric layer 411 .

[0049] The gate dielectric layer 411 is used to isolate the gate structure 401 from the channel layer 211 .

[0050] The material of the gate dielectric layer 411 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the material of the gate dielectric layer 411 includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0051] The gate electrode layer 421 includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer.

[0052] The work function layer is used to adjust the threshold voltage of the transistor. For PMOS transistors, the work function layer is a P-type work function layer, and the materials of the P-type work function layer include one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. For NMOS transistors, the work function layer is an N-type work function layer, and the materials of the N-type work function layer include one or both of TiAl and TiAlC.

[0053] The electrode layer is used to electrically lead out the gate electrode layer. In this embodiment, the material of the electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0054] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0055] The gate isolation structure is used to insulate the gate structures 401 from each other. The first gate isolation structure 441 is used to insulate the gate structures 401 in the adjacent first device region 101A and the second device region 101B from each other.

[0056] In this embodiment, the gate isolation structure further includes: a second gate isolation structure 461 , which is located on the substrate 101 at the junction of the adjacent third device regions 101C and penetrates the gate structure 401 .

[0057] The second gate isolation structure 461 is used to insulate the gate structures 401 of adjacent third device regions 101C from each other.

[0058] The material of the gate isolation structure has high hardness and density, thereby reducing the probability of the gate isolation structure being damaged during the formation of the semiconductor structure, thereby ensuring the isolation performance of the gate isolation structure.

[0059] Therefore, in this embodiment, the gate isolation structure is made of silicon nitride, which also has good isolation performance. In other embodiments, the gate isolation structure can also be made of other nitrogen-containing dielectric materials.

[0060] Figures 5 to 18 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0061] refer to Figure 5A substrate 100 is provided, including an adjacent first device area 100A and a second device area 100B. Channel layer structures 200 are respectively formed on the substrate 100 of the first device area 100A and the second device area 100B. The channel layer structure 200 includes one or more spaced channel layers 210. At the junction of the first device area 100A and the second device area 100B, an initial isolation wall 300 covering the opposite side walls of the channel layer structure 200 is formed on the substrate 100 between adjacent channel layer structures 200.

[0062] The substrate 100 provides a process foundation for forming a semiconductor structure, wherein the semiconductor structure includes a forksheet transistor.

[0063] The base 100 includes a substrate 110 .

[0064] In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the substrate material may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0065] In this embodiment, the substrate 100 further includes an isolation layer 120 . The isolation layer 120 is used to achieve insulation between different devices. For example, in a CMOS manufacturing process, the isolation layer 120 is usually formed between an NMOS transistor and a PMOS transistor.

[0066] In this embodiment, taking the semiconductor structure as a fork-gate transistor as an example, the substrate 100 includes a first device region 100A and a second device region 100B adjacent to each other. The first device region 100A is used to form a first device, and the second device region 100B is used to form a second device.

[0067] In this embodiment, the first device region 100A includes an NMOS region, and the second device region 100B includes a PMOS region. The NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor, thereby forming a fork-gate transistor.

[0068] As device feature sizes continue to shrink, the use of fork-gate transistors can allow for smaller spacing between adjacent NMOS transistors and PMOS transistors, thereby achieving better area scalability.

[0069] In this embodiment, the NMOS transistor formed in the first device region 100A and the PMOS transistor formed in the first device region 100B constitute a fork-gate transistor.

[0070] Accordingly, the first device region 100B and the second device region 100B constitute a third device region 100C, and the third device region 100C is used to form a fork-gate transistor.

[0071] In this embodiment, an interlayer dielectric layer (not shown) covering the substrate 100 is formed on the substrate 100 , a gate opening 220 is formed in the interlayer dielectric layer, and a channel layer structure 200 is formed in the gate opening 220 .

[0072] The interlayer dielectric layer is used to isolate adjacent devices.

[0073] The gate opening 220 exposes the channel layer structure 200 and provides a space for the subsequent formation of a gate structure.

[0074] The channel layer structure 200 includes one or more spaced channel layers 210 , and the channel layers 210 are used to serve as channels of a semiconductor structure.

[0075] In this embodiment, the material of the channel layer 210 includes silicon, germanium, silicon germanium, or a III-V semiconductor material. As an example, the material of the channel layer 210 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.

[0076] The initial isolation wall 300 is used to isolate the devices close to the first device area 100A and the second device area 100B, so that the devices in the adjacent first device area 100A and the second device area 100B are as close as possible while better ensuring the isolation effect on adjacent devices, which is beneficial to reducing the distance between the adjacent channel layer structures 200 of the first device area 100A and the second device area 100B, thereby forming a more compact and smaller device.

[0077] In this embodiment, the top of the initial isolation wall 300 is higher than the top of the channel layer structure 200 , thereby improving the isolation effect on adjacent devices and also serving as a support portion for the subsequent formation of a cap layer.

[0078] In this embodiment, the material of the initial isolation wall 300 includes SiBCN or SiN.

[0079] SiBCN or SiN has good insulation properties, and can achieve good isolation between the devices in the first device region 100A and the second device region 100B.

[0080] Combined with reference Figures 6 to 8 A capping layer 330 is formed on the sidewall of the initial isolation wall 300. The capping layer 330 covers the portion of the sidewall of the initial isolation wall 300 that is higher than the top surface of the channel layer structure 200. There is a gap between the bottom of the capping layer 330 and the topmost channel layer 210. The capping layer 330 and the initial isolation wall 300 together serve as an isolation wall 340.

[0081] The capping layer 330 is used together with the initial isolation wall 300 to serve as an isolation wall 340 to isolate the devices in the first device region 100A and the second device region 100B.

[0082] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In this embodiment, the isolation wall 340 isolates the first device area 100A and the second device area 100B, thereby ensuring a good isolation effect on the adjacent devices and making the adjacent first device area 100A and the second device area 100B as close as possible, which is conducive to reducing the distance between the adjacent channel layer structures 200 of the first device area 100A and the second device area 100B, thereby forming a more compact and smaller device. At the same time, the first through-gate structure is subsequently formed on the top of the isolation wall 340. A partition opening is formed in the first partition opening, and a first gate partition structure is formed in the first partition opening. The cap layer 330 covers the portion of the side wall of the initial isolation wall 300 that is higher than the top surface of the channel layer structure 200, which is beneficial to increasing the area of the top of the isolation wall 340 for contact with the first gate partition structure, thereby increasing the process window for forming the first partition opening on the top of the isolation wall 340, and is beneficial to reducing the probability of damage to the film layer on the side of the isolation wall 340 (for example, the work function layer covering the channel layer 210 or the channel layer 210) when forming the first gate partition structure, thereby improving the performance of the semiconductor structure.

[0083] In this embodiment, the steps of forming the capping layer 330 include: forming a filling layer covering the channel layer structure 200 and a portion of the sidewalls of the initial isolation wall 300, wherein the top surface of the filling layer is lower than the top surface of the initial isolation wall 300; forming a capping material layer covering the filling layer and the portion of the initial isolation wall 300 exposed by the filling layer; removing the capping material layer covering the filling layer, retaining the portion of the capping material layer covering the initial isolation wall 300 exposed by the filling layer as the capping layer 330; and removing the filling layer after forming the capping layer 330. The thickness of the capping material layer formed on the top of the initial isolation wall 300 can be adjusted by adjusting the process parameters for forming the capping material layer. Therefore, by adjusting the thickness of the capping material layer formed on the top of the initial isolation wall 300 so as to be greater than the thickness of the capping material layer covering the filling layer, the capping material layer covering the top of the initial isolation wall 300 is retained during the step of removing the capping material layer covering the filling layer. Therefore, in this embodiment, the capping layer 330 also covers the top surface of the initial isolation wall 300.

[0084] In other embodiments, the thickness of the capping material layer formed on the top of the initial isolation wall can be adjusted to be equal to the thickness of the capping material layer covering the filling layer. Then, in the step of removing the capping material layer covering the filling layer, the capping material layer covering the top of the initial isolation wall is also removed. For this purpose, the capping layer can also be located only on the side wall of the initial isolation wall.

[0085] In this embodiment, the material of the capping layer 330 includes SiC.

[0086] SiC has good insulation properties and can be used together with the initial isolation wall 300 as the isolation wall 340 , thereby achieving a good isolation effect between the devices in the first device region 100A and the second device region 100B.

[0087] It should be noted that, in this embodiment, the width of the capping layer 330 located on the sidewall of the initial isolation wall 300 should not be too large or too small. If the width of the capping layer 330 located on the sidewall of the initial isolation wall 300 is too large, the thickness of the capping material layer formed is too large, which increases the difficulty of removing the capping material layer covering the filling layer. Moreover, while the area of the top of the isolation wall 340 used for contact with the first gate isolation structure 440 is appropriately increased, unnecessary waste is caused. If the width of the capping layer 330 located on the sidewall of the initial isolation wall 300 is too small, the area of the top of the isolation wall 340 used for contact with the first gate isolation structure 440 is increased too little, so that the process window for forming the first gate isolation structure 440 on the top of the isolation wall 340 is still small, which can easily lead to damage to the film layer on the side of the isolation wall 340 (for example, the work function layer covering the channel layer 210 or the channel layer 210) when forming the first gate isolation structure 440, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the width of the capping layer 330 located on the sidewall of the initial isolation wall 300 is 10 nm to 26 nm.

[0088] Specifically, refer to Figure 5 The step of forming a capping layer 330 on the sidewall of the initial isolation wall 300 includes: forming a filling layer 310 covering the channel layer structure 200 and part of the sidewall of the initial isolation wall 300, and the top surface of the filling layer 310 is lower than the top surface of the initial isolation wall 300.

[0089] The filling layer 310 provides a process basis for the subsequent formation of a cap material layer. The filling layer 310 covers the channel layer structure 200 and can protect the channel layer structure 200 during the step of forming the cap material layer. The top surface of the filling layer 310 is lower than the top surface of the initial isolation wall 300, so that the cap layer 330 can be formed on the side wall of the initial isolation wall 300, and the area of the side wall of the initial isolation wall 300 covered by the cap layer 330 can be controlled by controlling the height of the filling layer 310.

[0090] In this embodiment, the filling layer 310 is formed by a chemical vapor deposition process.

[0091] The chemical vapor deposition process has a good deposition effect and a high gap filling capability, can form a high-quality filling layer 310 , and can reduce voids in the film layer.

[0092] In this embodiment, the filling layer 310 needs to be removed later, so the filling layer 310 needs to be made of a material that is easy to remove. For this reason, in this embodiment, the material of the filling layer 310 includes an advanced patterning film (APF) material, which is easy to remove the filling layer 310 later and helps to reduce damage to the channel layer 210 and the initial isolation wall 300 during the removal process.

[0093] refer to Figure 7 , forming a capping material layer 320 covering the filling layer 310 and the initial isolation wall 300 exposed by the filling layer 310 .

[0094] The capping material layer 320 is used to directly form the capping layer 330 .

[0095] In this embodiment, the process of forming the capping material layer 320 covering the filling layer 310 and the initial isolation wall 300 exposed by the filling layer 310 includes an atomic layer deposition process or a chemical vapor deposition process.

[0096] The atomic layer deposition process or the chemical vapor deposition process has a good deposition effect and a good step coverage capability, so that the cap material layer 320 can better cover the filling layer 310 and the initial isolation wall 300 exposed by the filling layer 310. Moreover, the atomic layer deposition process or the chemical vapor deposition process can adjust the cap material layer 320 formed on the top of the initial isolation wall 300 by adjusting the process parameters.

[0097] Accordingly, in this embodiment, the material of the capping material layer 320 includes SiC.

[0098] refer to Figure 8 , the capping material layer 320 covering the filling layer 310 is removed, and the capping material layer 320 covering the initial isolation wall 300 exposed by the filling layer 310 is retained as the capping layer 330 .

[0099] The cap material layer 320 covering the filling layer 310 is removed to form the cap layer 330 , while exposing the filling layer 310 in preparation for subsequent removal of the filling layer 310 .

[0100] In other embodiments, when removing the capping material layer covering the filling layer, the capping material layer located on the top of the initial isolation wall may also be removed simultaneously.

[0101] In this embodiment, the process of removing the capping material layer 320 covering the filling layer 310 and retaining the capping material layer 320 covering the initial isolation wall 300 exposed from the filling layer 310 as the capping layer 330 includes an anisotropic etching process.

[0102] The anisotropic etching process includes an anisotropic dry etching process. The anisotropic dry etching process is more directional and is conducive to forming the capping layer 330 with higher sidewall quality.

[0103] refer to Figure 9 After forming the cap layer 330 , the method further includes: removing the filling layer 310 .

[0104] The filling layer 310 is removed to expose various surfaces of the channel layer 210 , in preparation for the subsequent formation of a gate structure covering the channel layer 210 .

[0105] In this embodiment, the process of removing the filling layer 310 includes an isotropic etching process.

[0106] The isotropic etching process includes an isotropic wet etching process. The isotropic wet etching process can achieve a larger etching selectivity ratio, thereby completely removing the filling layer 310 while reducing damage to the channel layer 210 .

[0107] refer to Figure 10 , forming a gate structure 400 spanning the channel layer structure 200 and the isolation wall 340 , and the gate structure 400 covers the exposed top, bottom and sidewalls of the channel layer 210 .

[0108] The gate structure 400 is used to control the opening or closing of the channel of the transistor.

[0109] In this embodiment, the gate structure 400 includes a gate dielectric layer 410 and a gate electrode layer 420 located on the gate dielectric layer 410 .

[0110] The gate dielectric layer 410 is used to isolate the gate structure 400 from the channel layer 210 .

[0111] The material of the gate dielectric layer 410 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the material of the gate dielectric layer 410 includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0112] The gate electrode layer 420 includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer.

[0113] The work function layer is used to adjust the threshold voltage of the transistor. For PMOS transistors, the work function layer is a P-type work function layer, and the materials of the P-type work function layer include one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. For NMOS transistors, the work function layer is an N-type work function layer, and the materials of the N-type work function layer include one or both of TiAl and TiAlC.

[0114] The electrode layer is used to electrically lead out the gate electrode layer. In this embodiment, the material of the electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0115] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0116] Combined with reference Figures 11 to 15 A first isolation opening 430 penetrating the gate structure 400 is formed on the top of the isolation wall 340 . The first isolation opening 430 divides the gate structure 400 along an extension direction of the gate structure 400 .

[0117] The first isolation opening 430 is used to provide a space for subsequently forming a first gate isolation structure.

[0118] In this embodiment, an anisotropic etching process is used to form the first isolation opening 430 penetrating the gate structure 400 .

[0119] The anisotropic etching process includes an anisotropic dry etching process. The longitudinal etching rate of the anisotropic dry etching process is much greater than the lateral etching rate, and can obtain equally precise graphic conversion, which is conducive to accurately positioning the bottom of the first partition opening 430 at the top of the isolation wall 340. At the same time, the anisotropic dry etching process has good directionality, which is conducive to improving the side wall morphology quality and dimensional accuracy of the first partition opening 430.

[0120] Specifically, refer to Figure 11 The step of forming a first isolation opening 430 penetrating the gate structure 400 on the top of the isolation wall 340 includes: forming a mask layer 500 covering the gate structure 400 .

[0121] The mask layer 500 is used as an etching mask for etching the gate structure 400 .

[0122] In this embodiment, the material of the mask layer 500 includes one or more of silicon oxide and silicon nitride, that is, the mask layer 500 can have a single-layer structure or a stacked-layer structure. As an example, the material of the mask layer 500 is silicon nitride, that is, the mask layer 500 has a single-layer structure. Silicon nitride has a relatively high hardness, which helps to better protect the top of the gate structure 400 during the etching process.

[0123] Specifically, a chemical vapor deposition process is used to form the mask layer 500 covering the gate structure 400 .

[0124] Combined with reference Figure 11 and Figure 12 , the mask layer 500 located above the isolation wall 340 is removed to form a mask opening 510 exposing the gate structure 400 .

[0125] The gate structure 400 is etched through the mask opening 510 to improve the accuracy of pattern transfer.

[0126] Specifically, refer to Figure 11 , a photoresist 600 covering the mask layer 500 is formed, and a pattern opening 610 is formed in the photoresist 600 .

[0127] The mask layer 500 is etched through the pattern opening 610 to form a mask opening 510 .

[0128] refer to Figure 12 In the step of removing the mask layer 500 located above the isolation wall 340 , a portion of the mask layer 500 is removed to form a mask opening 510 .

[0129] In this embodiment, it is necessary to subsequently form a protective material layer covering the bottom and side walls of the mask opening 510, and then remove the protective material layer covering the bottom of the mask opening 510. Therefore, a portion of the thickness of the mask layer 500 is removed, and the remaining thickness of the mask layer 500 is retained at the bottom of the mask opening 510, which is beneficial to reduce or avoid damage to the gate structure 400 in the process of removing the protective material layer covering the bottom of the mask opening 510.

[0130] In other embodiments, a mask opening penetrating the mask layer may be formed, the mask opening exposing the gate structure, and the exposed gate structure is directly removed through the mask opening to form the first isolation opening.

[0131] Combined with reference Figure 13 and Figure 14 After forming the mask opening 510 , before removing the gate structure 400 located on the top of the isolation wall 340 along the mask opening 510 , the method further includes: forming a protection layer 530 covering the sidewalls of the mask opening 510 .

[0132] The protective layer 530 is used to reduce the opening size of the mask opening 510, thereby reducing the top size of the first partition opening 430 in the step of forming the first partition opening 430, thereby reducing the bottom size of the first partition opening 430, which is beneficial to ensure that the first partition opening 430 is formed at the top of the isolation wall 340.

[0133] After the first isolation opening 430 is formed, the protective layer 530 needs to be removed. The protective layer 530 needs to be made of a material that is easy to remove. Therefore, in this embodiment, the material of the protective layer 530 includes silicon oxide.

[0134] Specifically, refer to Figure 13 The step of forming the protection layer 530 on the sidewall of the mask opening 510 includes: forming a protection material layer 520 covering the bottom and sidewall of the mask opening 510 and the top of the mask layer 500 .

[0135] The protective material layer 520 is used to directly form the protective layer 530 .

[0136] In this embodiment, the protective material layer 520 also covers the sidewalls of the pattern opening 610 and the top of the photoresist 600 .

[0137] In other embodiments, the photoresist may be removed after forming the mask opening and before forming the protective material layer. In the step of forming the protective material layer, the protective material layer only covers the bottom and sidewalls of the mask opening and the top of the mask layer.

[0138] In this embodiment, the protective material layer 520 is formed by an atomic layer deposition process.

[0139] The protective material layer 520 formed by the atomic layer deposition process has good thickness uniformity and good step coverage, so that the protective material layer 520 can conformally cover the bottom and sidewalls of the mask opening 510 and the top of the mask layer 500.

[0140] Accordingly, the material of the protective material layer 520 includes silicon oxide.

[0141] refer to Figure 14 , the protective material layer 520 located at the bottom of the mask opening 510 and the top of the mask layer 500 is removed, and the protective material layer 520 located at the sidewall of the mask opening 510 is retained as the protective layer 530.

[0142] The protective material layer 520 at the bottom of the mask opening 510 is removed to expose the remaining thickness of the mask layer 500 in preparation for forming the first isolation opening 430 .

[0143] In this embodiment, an anisotropic dry etching process is used to remove the protective material layer 520 at the bottom of the mask opening 510 and the top of the mask layer 500. The anisotropic dry etching process is more directional and is conducive to forming a protective layer 530 with better sidewall quality.

[0144] refer to Figure 15 , the gate structure 400 located on the top of the isolation wall 340 is removed along the mask opening 510 to form a first isolation opening 430 .

[0145] Accordingly, the remaining thickness of the mask layer 500 is removed along the mask opening 510 .

[0146] refer to Figure 16 After forming the first isolation opening 430 , the method further includes: removing the protective layer 530 .

[0147] The protective layer 530 is removed to prepare for the subsequent formation of a first gate isolation structure in the first isolation opening 430.

[0148] In this embodiment, an isotropic wet etching process is used to remove the protective layer 530. The isotropic wet etching process can achieve a large etching selectivity ratio, thereby completely removing the protective layer 530 while reducing damage to the gate structure 400 and the mask layer 500.

[0149] In this embodiment, after forming the first isolation opening 430 , the process further includes: removing the photoresist 600 .

[0150] It should be noted that, in this embodiment, an isotropic wet etching process is used to remove the protective layer 530 and the photoresist 600 in the same step, thereby improving process efficiency.

[0151] refer to Figure 17 , a first gate isolation structure 440 is formed in the first isolation opening 430 .

[0152] The first gate isolation structure 440 is used to insulate the gate structures 400 in the adjacent first device region 100A and the second device region 100B from each other.

[0153] The material of the first gate isolation structure 440 has high hardness and density, thereby reducing the probability of the first gate isolation structure 440 being damaged during the formation of the semiconductor structure, thereby ensuring the isolation performance of the first gate isolation structure 440.

[0154] Therefore, in this embodiment, the material of the first gate isolation structure 440 is silicon nitride, which also has good isolation performance. In other embodiments, the first gate isolation structure can also be made of other nitrogen-containing dielectric materials.

[0155] Continue to refer Figure 17 After forming the first gate isolation structure 440 , the formation method further includes: removing the gate structure 400 located at the junction of the adjacent third device region 100C to form a second isolation opening 450 , and the second isolation opening 450 divides the gate structure 400 along the extension direction of the gate structure 400 .

[0156] The second isolation opening 450 is used to provide a space for subsequently forming a second gate isolation structure.

[0157] In this embodiment, an anisotropic etching process is used to form the second isolation opening 450 penetrating the gate structure 400 .

[0158] refer to Figure 18 , a second gate isolation structure 460 is formed in the second isolation opening 450 .

[0159] The second gate isolation structure 460 is used to insulate the gate structures 400 in adjacent third device regions 100C from each other.

[0160] Accordingly, in this embodiment, the material of the second gate isolation structure 460 is silicon nitride, which also has good isolation performance. In other embodiments, the second gate isolation structure can also be made of other nitrogen-containing dielectric materials.

[0161] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a first device region and a second device region adjacent to each other; A channel layer structure is respectively located on the substrate of the first device region and the second device region, and along the normal direction of the substrate surface, the channel layer structure includes one or more spaced channel layers; an initial isolation wall protruding from the substrate at the junction of the first device region and the second device region, the initial isolation wall covering opposite sidewalls of the channel layer structure of the first device region and the second device region; a capping layer, located on the sidewalls of the initial isolation wall and covering a portion of the sidewalls of the initial isolation wall that is higher than the top surface of the channel layer structure, with a gap between the bottom of the capping layer and the topmost channel layer, and the capping layer and the initial isolation wall acting together as an isolation wall; a gate structure, located on the substrate and spanning the channel layer structure and the isolation wall, wherein the gate structure covers the exposed top, bottom and sidewalls of the channel layer; The gate partition structure comprises a first gate partition structure located on the top of the isolation wall and penetrating the gate structure, wherein the gate partition structure divides the gate structure along an extension direction of the gate structure.

2. The semiconductor structure according to claim 1, wherein The capping layer also extends to cover the top surface of the initial isolation wall.

3. The semiconductor structure according to claim 1, wherein: The first device region and the second device region constitute a third device region; The gate isolation structure further includes: a second gate isolation structure, which is located on the substrate at the junction of the adjacent third device regions and penetrates the gate structure.

4. The semiconductor structure according to claim 1, wherein: The material of the initial isolation wall includes SiBCN or SiN.

5. The semiconductor structure according to claim 1, wherein The material of the capping layer includes SiC.

6. The semiconductor structure according to claim 1, wherein The width of the capping layer located on the sidewall of the initial isolation wall is 10 nm to 26 nm.

7. The semiconductor structure according to claim 1, wherein The gate isolation structure is made of SiN.

8. The semiconductor structure according to claim 1, wherein: The material of the channel layer includes silicon, germanium, silicon germanium or Group III-V semiconductor materials.

9. The semiconductor structure according to claim 1, wherein: The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a first device region and a second device region adjacent to each other, wherein a channel layer structure is formed on the substrate of each of the first device region and the second device region, wherein the channel layer structure comprises one or more spaced channel layers, and at a junction between the first device region and the second device region, an initial isolation wall is formed on the substrate between adjacent channel layer structures, covering opposite sidewalls of the channel layer structure; forming a capping layer on the sidewall of the initial isolation wall, the capping layer covering a portion of the sidewall of the initial isolation wall that is higher than the top surface of the channel layer structure, with a gap between the bottom of the capping layer and the topmost channel layer, the capping layer and the initial isolation wall acting together as an isolation wall; forming a gate structure spanning the channel layer structure and the isolation wall, wherein the gate structure covers the exposed top, bottom, and sidewalls of the channel layer; A first isolation opening is formed on the top of the isolation wall, penetrating the gate structure, wherein the first isolation opening divides the gate structure along an extension direction of the gate structure; A first gate isolation structure is formed in the first isolation opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a capping layer on the sidewall of the initial isolation wall, the capping layer also covers the top surface of the initial isolation wall.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming a capping layer on the sidewall of the initial isolation wall includes: forming a filling layer covering the channel layer structure and a portion of the sidewall of the initial isolation wall, wherein the top surface of the filling layer is lower than the top surface of the initial isolation wall; forming a capping material layer covering the filling layer and the initial isolation wall exposed from the filling layer; removing the capping material layer covering the filling layer, and retaining the capping material layer covering the initial isolation wall exposed from the filling layer as the capping layer; After forming the cap layer, the method further includes: removing the filling layer.

13. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming a first isolation opening penetrating the gate structure on the top of the isolation wall comprises: forming a mask layer covering the gate structure; removing the mask layer above the isolation wall to form a mask opening exposing the gate structure; The gate structure located on the top of the isolation wall is removed along the mask opening to form a first isolation opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of removing the mask layer located above the isolation wall, a portion of the mask layer is removed to form the mask opening; After forming the mask opening and before removing the gate structure located on the top of the isolation wall along the mask opening, the method further includes: forming a protection layer covering the sidewalls of the mask opening; After forming the first isolation opening, the method further includes: removing the protective layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The step of forming a protective layer on the sidewall of the mask opening includes: forming a protective material layer covering the bottom and sidewall of the mask opening and the top of the mask layer; The protective material layer located at the bottom of the mask opening and the top of the mask layer is removed, and the protective material layer located at the sidewall of the mask opening is retained as a protective layer.

16. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, the first device region and the second device region constitute a third device region; After forming the first gate isolation structure, the forming method further includes: removing the gate structure located at the intersection of adjacent third device regions to form a second isolation opening, wherein the second isolation opening divides the gate structure along an extension direction of the gate structure; A second gate isolation structure is formed in the second isolation opening.

17. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the cap material layer covering the filling layer and the initial isolation wall exposed by the filling layer includes an atomic layer deposition process or a chemical vapor deposition process.

18. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing the capping material layer covering the filling layer and retaining the capping material layer covering the initial isolation wall exposed from the filling layer as the capping layer includes an anisotropic etching process.

19. The method for forming a semiconductor structure according to claim 12, wherein: The process of removing the filling layer includes an isotropic etching process.

20. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, an interlayer dielectric layer covering the substrate is formed on the substrate, a gate opening is formed in the interlayer dielectric layer, and a channel layer structure is formed in the gate opening.

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