Chip interconnection, base island interconnection and wire bonding structure of electronic device

Abstract

The present invention relates to a chip interconnection, base island interconnection and wire bonding structure of an electronic device, belonging to the technical field of electronic device packaging, and is used to solve the parasitic inductance problem caused by long bonding wires. The base island interconnection structure includes a first base island, a second base island and a first wiring substrate, the first base island includes a first chip; the second base island is spaced apart from the first base island; the first wiring substrate is connected between the first base island and the second base island, and the first wiring substrate includes one or more non-metallic wire conductive circuits; wherein the first chip is electrically connected to the one or more non-metallic wire conductive circuits on the first wiring substrate, and the one or more non-metallic wire conductive circuits extend to the second base island. The present invention uses a wiring substrate to reduce the lead length when interconnecting pins of different chips, thereby reducing the parasitic inductance and reducing the influence of the parasitic inductance on the performance of electronic devices during packaging.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic device packaging, and in particular to a chip interconnection, base island interconnection and wire bonding structure of an electronic device. Background Art

[0002] Electronic devices are usually composed of several interconnected chips. In order to realize the interconnection between chips and facilitate packaging, the traditional packaging structure of electronic devices mainly includes a substrate and a base island set thereon. The same chip is mounted on the same base island, and the signal is led out on the nearest pin. The chips between different base islands are interconnected by bonding wires. For example, a Chinese patent application with publication number CN110634856A and invention name "A hybrid packaging structure with flip-chip and wire bonding and its packaging method" discloses a chip packaging structure, in which the wire-bonded chip and the substrate are electrically connected by metal wires. For another example, a Chinese patent application with publication number CN115188720 A and invention name "SIP module based on lead frame vertical packaging" discloses a semiconductor module package, in which the lead frame and the IC chip layer are electrically connected by wires. Since different base islands or different chips are mainly connected by bonding wires, when the distance between two base islands or two chips or between a chip and a base island is far, the length of the bonding wire is large, and the long bonding wire is bound to produce parasitic inductance, which to a certain extent interferes with the signal transmission between chips, thereby affecting the overall performance of the electronic device. Summary of the invention

[0003] In view of the technical problems existing in the prior art, the present invention proposes a chip interconnection, base island interconnection and wire bonding structure of an electronic device, which is used to reduce the length of the bonding wire and further reduce the parasitic inductance generated by the long bonding wire.

[0004] In order to solve the above-mentioned technical problems, according to one aspect of the present invention, the present invention provides a base island interconnection structure, including a first base island, a second base island and a first wiring substrate, the first base island includes a first chip; the second base island is spaced apart from the first base island; the first wiring substrate is connected between the first base island and the second base island, the first wiring substrate includes one or more non-metallic wire conductive circuits; wherein the first chip is electrically connected to the one or more non-metallic wire conductive circuits on the first wiring substrate, and the one or more non-metallic wire conductive circuits extend to the second base island.

[0005] In order to solve the above-mentioned technical problems, according to another aspect of the present invention, the present invention provides a wire bonding structure, including a first base island, a second base island and a first wiring substrate, wherein the second base island is separated from the first base island and includes a frame electrode; the first wiring substrate is connected between the first base island and the second base island, and the first wiring substrate includes a non-metallic wire conductive line, which includes a first area, and the first area extends from the vicinity of the first base island to the second base island; wherein the first base island or the first wiring substrate includes a first chip, and the first chip is electrically connected to the first area on the first wiring substrate.

[0006] In order to solve the above-mentioned technical problems, according to another aspect of the present invention, the present invention provides a chip interconnection structure, including: a first base island, a second base island and a first wiring substrate, the second base island is spaced apart from the first base island and includes a frame electrode; the first wiring substrate is connected between the first base island and the second base island, the first wiring substrate includes a non-metallic wire conductive line, which includes a first area and a second area, the second area is at least partially arranged on the first base island, the second area includes a first chip and a second chip, the back electrodes of the first chip and the second chip are electrically connected through the second area, and the front electrodes of the first chip and the second chip are electrically connected through metal wires.

[0007] In order to solve the above technical problem, according to another aspect of the present invention, the present invention provides an electronic device, including the aforementioned island interconnection structure, or the aforementioned wire bonding structure, or the aforementioned chip interconnection structure.

[0008] The present invention adopts a wiring substrate to reduce the lead length when different chips are interconnected, thereby reducing the parasitic inductance and reducing the influence of the parasitic inductance on the performance of the electronic device during packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0010] Figure 1A is a schematic diagram of an existing base island interconnection structure according to an embodiment of the present invention;

[0011] Figure 1B is with Figure 1A The corresponding schematic diagram of the base island interconnection structure provided by the present invention;

[0012] Figure 2A is a schematic diagram of the front structure of a first wiring substrate according to an embodiment of the present invention;

[0013] Figure 2B yes Figure 2A A schematic diagram of the back structure of the first wiring substrate;

[0014] Figure 2C yes Figure 2A Schematic diagram of the cross-sectional structure at AA in the middle;

[0015] Figure 3A is a schematic diagram of an existing base island interconnection structure according to another embodiment of the present invention;

[0016] Figure 3B is with Figure 3A The corresponding schematic diagram of the base island interconnection structure provided by the present invention;

[0017] Figure 4A is a schematic diagram of an existing base island interconnection structure according to another embodiment of the present invention;

[0018] Figure 4B is with Figure 4A The corresponding schematic diagram of the base island interconnection structure provided by the present invention;

[0019] Figure 5 is a schematic diagram of a base island interconnection structure according to another embodiment of the present invention;

[0020] Figure 6 is a schematic diagram of a three-dimensional structure of a base island interconnection structure according to another embodiment of the present invention;

[0021] Figure 7 is a schematic diagram of a base island interconnection structure according to another embodiment of the present invention; and

[0022] Figure 8 This is a schematic diagram of the traditional packaging structure of power devices. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0025] Generally speaking, increasing the length of the wire and reducing the diameter of the wire will increase the parasitic inductance, and when the diameter of the wire (such as thick aluminum wire) varies within the range of 0.2mm to 0.5mm, the variation range of the parasitic inductance is extremely small and can be ignored. Therefore, the most effective way to reduce the parasitic inductance is to reduce the length of the lead. Based on this theory, the present invention uses a wiring substrate for double-sided wiring to achieve conduction between the pins of different chips, thereby effectively reducing the lead length when different chips are interconnected, thereby achieving the purpose of reducing parasitic inductance. Among them, the wiring substrate can be a substrate covered with conductive metal on both sides, and the substrate material is, for example, commonly used alumina ceramics or other types of ceramics, such as aluminum nitride ceramics, beryllium oxide ceramics or boron nitride ceramics. In addition, the substrate material can also be other materials, such as an organic substrate with an interconnection layer, the main materials of which are resin, polytetrafluoroethylene, and a metal layer, or a metal core substrate, the main materials of which are a metal core and a resin insulating layer, wherein the metal core can be a metal or a synthetic metal. The conductive metal on the wiring substrate can be any metal used for wiring, such as copper, gold, silver or aluminum. Based on the wiring substrate, the present invention provides a base island interconnection structure, a wire bonding structure, a chip interconnection structure and electronic devices based on these structures, which are specifically described as follows.

[0026] Figure 1A is a schematic diagram of an existing base island interconnection structure according to an embodiment of the present invention, Figure 1B is with Figure 1A The corresponding schematic diagram of the base island interconnection structure provided by the present invention. In this embodiment, the base island interconnection structure includes a first base island 1 and a second base island 2. The first base island 1 is mounted with a first chip 11. Some pins of the first chip 11 need to be electrically connected to the pads on the first base island 1, and another part of the pins of the first chip 11 need to be electrically connected to the pads on the second base island 2. In the traditional packaging structure, Figure 1A As shown, some pins of the first chip 11 are electrically connected to the pads on the first base island 1 through the first lead 111', and some pins of the first chip 11 are electrically connected to the pads on the second base island 2 through the second lead 112'. Since the second base island 2 is spaced a certain distance from the first base island 1, the length of the second lead 112' is relatively long. Figure 1BThe base island interconnection structure provided by the present invention also includes a first wiring substrate 3a. The first wiring substrate 3a is connected between the first base island 1 and the second base island 2. The front side of the first wiring substrate 3a includes a non-metallic wire conductive circuit 31a. The non-metallic wire conductive circuit 31a extends to the second base island 2 and is electrically connected to the second base island 2. Some pins of the first chip 11 are electrically connected to the pads on the first base island 1 through the first lead 111, and another pin of the first chip 11 is electrically connected to the non-metallic wire conductive circuit 31a on the front side of the first wiring substrate 3a through the second lead 112. Since the first wiring substrate 3a is electrically connected to the second base island 2, the electrical connection between the first chip 11 on the first base island 1 and the second base island 2 is realized. Figure 1A As can be seen from the structural comparison in FIG. 1 , the length of the second lead 112 is much smaller than the length of the second lead 112′. Figure 1B The island interconnect structure reduces the parasitic inductance caused by the long leads of the chip.

[0027] One or more non-metallic wire conductive circuits on the first wiring substrate of the present invention are connected to the electrical connection portion of the second base island by non-metallic wires. Figure 2A is a schematic diagram of the front structure of a first wiring substrate according to an embodiment of the present invention, Figure 2B yes Figure 2A Schematic diagram of the back structure of the first wiring substrate. Figure 2C yes Figure 2ASchematic diagram of the cross-sectional structure at AA in FIG. The front of the first wiring substrate 3a in this embodiment is covered with a conductive metal layer 30, which can be used as a non-metallic wire conductive circuit alone, or a plurality of isolation regions can be etched out according to wiring needs, thereby forming one or more non-metallic wire conductive circuits on the front of the first wiring substrate. A through hole 32 is provided on the first wiring substrate at a position where electrical connection with the pad on the second base island 2 is required, and the conductive metal layer 30 extends from the front surface to the side wall of the through hole, or continues to extend to the back of the first wiring substrate 3a. In one embodiment, in the base island interconnection structure, in order to make the first wiring substrate 3a and the second base island have an electrical connection relationship, the through hole 32 in the first wiring substrate 3a is opposite to the conductive area (such as the pad) on the second base island, and the entire through hole 32 is electroplated with metal, so that the first wiring substrate 3a and the second base island have a reliable electrical connection relationship. In another embodiment, the conductive metal layer on the back of the first wiring substrate 3 extends from the through hole 32 to the conductive area on the second base island. When the first wiring substrate 3a and the second base island are welded together, the conductive metal layer on the back of the first wiring substrate 3a and the conductive area on the second base island can form a reliable electrical connection relationship. Among them, the position and shape of the through hole are not limited, and the metal of the conductive metal layer on the first wiring substrate 3a and the metal of the conductive area on the second base island can be the same or different. On the back of the first wiring substrate 3a, the area that needs to be connected to the first base island 1 and the second base island 2 is covered with solder to form welding areas 33 and 34. The solder is usually a welding metal, such as titanium, nickel, silver, etc. There is an insulating area 35 between the two welding areas 33 and 34, which is used to isolate the welding areas 33 and 34.

[0028] Figure 3A is a schematic diagram of an existing base island interconnection structure according to another embodiment of the present invention, Figure 3B is with Figure 3A The corresponding schematic diagram of the base island interconnection structure provided by the present invention. In this embodiment, the base island interconnection structure includes a first base island 1 and a second base island 2. The first chip 11 is arranged on a ceramic pad 3'. Some pins of the first chip 11 need to be electrically connected to the pads on the first base island 1, and the other pins need to be electrically connected to the pads on the second base island 2. A conductive area can be provided on the ceramic pad 3' for electrical connection with other chips or base islands. In a conventional packaging structure, such as Figure 3A As shown, some pins of the first chip 11 are electrically connected to the pads on the first base island 1 through the first lead 111', and another part of the pins of the first chip 11 are electrically connected to the pads on the second base island 2 through the second lead 112'. Since the second base island 2 is spaced a certain distance from the first base island 1, the length of the second lead 112' is relatively long. Figure 3B The base island interconnection structure provided by the present invention adopts the first wiring substrate 3b to replace Figure 3AThe ceramic gasket 3' in the first wiring substrate 3b includes a first area 311b and a second area 312b separated by an insulating area. In the present embodiment, the first area 311b and the second area 312b respectively constitute a non-metallic wire conductive circuit. The first chip 11 is arranged on the first area 311b and electrically connected thereto. In one embodiment, due to the special requirements of the chip layout, or when the first chip 11 is a power chip, due to the heat dissipation requirements of the power chip, the first chip 11 is provided with pins or electrodes on the front and back sides. The electrodes or pins on the back side of the first chip 11 are welded to the first area 311b, and some of the pins on the front side of the first chip 11 are electrically connected to the pads on the first base island 1 through the first lead 111, and some of the pins on the front side of the first chip 11 are electrically connected to the second area 312b on the first wiring substrate 3 through the second lead 112, and the second area 312b is electrically connected to the pads on the second base island 2. Figure 3A As can be seen from the structural comparison in FIG. 1 , the length of the second lead 112 is much smaller than the length of the second lead 112′. Figure 3B The island interconnect structure reduces the parasitic inductance caused by the long leads of the chip.

[0029] In one embodiment, the non-metallic wire conductive circuit is respectively two complete conductive areas. In other embodiments, as required, the non-metallic wire conductive circuit can be composed of a plurality of conductive areas of different shapes connected together.

[0030] Figure 4A is a schematic diagram of an existing base island interconnection structure according to another embodiment of the present invention, Figure 4B is with Figure 4A Corresponding schematic diagram of the base island interconnection structure provided by the present invention. In the present embodiment, the base island interconnection structure includes a first base island 1 and a second base island 2, and a first chip 11 and a second chip 12 are arranged on a ceramic gasket 3'. Some pins of the first chip 11 need to be electrically connected to the pads on the first base island 1, and another part of the pins need to be electrically connected to the pads on the second base island 2. Some pins of the second chip 12 need to be electrically connected to the pads on the first base island 1. When there is an electrical connection between the first chip 11 and the second chip 12, the two are either connected by leads or by a conductive area on the ceramic gasket 3'. A circuit can be set in the ceramic gasket 3' for connecting to other chips or base islands. In a traditional packaging structure, such as Figure 3A As shown, some pins of the first chip 11 are electrically connected to the pads on the first base island 1 through the first lead 111', and some pins of the first chip 11 are electrically connected to the pads on the second base island 2 through the second lead 112'. Figure 4B The base island interconnection structure provided by the present invention adopts the first wiring substrate 3b to replace Figure 4AThe ceramic gasket 3' in the first wiring substrate 3b includes a first area 311b and a second area 312b separated by an insulating area. The first chip 11 is mounted on the first area 311b and electrically connected to it. Some pins of the first chip 11 are electrically connected to the pads on the first base island 1 through the first lead 111, and some pins of the first chip 11 are electrically connected to the second area 312b on the first wiring substrate 3b through the second lead 112. The second area 312b is electrically connected to the pads on the second base island 2. Figure 4A As can be seen from the structural comparison in FIG. 1 , the length of the second lead 112 is much smaller than the length of the second lead 112′. Figure 4B The island interconnect structure reduces the parasitic inductance caused by the long leads of the chip.

[0031] Figure 5 FIG. 1 is a schematic diagram of a base island interconnection structure according to another embodiment of the present invention. Figure 4B In comparison, the present embodiment further includes a third chip 13. The third chip 13 is located outside the first wiring substrate 3b, the third chip 13 is electrically connected to the first region 311b of the first wiring substrate 3b through a metal wire 131, and the third chip 13 is electrically connected to a circuit of the first base island 1, such as a pad, through a metal wire 132.

[0032] Figure 6 3D schematic diagram of the base island interconnection structure according to another embodiment of the present invention. Figure 5 The structure shown is similar, for example, it includes a first wiring substrate 3d, the first wiring substrate 3d includes two first areas 311d and second areas 312d separated by an insulating area, the first chip 11 and the second chip 12 are mounted on the first area 311d, and the third chip 13 is mounted on the first base island 1. The interconnection structure of this embodiment also includes a second wiring substrate 4 and a third base island 5a, the second wiring substrate 4 is connected between the first base island 1 and the third base island 5a, the second wiring substrate 4 includes one or more non-metallic wire conductive circuits (not shown in the figure), the third chip 13 is electrically connected to the non-metallic wire conductive circuits on the second wiring substrate 4 through metal wires, such as a lead group 134, and the non-metallic wire conductive circuits of the second wiring substrate 4 extend to the third base island 5a. The electrical connection relationship between the second wiring substrate 4 and the third base island 5a is similar to Figures 2A-2C The connection relationship shown in is the same as that shown in , and will not be repeated here.

[0033] Figure 7: is a schematic diagram of a base island interconnection structure according to another embodiment of the present invention. In this embodiment, the base island interconnection structure further includes a third base island 5b, and the first wiring substrate 3c is connected between the first base island 1 and the third base island 5b, and the third base island 5b is isolated from the first base island 1 and the second base island 2. The first wiring substrate 3c includes a first region 311c, a second region 312c and a third region 313c that are electrically isolated from each other. The first region 311c, the second region 312c and the third region 313c constitute a non-metallic wire conductive circuit. Among them, the third region 313c is electrically connected to the third base island 5b, and the third chip 13 located on the first base island 1 is electrically connected to the third region 313c of the non-metallic wire conductive circuit of the first wiring substrate 3c through a metal wire 133. Since the third region 313c is electrically connected to the third base island 5b, when the third chip 13 needs to be connected to the circuit on the third base island 5b, it is not necessary to connect it to the third base island 5b with a long lead. Instead, it is only connected to the third region 313c on the first wiring substrate 3c on the same base island through a short lead, and then connected to the third base island 5b via the first wiring substrate 3c, thereby shortening the lead length and reducing parasitic inductance.

[0034] In addition, when the space between multiple wiring substrates is large, in order to increase the support of the wiring substrates, insulating reinforcing ribs can be added between the two wiring substrates, or multiple wiring substrates can be integrated into one, and based on the needs of electrical connection, insulated conductive areas can be covered on the wiring substrate as non-metallic conductive lines. Since the chip is located on the wiring substrate, and the wiring substrate connects the two base islands, the position of the chip and the base island can be that the chip is located on the base island or beyond the base island, such as Figure 6 The second chip 12 shown on the first wiring substrate 3d exceeds the first base island 1. Therefore, it can be seen that the chip interconnection structure provided by the present invention improves the flexibility of the relative position of the chip and the base island.

[0035] It can be seen from the above embodiments that the aforementioned base island interconnection structure can also be applied to the interconnection structure of the chip. The interconnection structure changes the wire bonding method and structure, and changes the traditional wire bonding method from the chip to the base island to a method combining wire bonding with a wiring substrate, thereby reducing the lead length when the chip is electrically connected to the base island, thereby reducing the parasitic inductance and the packaging resistance caused by the lead.

[0036] On the other hand, the present invention also provides an electronic device, which adopts the aforementioned base island / chip interconnection structure and wire bonding structure during packaging, thereby reducing the influence of parasitic inductance on device performance. In an application embodiment, for the packaging structure of a power device, different electrodes in the power device need to be interconnected. Figure 8As an embodiment of a conventional packaging structure, the source of the first chip 11 needs to be connected to the source on the second base island 2, and the drain of the third chip 13 needs to be connected to the drain on the third base island 5a. The connection structure is as follows: Figure 8 As shown, the drain of the third chip 13 is connected to the drain on the third base island 5a through the lead set 134', and the source of the first chip 11 is connected to the source of the second base island 2 through the second lead 112'. Figure 6 The base island interconnection and bonding wire structure shown can be applied to the packaging of power devices. The source of the third chip 13 is connected to the source on the third base island 5a through the second wiring substrate 4. The first wiring substrate 3d includes a first area 311d and a second area 312d isolated by an insulating area. The first chip 11 is electrically connected to the first area 311d. The drain of the first chip 11 is electrically connected to the second area 312d on the first wiring substrate 3d through the second lead 112, and the second area 312d is connected to the drain on the second base island 2. Figure 6 The total length of the lead group 134 is reduced from 28 mm in the traditional packaging structure to 7 mm, and the second lead 112 is reduced from 3.5 mm in the traditional packaging structure to 1 mm.

[0037] Simplify the lead wire into a cylindrical straight wire. For a single cylindrical straight wire with a length of l and a radius of r, its local inductance L p It can be expressed by formula 1-1:

[0038]

[0039] Where μ0 is the magnetic permeability of vacuum.

[0040] Through calculation and comparison using the above formula, the parasitic inductance generated by the lead group 134 is reduced by about 80%, and the parasitic inductance generated by the second lead 112 is reduced by about 78.9%. Theoretically, the parasitic inductance is greatly reduced.

[0041] For some traditional power devices, such as the DFN8×8 structure, the parasitic inductance therein is mainly generated by the long bonding wires, and the wire bonding structure provided by the present invention effectively reduces the parasitic inductance generated during the packaging process. Therefore, the power device packaged using the wire bonding structure and base island interconnection structure provided by the present invention can significantly increase the switching speed of the power device, thereby effectively increasing the switching frequency of the power device.

[0042] Taking the cascode structure as an example, the cascode structure is composed of a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, referred to as MOSFET) and a high electron mobility transistor (High Electron Mobility Transistor, referred to as HEMT), which can be used Figure 6 The chip interconnection structure in. Among them, the first chip 11 is a MOSFET, the source (Source pole) and the gate (Gate pole) are arranged on the front of the chip, and the drain (Drain pole) is arranged on the back of the chip. The third chip 13 is a HEMT, and its Source pole, Gate pole and Drain pole are all arranged on the front. The second chip 12 is a capacitor, and electrodes are arranged on the front and back. Since the typical feature of the cascode structure is the high switching frequency, for example, up to tens of MHz, the relatively large parasitic inductance will affect the voltage oscillation on the gate, increase the switching loss, and reduce the switching frequency, and the chip interconnection structure provided by the present invention effectively reduces the influence of the parasitic inductance, so that the cascode structure using the interconnection structure of the present invention has low switching loss and good performance.

[0043] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. A base island interconnection structure, comprising: A first base island including a first chip; a second base island spaced apart from the first base island; as well as A first wiring substrate connected between the first base island and the second base island, the first wiring substrate comprising a non-metallic conductive line; wherein the first chip is electrically connected to the non-metallic conductive line on the first wiring substrate, and the non-metallic conductive line extends to the second base island; The front surface of the first wiring substrate is covered with a conductive metal layer, the conductive metal layer is used as a non-metallic conductive circuit alone, a through hole is provided on the first wiring substrate, the conductive metal layer extends from the front surface to the side wall of the through hole, the through hole is opposite to the conductive area on the second base island, and the first wiring substrate is electrically connected to the second base island; Some pins of the first chip are electrically connected to pads on the first base island through first leads, and another pin of the first chip is electrically connected to a non-metallic conductive line on the front side of the first wiring substrate through a second lead; The island interconnect structure further includes a second chip. The first chip and the second chip are both arranged on the first wiring substrate. The first chip and the second chip are connected via the non-metallic conductive line.

2. The base island interconnect structure according to claim 1, wherein the first wiring substrate comprises an electrically isolated first area and a second area, the first chip is located on the first area of ​​the first wiring substrate, the first chip is electrically connected to the non-metallic wire conductive line in the first area of ​​the first wiring substrate through a non-metallic wire, and is electrically connected to the non-metallic wire conductive line in the second area of ​​the first wiring substrate through a metal wire, and the second area extends to the second base island. 3 . The island interconnect structure according to claim 2 , wherein the first chip is electrically connected to the circuit of the first island through metal wires.

4. The base island interconnection structure according to claim 2, wherein the second chip is located on the first area of ​​the first wiring substrate, the second chip is electrically connected to the non-metallic wire conductive line in the first area of ​​the first wiring substrate through a non-metallic wire, and the second chip is electrically connected to the circuit of the first base island through a metal wire. The island interconnect structure according to claim 4 , wherein the second chip at least partially extends beyond the first island.

6. The base island interconnect structure according to claim 2 further comprises a third chip, wherein the third chip is located outside the first wiring substrate, the third chip is electrically connected to the non-metallic wire conductive line of the first area of ​​the first wiring substrate through metal wires, and the third chip is electrically connected to the circuit of the first base island through metal wires.

7. The base island interconnection structure according to claim 6 further comprises a second wiring substrate and a third base island, which are connected between the first base island and the third base island, the second wiring substrate comprises one or more non-metallic wire conductive circuits, the third chip is electrically connected to the non-metallic wire conductive circuits of the second wiring substrate through metal wires, and the non-metallic wire conductive circuits of the second wiring substrate extend to the third base island. 8 . The island-base interconnect structure according to claim 1 , wherein the one or more non-metallic conductive lines of the first wiring substrate are connected to the electrical connection portion of the second island-base by a non-metallic wire method. 9 . The island-base interconnect structure according to claim 7 , wherein the one or more non-metallic conductive lines of the second wiring substrate are connected to the electrical connection portion of the third island-base by non-metallic wire means.

10. The base island interconnect structure according to claim 6 further comprises a third base island, the first wiring substrate is connected between the first base island and the third base island, the non-metallic wire conductive circuit of the first wiring substrate comprises a third region electrically isolated from the first region and the second region, the third region extends from the first base island to the third base island, and the third chip is electrically connected to the third region of the non-metallic wire conductive circuit of the first wiring substrate through a metal wire. 11 . The island interconnect structure according to claim 7 , wherein the first wiring substrate and / or the second wiring substrate is a double-sided wiring substrate.

12. A wire bonding structure, comprising: First Base Island; a second base island spaced apart from the first base island and comprising a frame electrode; as well as A first wiring substrate connected between the first base island and the second base island, the first wiring substrate comprising a non-metallic conductive line including a first region extending from the vicinity of the first base island to the second base island; Wherein, the first wiring substrate includes a first chip, Some pins of the first chip are electrically connected to pads on the first base island through first leads, another pin of the first chip is electrically connected to a first region on the first wiring substrate through a second lead, and the first region is electrically connected to pads on the second base island; The front surface of the first wiring substrate is covered with a conductive metal layer, the conductive metal layer is used as a non-metallic conductive circuit alone, a through hole is provided on the first wiring substrate, the conductive metal layer extends from the front surface to the side wall of the through hole, the through hole is opposite to the conductive area on the second base island, and the first wiring substrate is electrically connected to the second base island; The wire bonding structure further includes a second chip. The first chip and the second chip are both arranged on the first wiring substrate. The first chip and the second chip are connected via the non-metallic conductive line. 13 . The wire bonding structure according to claim 12 , wherein the first wiring substrate further comprises a second region electrically isolated from the first region, wherein the second region is at least partially disposed on the first base island, and the second region comprises one or more chips.

14. A chip interconnection structure, comprising: First Base Island; a second base island spaced apart from the first base island and comprising a frame electrode; as well as A first wiring substrate, which is connected between the first base island and the second base island, the first wiring substrate includes a non-metallic wire conductive circuit, which includes a first area and a second area, the second area is at least partially arranged on the first base island, the second area includes a first chip and a second chip, the back electrodes of the first chip and the second chip are electrically connected through the non-metallic wire conductive circuit in the second area, and the front electrodes of the first chip and the second chip are electrically connected through metal wires; wherein the first area extends from the vicinity of the first base island to the second base island; Some pins of the first chip are electrically connected to pads on the first base island through first leads, some pins of the first chip are electrically connected to a first area on the first wiring substrate through second leads, and the first area is electrically connected to pads on the second base island; The front side of the first wiring substrate is covered with a conductive metal layer, and the conductive metal layer serves as a non-metallic conductive circuit alone. A through hole is provided on the first wiring substrate, and the conductive metal layer extends from the front surface to the side wall of the through hole. The through hole is opposite to the conductive area on the second base island, and the first wiring substrate is electrically connected to the second base island. 15 . The chip interconnection structure according to claim 14 , further comprising a third chip on the first base island, wherein the third chip is electrically connected to the second region of the non-metal line conductive circuit of the first wiring substrate through a metal line.

16. The chip interconnection structure according to claim 15 further comprises a second wiring substrate and a third base island, wherein the second wiring substrate is connected between the first base island and the third base island, the second wiring substrate comprises one or more non-metallic wire conductive circuits, the third chip is electrically connected to the non-metallic wire conductive circuits of the second wiring substrate through metal wires, and the non-metallic wire conductive circuits of the second wiring substrate extend to the third base island.

17. The chip interconnection structure according to claim 15 further comprises a third base island, the first wiring substrate is connected between the first base island and the third base island, the non-metallic wire conductive circuit of the first wiring substrate comprises a third region electrically isolated from the first region and the second region, the third region extends from the first base island to the third base island, and the third chip is electrically connected to the third region of the non-metallic wire conductive circuit of the first wiring substrate through metal wires.

18. An electronic device comprising: The island interconnection structure as described in any one of claims 1-11, or the wire bonding structure as described in claim 12 or 13, or the chip interconnection structure as described in any one of claims 14-17.

Images