An N-face HEMT high-frequency device using a side gate structure and a preparation method thereof

Abstract

The application discloses an N-face HEMT high-frequency device using a side gate structure and a preparation method thereof. + The GaN epitaxial layer, the source, the drain, the metal interconnection layer, the gate, the gate bridge and the gate dielectric layer, the epitaxial substrate comprises a substrate, a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer and a GaN cap layer from bottom to top, the n + The GaN epitaxial layer comprises a first n + The GaN epitaxial layer and a second n + The GaN epitaxial layer, the source and the drain are respectively located in the first n + The GaN epitaxial layer and a second n + The upper surface of the GaN epitaxial layer, a plurality of side gates in the gate are arranged at intervals in the first n + The GaN epitaxial layer and a second n + The GaN epitaxial layer and a second n The gate bridge is on the upper surface of the gate, the metal interconnection layer is on the upper surfaces of the source, the drain and the gate, and the gate dielectric layer covers the upper surface of the device below the periphery of the metal interconnection layer. The application can improve the problem of serious radio frequency dissipation in the N-face HEMT device and reduce the influence of the parasitic channel on the channel switch of the channel layer.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, specifically to an N-plane HEMT high-frequency device using a side-gate structure and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) third-generation semiconductor materials typically have a wurtzite structure. This structure results in strong polarization along the c-axis, which is crucial in high-electron-mobility transistors (HEMTs). HEMTs constructed primarily from second-generation semiconductor materials such as gallium arsenide (GaAs) and indium phosphide (InP) exhibit a modulation-doped structure. These HEMTs are widely used in ultra-high frequency and even terahertz fields due to the high mobility of materials like GaAs and InP. In contrast, HEMTs made from gallium nitride, even without doping, can generate polarization charges through the material's strong spontaneous and piezoelectric polarization, attracting electrons (or holes) into the potential well to form a two-dimensional electron (hole) gas. These HEMTs, due to the large bandgap of gallium nitride, excel in high-frequency, high-power applications.

[0003] Gallium nitride (GaN) electronic devices are mainly categorized into two types based on different application scenarios: high-frequency devices and power devices. High-frequency devices are primarily used in applications such as 5G base stations and radar communications, while power devices are typically used in automotive electronics and high-power fast charging. For high-frequency devices, miniaturization means lower latency and faster response times, making miniaturization crucial. To maintain DC characteristics during miniaturization, the current mainstream approach is to replace the barrier material with a material with higher polarization intensity, such as InAlN, ScAlN, and AlN. These materials can reduce the thickness of the barrier layer while maintaining the same level of two-dimensional electron gas density, thereby maintaining a high aspect ratio and avoiding severe short-channel effects during device miniaturization. However, another feasible path to promote device miniaturization is to use N-faceted materials for device design. This approach has received less attention because of the greater difficulty in material growth. Currently, only UCSB in the United States has mature N-faceted material growth technology. In recent years, scholars both domestically and internationally have published a number of achievements, realizing high-quality growth of N-faceted materials. For example, in September 2022, Osaka University successfully developed low-cost N-polar GaN technology. These efforts will usher in a new era for the design of N-faceted gallium nitride (HEMT) devices.

[0004] However, N-plane gallium nitride (GaN) HEMTs also present design challenges. Among these, severe gate leakage and RF dissipation caused by donor-like traps near the negatively polarized interface (NPI) are critical issues that require careful consideration. The severe gate leakage is caused by two main factors: firstly, the presence of numerous hexagonal defect states in the grown N-plane material, which create leakage channels and worsen the leakage current; secondly, in N-plane HEMT systems, the gate metal contacts a GaN channel layer with a narrower bandgap and lower barrier height. The lower barrier height allows electrons to more easily cross the barrier, and the narrower bandgap means a lower breakdown field strength. Consequently, strong impact ionization occurs in the GaN channel layer at relatively low voltages, leading to premature breakdown. Both factors necessitate improvements to the gate structure of N-plane HEMT devices. Employing cap-layer structures and MIS structures are mainstream methods for improving gate leakage, but since electrons at the composite cap-layer interface do not participate in conduction, channel electrons are wasted. The structure of the composite cap layer interface results in some differences in the control of electrons in the two layers of the gate. The parasitic electron channels in the composite cap layer affect the opening of electron channels in the channel layer, thus restricting the switching characteristics of the device. In addition, radio frequency dissipation is also a significant issue for high-frequency devices. In N-plane HEMT devices, the donor-like traps near NPI are relatively close to the Fermi level, resulting in electron charging and discharging under different voltage stresses, thus exhibiting current output hysteresis. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an N-plane HEMT high-frequency device using a side-gate structure and its fabrication method.

[0006] In a first aspect of the invention, an N-plane HEMT high-frequency device using a side-gate structure is provided, comprising an epitaxial substrate, an n-plane HEMT, and an n-plane HEMT. + The GaN epitaxial layer, source, drain and metal interconnect layer, gate, gate bridge and gate dielectric layer, wherein...

[0007] The epitaxial substrate includes, from bottom to top, a substrate, a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer, and a GaN cap layer. Steps (14) are formed around the perimeter of the epitaxial substrate to isolate it from other devices. + The GaN epitaxial layer includes a first n + GaN epitaxial layer and second n + GaN epitaxial layer, the first n + GaN epitaxial layer and the second n +The GaN epitaxial layers are symmetrically distributed on both sides of the interior of the epitaxial substrate, and the source is located at the first n + The drain is located on the upper surface of the GaN epitaxial layer, in the second nth position. + The upper surface of the GaN epitaxial layer, the first n + GaN epitaxial layer and the second n + A gate groove is formed near the center between the GaN epitaxial layers. The metal interconnect layer includes a first metal interconnect layer, a second metal interconnect layer and a third metal interconnect layer. The first metal interconnect layer is located on the upper surface of the source, and the second metal interconnect layer is located on the upper surface of the drain.

[0008] The gate dielectric layer covers the outer surface of the epitaxial substrate and the interior of the gate recess, the n + The GaN epitaxial layer, the source, and the drain are covered inside the gate dielectric layer, and the upper surface of the metal interconnect layer is exposed outside the gate dielectric layer.

[0009] The gate includes a plurality of side gates, which are spaced apart on the upper surface of the gate dielectric layer in the gate recess. The gate bridge is formed on the upper surface of the plurality of side gates, and the third metal interconnect layer is located on the upper surface of one end of the gate bridge.

[0010] In one embodiment of the invention, the gate bridge connects the plurality of side gates.

[0011] In one embodiment of the present invention, the upper surface of the gate is higher than the upper surface of the gate dielectric layer above the GaN cap layer.

[0012] In one embodiment of the invention, each side gate is cylindrical.

[0013] In one embodiment of the invention, the spacing between the plurality of side gates is the same.

[0014] In one embodiment of the present invention, the bottom of the gate recess is located below the upper surface of the GaN buffer layer.

[0015] In one embodiment of the present invention, the n + The lower surface of the GaN epitaxial layer is located inside the GaN buffer layer, and the n + The upper surface of the GaN epitaxial layer is higher than the upper surface of the GaN cap layer.

[0016] In one embodiment of the present invention, the platform of the step (14) is located below the upper surface of the GaN buffer layer.

[0017] In a second aspect, the present invention provides a method for fabricating an N-plane HEMT high-frequency device using a side-gate structure, the method comprising the following steps:

[0018] Step 1: Obtain an epitaxial substrate, which includes, from bottom to top, a substrate, a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer, and a GaN cap layer.

[0019] Step 2: Etch an epitaxial layer trench above the epitaxial substrate down to the GaN buffer layer to form an epitaxial layer trench. The epitaxial layer trenches are symmetrically distributed on both sides of the inner edge of the device. Epitaxial layers are then formed inside and outside the epitaxial layer trenches. + GaN, forming n + GaN epitaxial layer;

[0020] Step 3, in the n + The source and drain electrodes are formed on the upper surface of the GaN epitaxial layer;

[0021] Step 4: Etch the outer perimeter of the device to form a step at the outer edge of the device to form a mesa isolation, wherein the mesa of the step is located below the upper surface of the GaN buffer layer;

[0022] Step 5: Etch the GaN cap layer between the source and the drain downwards into the GaN buffer layer to form a gate trench;

[0023] Step 6: Grow a gate dielectric layer on the upper surface of the device;

[0024] Step 7: Apply PMMA adhesive to the gate dielectric layer on the upper surface of the device, apply PMMA-MAA adhesive on the PMMA adhesive, expose a preset side gate region above the PMMA-MAA adhesive, then expose a preset gate bridge region above the PMMA-MAA adhesive, and develop in all exposed areas. Perform metal evaporation in the preset side gate region to form a gate, the gate including a plurality of cylindrical side gates spaced apart in the gate groove. Perform metal evaporation in the preset gate bridge region to form a gate bridge, the gate bridge being disposed on the upper surface of the gate and connecting the plurality of side gates.

[0025] Step 8: Etch the gate dielectric layer at a preset position on the upper surface of the source and the drain to form a metal interconnect opening region, and use an electron beam evaporation process to evaporate metal in the metal interconnect opening region and at one end of the upper surface of the gate bridge to form a metal interconnect layer.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] 1. The N-plane HEMT high-frequency device with a side-gate structure provided by this invention employs a composite cap structure of AlGaN and GaN cap layers, which can improve the transconductance of the device. This composite cap structure has a large thickness, which can reduce the surface scattering effect on channel electrons and improve the device mobility. In addition, in addition to the electron gas formed between the AlGaN barrier layer and the GaN channel layer, a high concentration of electrons is also formed at the contact interface between the AlGaN cap layer and the GaN cap layer. Under voltage, these electrons are equivalent to channel layer electrons, thus acting as parasitic electron channels. Both electron gas layers participate in conduction, which can further improve the DC characteristics of the device, such as output current and transconductance.

[0028] 2. The N-plane HEMT high-frequency device using a side-gate structure provided by this invention employs a side-gate structure. This structure achieves switching of the HEMT high-frequency device through the depletion effect between adjacent gates. Compared to traditional gate structures, the gate control capability of the side-gate structure is relatively weak. Using a side-gate structure can further reduce the gate's control over electrons in the access region while ensuring the device's switching capability. This reduces the impact of donor-like level charging and discharging near the NPI on the number of conductive electrons, further improving the problem of severe RF dissipation in N-plane HEMT devices. Furthermore, the side-gate structure provides almost identical control over parasitic electron channels and channel layer electron channels. On the one hand, it can improve the influence of parasitic channels on channel layer switching; on the other hand, it can also improve the influence of parasitic channels on HEMT device leakage current.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of an N-plane HEMT high-frequency device using a side-gate structure along the gate length direction provided in an embodiment of the present invention;

[0031] Figure 2 yes Figure 1 A schematic diagram of the structure of an N-plane HEMT high-frequency device using a side-gate structure along the gate width direction;

[0032] Figure 3 yes Figure 1 A schematic diagram of an N-plane HEMT high-frequency device using a side-gate structure, viewed from above.

[0033] Figure 4 This is a schematic diagram of a method for fabricating an N-plane HEMT high-frequency device using a side-gate structure, provided by an embodiment of the present invention.

[0034] Figure 5 This is a schematic diagram of the fabrication process of an N-plane HEMT high-frequency device using a side-gate structure provided in an embodiment of the present invention. Detailed Implementation

[0035] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of an N-plane HEMT high-frequency device using a side-gate structure and its fabrication method based on the present invention.

[0036] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0038] Please see Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic diagram along the gate length direction of an N-plane HEMT high-frequency device using a side-gate structure, provided by an embodiment of the present invention. Figure 2 yes Figure 1 A schematic diagram of the structure of an N-plane HEMT high-frequency device using a side-gate structure along the gate width direction. Figure 3 yes Figure 1 A schematic diagram of an N-plane HEMT high-frequency device using a side-gate structure, viewed from above. This N-plane HEMT high-frequency device with a side-gate structure includes an epitaxial substrate, n... + GaN epitaxial layer 4, source 8, drain 9, metal interconnect layer 13, gate 10, gate bridge 11, and gate dielectric layer 12.

[0039] Specifically, the epitaxial substrate includes, from bottom to top, a substrate 1, a GaN buffer layer 2, an AlGaN barrier layer 3, a GaN channel layer 5, an AlGaN cap layer 6, and a GaN cap layer 7. The substrate 1 is made of an insulating material selected from sapphire, GaN, Si, or SiC, and has a thickness of 400 μm to 500 μm. The GaN buffer layer 2 has a thickness of 1.3 μm to 2 μm, the AlGaN barrier layer 3 has a thickness of 20 to 30 nm, the GaN channel layer 5 has a thickness of 10 to 20 nm, the AlGaN cap layer 6 has a thickness of 1 to 3 nm, and the GaN cap layer 7 has a thickness of 100 to 130 nm. Steps 14 are formed around the perimeter of the epitaxial substrate to isolate it from other devices on the substrate. Furthermore, the mesa of the steps 14 is located below the upper surface of the GaN buffer layer 2.

[0040] n + GaN epitaxial layer 4 includes the first n + GaN epitaxial layer and second n + GaN epitaxial layer, first n + GaN epitaxial layer and second n + The GaN epitaxial layers are symmetrically distributed on both sides of the inner surface of the epitaxial substrate, n + The lower surface of GaN epitaxial layer 4 is located inside GaN buffer layer 2, n + The top of GaN epitaxial layer 4 is higher than the top of the epitaxial substrate, specifically, n + The upper surface of GaN epitaxial layer 4 is higher than the upper surface of GaN cap layer 7, n + The thickness of GaN epitaxial layer 4 is 120nm to 150nm.

[0041] First n + GaN epitaxial layer and the second n + A gate groove is formed near the center between the GaN epitaxial layers, and the bottom of the gate groove is located below the upper surface of the GaN buffer layer 2.

[0042] Source pole 8 is located in the first n + On the upper surface of the GaN epitaxial layer, drain 9 is located at the second n-th... + The upper surface of the GaN epitaxial layer has a metal interconnect layer 13, which includes a first metal interconnect layer, a second metal interconnect layer and a third metal interconnect layer. The first metal interconnect layer is located on the upper surface of the source electrode 8, the second metal interconnect layer is located on the upper surface of the drain electrode 9, and the third metal interconnect layer is located between the first metal interconnect layer and the second metal interconnect layer.

[0043] Gate dielectric layer 12 covers the outer surface of the epitaxial substrate and the interior of the gate recess, n +The GaN epitaxial layer 4, source 8, and drain 9 are covered inside the gate dielectric layer 12, and the upper surface of the metal interconnect layer 13 is exposed outside the gate dielectric layer 12. Furthermore, the thickness of the gate dielectric layer 12 is 3 to 10 nm.

[0044] The gate 10 includes a plurality of side gates 101, which are spaced apart on the upper surface of the gate dielectric layer 12 in the gate recess. The upper surface of the gate 10 is higher than the upper surface of the gate dielectric layer 12 above the GaN cap layer 7. The spacing between the plurality of side gates 101 is the same, and each side gate is cylindrical. A gate bridge 11 is formed on the upper surface of the plurality of side gates 101, and the gate bridge 11 connects the plurality of side gates 101. That is, the side gates 101 are connected by the gate bridge 11. Furthermore, one end of the gate bridge 11 is located below the third metal interconnect layer, that is, the third metal interconnect layer is located on the upper surface of one end of the gate bridge 11.

[0045] In this embodiment, the substrate 1 is made of insulating sapphire, and the AlGaN barrier layer 3 is made of Al 0.4 Ga 0.6 N, the material of the AlGaN cap layer 6 is Al 0.3 Ga 0.7 N, the material of the gate dielectric layer 12 is SiN, the thickness of the AlGaN barrier layer 3 is 30nm, the thickness of the GaN channel layer 5 is 20nm, the thickness of the AlGaN cap layer 6 is 2nm, the thickness of the GaN cap layer 7 is 100nm, and the thickness of the gate dielectric layer 12 is 5nm.

[0046] The N-plane HEMT high-frequency device with a side-gate structure provided in this embodiment employs a composite cap structure of AlGaN and GaN cap layers to improve the transconductance of the device. This composite cap structure has a relatively large thickness, which reduces surface scattering of channel electrons and improves device mobility. Furthermore, in addition to the electron gas formed between the AlGaN barrier layer 3 and the GaN channel layer 5, a high concentration of electrons is also formed at the interface between the AlGaN and GaN cap layers. Under voltage, these electrons are equivalent to channel layer electrons, thus acting as parasitic electron channels. Both electron gas layers participate in conductivity, further improving the DC characteristics of the device, such as output current and transconductance.

[0047] The N-plane HEMT high-frequency device using a side-gate structure provided in this embodiment achieves switching of the HEMT high-frequency device through the depletion effect between adjacent gates. Compared with the traditional gate structure, the gate control capability of the side-gate structure is relatively weak. Using the side-gate structure can further reduce the gate's control effect on electrons in the access region while ensuring the device's switching capability, thereby reducing the impact of the charging and discharging of the donor-like energy level near the NPI on the number of conductive electrons, and further improving the problem of severe RF dissipation in N-plane HEMT devices. Furthermore, the side-gate structure provides almost identical control over parasitic electron channels and channel layer electron channels. On the one hand, it can improve the influence of parasitic channels on the switching of channel layer channels; on the other hand, it can also improve the influence of parasitic channels on the leakage current of the HEMT device.

[0048] Please see Figure 4 , Figure 4 This is a schematic diagram of a fabrication method for an N-plane HEMT high-frequency device using a side-gate structure, provided by an embodiment of the present invention. The fabrication method specifically includes:

[0049] Step S10: Obtain an epitaxial substrate, which includes a substrate, a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer, and a GaN cap layer arranged sequentially from bottom to top.

[0050] like Figure 5 As shown in (a), obtaining an epitaxial substrate includes preparing an epitaxial substrate or selecting an existing epitaxial substrate. The integrated epitaxial substrate includes a substrate, a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer, and a GaN cap layer arranged sequentially from bottom to top.

[0051] Specifically, the preparation of the epitaxial substrate includes: sequentially growing a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer, and a GaN cap layer on the substrate using a metal-organic chemical vapor deposition (MOCVD) process. In this embodiment, the substrate is a sapphire substrate, and the material of the AlGaN barrier layer is Al 0.4 Ga 0.6 N, with a thickness of 30nm, GaN channel layer thickness of 20nm, and AlGaN cap layer material is Al 0.3 Ga 0.7 N has a thickness of 2nm, and the GaN cap layer has a thickness of 100nm.

[0052] Step S20: Epitaxially grow n on both sides of the GaN buffer layer inside the epitaxial substrate. + GaN, forming n + GaN epitaxial layer;

[0053] like Figure 5 As shown in (b), n are epitaxially grown on both sides inside the GaN buffer layer. + GaN, forming n + GaN epitaxial layer. Further, epitaxial layer grooves are formed by etching above the epitaxial substrate down to the GaN buffer layer, and these grooves are symmetrically distributed on both sides of the inner edge of the device. n epitaxial layers are formed inside and outside the epitaxial layer grooves. + GaN, forming n + GaN epitaxial layer. The specific steps are as follows.

[0054] Step S200: Using plasma-enhanced chemical vapor deposition (PECVD), a SiO2 layer and a SiN layer are sequentially deposited on the GaN cap layer to form a mask layer, specifically including:

[0055] An epitaxial substrate is placed in a PECVD apparatus to grow a 200 nm thick SiO2 layer. In this embodiment, the process conditions for growing the SiO2 layer are: N2O and SiN4 are used as reaction gases, the substrate temperature is 300 °C, the reaction chamber pressure is 600 mTorr, and the RF power is 70 W. Subsequently, a SiN layer is grown on the SiO2 layer using a PECVD apparatus. In this embodiment, the process conditions for growing the SiN layer are: NH3 and SiH4 are used as reaction gases, the substrate temperature is 250 °C, the reaction chamber pressure is 600 mTorr, and the RF power is 22 W.

[0056] Step S201: Perform photolithography on the mask layer, specifically including:

[0057] The epitaxial substrate was baked on a hot plate at 200°C for 5 minutes. Photoresist was then applied and spin-coated onto the mask layer, with a spin-coating thickness of 0.77 μm. The sample was then baked on a hot plate at 90°C for 1 minute. The epitaxial substrate was placed in a photolithography machine to expose the coated surface. After exposure, the epitaxial substrate was immersed in a developing solution to remove the photoresist and stripper. It was then rinsed with ultrapure water and dried with nitrogen. Finally, the preset n... + Photoresist removal was performed on the GaN epitaxial layer region. ICP-based etching equipment was used to etch the pre-defined n... + The SiO2 layer and SiN layer in the GaN epitaxial layer region are etched. After etching, the layers are cleaned with an organic solution and rinsed with ultrapure water, then dried with nitrogen. The preset n... + The GaN epitaxial layer regions are located on both sides of the device's interior. In this embodiment, for the preset n... +The SiO2 and SiN mask in the GaN epitaxial layer region were etched to a depth of 280 nm. An ICP-based etching apparatus was used to etch the material at a preset n... + The GaN cap layer, AlGaN cap layer, GaN channel layer, AlGaN barrier layer, and part of the GaN buffer layer beneath the GaN epitaxial layer are etched. Specifically, grooves are formed on the epitaxial substrate from the GaN cap layer to the interior of the GaN buffer layer, with an etching depth of 140 nm. After etching, the substrate is cleaned with an organic solution and rinsed with ultrapure water, followed by nitrogen drying.

[0058] Step S202: Extend n inside and outside the etched groove + GaN;

[0059] Specifically, molecular beam epitaxy (MBE) equipment is used to epitaxially grow n on the etched grooves. + In this embodiment, the n-layer extends from the GaN layer above the GaN cap layer. + The thickness of GaN is 150nm.

[0060] Step S203: Remove the mask layer and remove the preset n + n outside the GaN epitaxial layer region + GaN.

[0061] Specifically, a buffered oxide etch (BOE) solution is used to remove the SiO2 and SiN layers, while simultaneously removing the preset n... + n outside the GaN epitaxial layer region + GaN, forming n inside the device + GaN epitaxial layer, n + The GaN epitaxial layer includes a first n layer located on both sides inside the device. + GaN epitaxial layer and second n + GaN epitaxial layer.

[0062] Step S30, in n + The source and drain electrodes are formed on the upper surface of the GaN epitaxial layer;

[0063] like Figure 5 As shown in (c), in n + The specific steps for fabricating source and drain electrodes on a GaN epitaxial layer include:

[0064] Step S300, in n + Photolithographically etched source and drain regions on GaN epitaxial layer;

[0065] First, the epitaxial substrate is baked on a hot plate at 200°C for 5 minutes, followed by n +The GaN epitaxial layer and GaN cap layer were coated and spin-spinned with release adhesive to a thickness of 0.35 μm. The sample was then baked on a hot plate at 200°C for 5 minutes. Next, photoresist was coated and spin-spinned on top of the release adhesive to a thickness of 0.77 μm. The entire device was then baked on a hot plate at 90°C for 1 minute. Finally, the coated and spin-spinned device was placed in a photolithography machine for exposure of the coated surface. After exposure, the device was immersed in a developing solution to remove the photoresist and release adhesive from the predetermined source and drain regions. The device was then rinsed with ultrapure water and dried with nitrogen to complete the photolithography of the source and drain regions. The predetermined source and drain regions are located at the first n... + The upper surface of the GaN epitaxial layer and the second n + The upper surface of the GaN epitaxial layer.

[0066] Step S301: Electron beam evaporation is performed on the upper surface of the device to form the source and drain electrodes.

[0067] Specifically, the device is placed in a plasma resist remover for 5 minutes to treat the underlying film. Then, the device is placed in an electron beam evaporation stage until the vacuum level in the reaction chamber reaches 2 × 10⁻⁶. -6 After Torr, ohmic metal is evaporated on the upper surface of the device, namely on the preset source and drain regions and photoresist. The ohmic metal is a metal stack structure composed of two layers of metal, Ti and Au, arranged sequentially from bottom to top. The ohmic metal, photoresist and release adhesive outside the source and drain are removed. The sample is then rinsed with ultrapure water and dried with nitrogen gas to form the source and drain in the preset source and drain regions.

[0068] Step S40: Use an ICP device to perform Cl-based etching to form a mesa isolation.

[0069] like Figure 5 As shown in (d), the outer perimeter of the device is etched to form a step at the outer edge of the device to create a mesa for isolation. The mesa of the step is located below the upper surface of the GaN buffer layer. In this embodiment, an inductively coupled plasma (ICP) device is used to perform Cl-based etching to form the mesa for isolation between devices. The specific steps include:

[0070] Step S400: Photolithographically lithographically print the mesa isolation region on the GaN cap layer 7;

[0071] First, the device is baked on a hot plate at 200°C for 5 minutes. Then, photoresist is applied and spun off at a speed of 3500 r / min. The device is then baked on a hot plate at 90°C for 1 minute. The device is then placed in a lithography machine to expose the photoresist in the passive area, which is the outer edge of the device. After exposure, the sample is placed in a developing solution to remove the photoresist in the passive area. Finally, the sample is rinsed with ultrapure water and dried with nitrogen.

[0072] Step S401: Etch the GaN cap layer to form a mesa isolation.

[0073] The passive region's GaN cap layer, AlGaN cap layer, GaN channel layer, and AlGaN barrier layer are etched away using an ICP device until a portion of the GaN buffer layer is reached. Specifically, the etching proceeds from the GaN cap layer downwards to the GaN buffer layer around the outer edge of the device, creating L-shaped grooves on both sides of the device along the source-to-drain direction. The bottom of these grooves is located inside the GaN buffer layer. After etching, a mesa isolation is formed in the active region. In this embodiment, the etching depth is 160nm to 180nm.

[0074] The sample was sequentially cleaned in acetone solution, stripping solution, acetone solution and isopropanol solution to remove the photoresist outside the electrically isolated area. Finally, the sample was rinsed with ultrapure water and dried with nitrogen.

[0075] Step S50: Etch the GaN cap layer between the source and drain downwards into the GaN buffer layer to form a gate trench;

[0076] like Figure 5 As shown in (e), a gate trench is formed by etching the GaN cap layer between the source and drain electrodes downwards, specifically including:

[0077] Step S500: Photolithographically etch the side gate region on the GaN cap layer;

[0078] Specifically, the sample is baked on a hot plate at 200°C for 5 minutes, and photoresist is applied and spun off at a speed of 4000 r / min. The device is then baked on a hot plate at 150°C for 1 minute. Subsequently, the device is placed in an electron beam lithography machine to expose the photoresist in the preset side gate region. The preset side gate region is located between the source and drain electrodes, and the length of the preset side gate region extends along the width direction of the device. After exposure, the device is placed in a developing solution to remove the photoresist in the preset side gate region, and the device is rinsed with ultrapure water and dried with nitrogen.

[0079] Step S501: Etch the GaN cap layer from top to bottom to form a gate groove structure;

[0080] Using an ICP Cl-based etching apparatus, the GaN cap layer, AlGaN cap layer, GaN channel layer, and AlGaN barrier layer within the preset side gate region are etched down to below the upper surface of the GaN buffer layer. That is, the etching extends from the GaN cap layer to the GaN buffer layer within the preset side gate region, forming a gate trench structure between the source and drain. The etching depth of the gate trench is 130nm to 140nm. The device is then sequentially immersed in acetone solution, stripping solution, acetone solution, and isopropanol solution for cleaning to remove the photoresist outside the side gate region. Finally, the sample is rinsed with ultrapure water and dried with nitrogen gas.

[0081] Step S60: Grow a gate dielectric layer on the upper surface of the device;

[0082] like Figure 5 As shown in (f), the device is placed in a PECVD equipment, and a gate dielectric layer is grown on the upper surface of the device. In this embodiment, the gate dielectric layer is SiN and the thickness of the gate dielectric layer is 5nm. The growth process conditions are as follows: NH3 and SiH4 are used as reaction gases, the substrate temperature is 250°C, the reaction chamber pressure is 600mTorr, and the RF power is 22W.

[0083] Step S70: Photolithographically etch the side gate region and gate bridge region on the gate dielectric layer, and fabricate the side gate and gate bridge using electron beam evaporation process;

[0084] like Figure 5 As shown in (g), PMMA adhesive is coated on the gate dielectric layer on the upper surface of the device, PMMA-MAA adhesive is coated on the PMMA adhesive, a predetermined side gate region is exposed above the PMMA-MAA adhesive, and a predetermined gate bridge region is then exposed above the PMMA-MAA adhesive. Development is performed in all exposed areas, and metal evaporation is performed in the predetermined side gate region to form a gate, which includes a plurality of cylindrical side gates spaced apart in a gate recess. Metal evaporation is performed in the predetermined gate bridge region to form a gate bridge, which is disposed on the upper surface of the gate and connects the plurality of side gates. Specific steps include:

[0085] Step S700: Photolithographically etch the side gate region on the gate dielectric layer;

[0086] The device was baked on a hot plate at 200°C for 5 minutes. PMMA adhesive was applied to the gate dielectric layer and baked at 200°C for 10 minutes. The thickness of the PMMA adhesive was greater than the depth of the groove etched in the side gate region, that is, the upper surface of the PMMA adhesive was located above the upper surface of the GaN cap layer, so that the gate bridge and the gate dielectric layer did not form contact. PMMA-MAA adhesive was then applied immediately on the PMMA and baked at 195°C for 10 minutes. The thickness of the PMMA-MAA adhesive was greater than the thickness of the gate bridge.

[0087] Optionally, a metal layer is deposited on top of the PMMA-MAA resist using magnetron sputtering, evaporation, or other methods. This metal can be one of Al, Ti, or W, with a thickness of 1–6 nm, to release residual charge from electron beam lithography and avoid affecting the exposure pattern. A high-dose exposure is first performed in a preset side gate region, followed by a low-dose exposure. Since PMMA-MAA is highly sensitive, only a low-dose exposure is required, while PMMA is less sensitive and requires a high-dose exposure. Performing a high-dose exposure in the preset side gate region allows simultaneous exposure of the side gate region and the gate bridge above it. Subsequent low-dose exposure ensures that the PMMA resist below the gate bridge is not exposed while the gate bridge region is being exposed, thus preventing contact between the gate bridge and the gate dielectric layer. After exposure, a developer is used to remove the PMMA-MAA resist and PMMA resist from the side gate region, remove the PMMA-MAA resist from the gate bridge region, and remove any metal fragments broken into metal pieces after exposure.

[0088] Step S701: Metal evaporation is performed in the side gate region and the gate bridge region to form the gate and the gate bridge;

[0089] Specifically, the device is placed in a plasma resist remover for 5 minutes to treat the bottom film. Then, the device is placed in an electron beam evaporation stage until the vacuum level in the reaction chamber reaches 2 × 10⁻⁶. -6 Following the Torr process, gate metal is evaporated onto the side gate region, gate bridge region, and the metal layers outside these regions. This gate metal is a metal stack structure consisting of two layers of Ni and Au, arranged sequentially from bottom to top, with Ni having a thickness of 45 nm and Au a thickness of 270 nm. The sample after gate metal evaporation is then stripped to remove the metal layers, PMMA-MAA, and PMMA photoresist outside the side gate region and gate bridge region, and the PMMA photoresist in the gate bridge region is also removed. The sample is rinsed with ultrapure water and dried with nitrogen to form the gate and gate bridge.

[0090] Step S80: Photolithography of the metal interconnect region, and fabrication of the metal interconnect layer in the metal interconnect region using electron beam evaporation process.

[0091] like Figure 5 As shown in (h), a metal interconnect aperture region is formed by etching the gate dielectric layer at predetermined positions on the upper surfaces of the source and drain electrodes. Then, metal is evaporated at one end of the upper surface of the gate bridge and the metal interconnect aperture region using an electron beam evaporation process to form a metal interconnect layer. Specifically, this includes:

[0092] Step S800: Photolithography of metal interconnect regions;

[0093] Specifically, the device is baked on a hot plate at 200°C for 5 minutes. Then, release adhesive is applied and spun onto the gate dielectric layer and gate bridges, with a spun-off thickness of 0.35 μm. The device is then baked on a hot plate at 200°C for 5 minutes. Next, photoresist is applied and spun onto the release adhesive, with a spun-off thickness of 0.77 μm. Finally, the device is baked on a hot plate at 90°C for 1 minute. The device is then placed in a photolithography machine to expose the photoresist in the metal interconnect area. After exposure, the device is immersed in a developing solution to remove the photoresist in the metal interconnect area and perform the release process. The adhesive is then rinsed with ultrapure water and dried with nitrogen. The metal interconnect region is a pre-defined area of ​​the metal interconnect layer, which includes a first metal interconnect aperture region, a second metal interconnect aperture region, and a gate bridge metal interconnect region. The first metal interconnect aperture region is located near the center of the gate dielectric layer on the upper surface of the source electrode, the second metal interconnect aperture region is located near the center of the gate dielectric layer on the upper surface of the drain electrode, and the gate bridge metal interconnect region is located on the upper surface of the gate bridge, between the first metal interconnect aperture region and the second metal interconnect aperture region.

[0094] Step S801: Evaporate metal in the metal interconnect region to form a metal interconnect layer.

[0095] First, the gate dielectric layer is etched in the first and second metal interconnect via regions. Specifically, the gate dielectric layer in the first and second metal interconnect via regions is removed using an ICP-based etching process. The etching conditions are: the reaction gases are CF4 and O2, the reaction chamber pressure is 10 m Torr, the RF power of the upper and lower electrodes is 100 W and 10 W respectively, and the etching depth is 10–20 nm, etching to the upper surfaces of the source and drain electrodes. Then, metal is evaporated from the surface of the metal interconnect regions. Specifically, the device is placed in a plasma resist remover for 5 minutes for bottom film treatment, and then placed in an electron beam evaporation stage until the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2 × 10⁻⁶. -6 After Torr, metal is evaporated in the pre-defined metal interconnect region and on the photoresist outside the metal interconnect region. The device after metal evaporation is stripped to remove the metal, photoresist and release adhesive outside the metal interconnect region. The sample is then rinsed with ultrapure water and dried with nitrogen to complete the device fabrication to form a metal interconnect layer in the metal interconnect region. This metal interconnect layer is a metal stack structure consisting of two layers, Ti and Au, arranged from bottom to top to bring out the source, drain and gate electrodes.

[0096] The fabrication method provided in this embodiment produces an N-plane HEMT high-frequency device using a side-gate structure. This HEMT high-frequency device employs a side-gate structure, which achieves switching conversion through the depletion effect between adjacent gates. Compared to traditional gate structures, the gate control capability of the side-gate structure is relatively weaker. Using a side-gate structure can further reduce the gate's control over electrons in the access region while ensuring the device's switching capability, thereby reducing the impact of donor-like level charging and discharging near the NPI on the number of conductive electrons and further improving the problem of severe RF dissipation in N-plane HEMT devices. Furthermore, the side-gate structure provides almost identical control over parasitic electron channels and channel layer electron channels. On the one hand, it can improve the influence of parasitic channels on channel layer switching; on the other hand, it can also improve the influence of parasitic channels on HEMT device leakage current.

[0097] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made to alter the shape and area of ​​the side gates without departing from the concept of the present invention, and all such modifications or substitutions should be considered within the scope of protection of the present invention.

Claims

1. An N-plane HEMT high-frequency device using a side-gate structure, characterized in that, include: epitaxial substrate, n + GaN epitaxial layer (4), source electrode (8), drain electrode (9) and metal interconnection layer (13), gate electrode (10), gate bridge (11) and gate dielectric layer (12), wherein, The epitaxial substrate comprises, from bottom to top, a substrate (1), a GaN buffer layer (2), an AlGaN barrier layer (3), a GaN channel layer (5), an AlGaN cap layer (6) and a GaN cap layer (7), the four peripheral edges of the epitaxial substrate form steps (14) to form isolation with other devices, the n + The GaN epitaxial layer (4) comprises a first n + The GaN epitaxial layer and a second n + The GaN epitaxial layer, the first n + The GaN epitaxial layer and the second n + The GaN epitaxial layers are symmetrically distributed on both sides of the inside of the epitaxial substrate, the source (8) is located on the upper surface of the first n + The GaN epitaxial layer, and the drain (9) is located on the upper surface of the second n + The GaN epitaxial layer, the first n + The GaN epitaxial layer and the second n + A gate recess is formed near the center between the GaN epitaxial layers, the metal interconnection layer (13) comprises a first metal interconnection layer, a second metal interconnection layer and a third metal interconnection layer, the first metal interconnection layer is located on the upper surface of the source (8), and the second metal interconnection layer is located on the upper surface of the drain (9). The gate dielectric layer (12) covers the outer surface of the epitaxial substrate and the interior of the gate recess, the n + The GaN epitaxial layer (4), the source (8) and the drain (9) are covered inside the gate dielectric layer (12), and the upper surface of the metal interconnect layer (13) is exposed outside the gate dielectric layer (12). The gate (10) includes a plurality of side gates (101), which are spaced apart on the upper surface of the gate dielectric layer (12) in the gate recess. The gate bridge (11) is formed on the upper surface of the plurality of side gates (101), and the third metal interconnect layer is located on the upper surface of one end of the gate bridge (11). The gate bridge (11) connects the plurality of side gates; the thickness of the AlGaN cap layer (6) is 1~3nm, and the thickness of the GaN cap layer (7) is 100~130nm.

2. The N-plane HEMT high-frequency device using a side-gate structure according to claim 1, characterized in that, The upper surface of the gate (10) is higher than the upper surface of the gate dielectric layer (12) above the GaN cap layer (7).

3. The N-plane HEMT high-frequency device using a side-gate structure according to claim 1, characterized in that, Each side gate (101) is cylindrical.

4. The N-plane HEMT high-frequency device using a side-gate structure as described in claim 1, characterized in that, The spacing between the plurality of side gates (101) is the same.

5. The N-plane HEMT high-frequency device using a side-gate structure according to claim 1, characterized in that, The bottom of the gate groove is located below the upper surface of the GaN buffer layer (2).

6. The N-plane HEMT high-frequency device using a side-gate structure according to claim 1, characterized in that, The n + The lower surface of the GaN epitaxial layer (4) is located inside the GaN buffer layer (2), and the n + The upper surface of the GaN epitaxial layer (4) is higher than the upper surface of the GaN cap layer (7).

7. The N-plane HEMT high-frequency device using a side-gate structure according to claim 1, characterized in that, The platform of the step (14) is located below the upper surface of the GaN buffer layer (2).

8. A method for fabricating an N-plane HEMT high-frequency device using a side-gate structure, characterized in that, The method for fabricating the N-plane HEMT high-frequency device according to any one of claims 1-7 comprises the following steps: Step 1: Obtain an epitaxial substrate, which includes, from bottom to top, a substrate, a GaN buffer layer, an AlGaN barrier layer, a GaN channel layer, an AlGaN cap layer, and a GaN cap layer. Step 2: Etch an epitaxial layer trench above the epitaxial substrate down to the GaN buffer layer to form an epitaxial layer trench. The epitaxial layer trenches are symmetrically distributed on both sides of the inner edge of the device. Epitaxial layers are then formed inside and outside the epitaxial layer trenches. + GaN, forming n + GaN epitaxial layer; Step 3, in the n + The source and drain electrodes are formed on the upper surface of the GaN epitaxial layer; Step 4: Etch the outer perimeter of the device to form a step at the outer edge of the device to form a mesa isolation, wherein the mesa of the step is located below the upper surface of the GaN buffer layer; Step 5: Etch the GaN cap layer between the source and the drain downwards into the GaN buffer layer to form a gate trench; Step 6: Grow a gate dielectric layer on the upper surface of the device; Step 7: Apply PMMA adhesive to the gate dielectric layer on the upper surface of the device, apply PMMA-MAA adhesive on the PMMA adhesive, expose a preset side gate region above the PMMA-MAA adhesive, then expose a preset gate bridge region above the PMMA-MAA adhesive, and develop in all exposed areas. Perform metal evaporation in the preset side gate region to form a gate, the gate including a plurality of cylindrical side gates spaced apart in the gate groove. Perform metal evaporation in the preset gate bridge region to form a gate bridge, the gate bridge being disposed on the upper surface of the gate and connecting the plurality of side gates. Step 8: Etch the gate dielectric layer at a preset position on the upper surface of the source and the drain to form a metal interconnect opening region, and use an electron beam evaporation process to evaporate metal in the metal interconnect opening region and at one end of the upper surface of the gate bridge to form a metal interconnect layer.

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