A metal oxide thin film transistor and a method of manufacturing the same

Abstract

The application provides a metal oxide thin film transistor and a preparation method thereof. The metal oxide thin film transistor is provided with a channel protection layer and a sacrifice layer in sequence on an active layer. The sacrifice layer is any one or a combination of at least two of amorphous oxide thin film, nitride thin film, oxynitride thin film, fluoride thin film or sulfide thin film. In the preparation method, the active layer, the channel protection layer and the sacrifice layer can be continuously deposited, and one etching patterning can be realized. The method is simple in operation, low in preparation cost, realizes preparation of a short channel device, and has large-scale industrialized application prospect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a metal oxide thin film transistor and a preparation method thereof. BACKGROUND

[0002] In recent years, the new display industry is developing rapidly, and the high demand for large size and high resolution display is increasing. As the core technology of the display industry, the thin film transistor (TFT) backplane technology is also undergoing profound changes.

[0003] Metal oxide (MO) TFT technology is considered to be the most potential device in the next generation of display technology because it combines the advantages of polycrystalline silicon TFT and amorphous silicon TFT. Especially in the preparation of TFT panel, the preparation process of metal oxide TFT is compatible with the existing amorphous silicon TFT production process because of the similar device structure and low-temperature preparation, that is, the back channel etching (BCE) process with simple process and low cost can be used. However, the chemical stability of metal oxide film is relatively poor, and it is easily affected by water, oxygen, plasma, etc. As an active layer material, it is easily affected by etching liquid, process flow, etc. Especially in the process of etching the source and drain electrodes, the metal oxide channel layer is directly exposed to the etching liquid, resulting in poor uniformity and reliability of the prepared device.

[0004] In addition, since the source and drain electrode metal layer is directly deposited on the active layer to form an interface layer, the metal atoms "diffuse" or "inject" into the active layer during the etching process of the source and drain electrode, which cannot be cleaned completely, resulting in a negative threshold voltage and poor device uniformity, and affecting the reliability of the device.

[0005] When using an etching liquid that can etch the active layer to etch the source and drain electrode, although the metal atoms in the active layer are cleaned completely, the active layer is also severely damaged, which also causes degradation of device uniformity and reliability. SUMMARY

[0006] In view of the problems in the prior art, the present application provides a metal oxide thin film transistor and a preparation method thereof, by additionally arranging a channel protection layer and a sacrificial layer on the active layer, effectively preventing the "diffusion" or "injection" of metal atoms from the source electrode and the drain electrode to the active layer during sputtering, and the sacrificial layer can be completely etched clean in the etching or other subsequent processes of the source electrode and the drain electrode, without affecting the overall performance of the device; the preparation method has simple process and strong compatibility, the prepared device has significantly improved uniformity and stability, and a short channel device with excellent performance can be prepared.

[0007] To achieve this purpose, the present application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a metal oxide thin film transistor, wherein a channel protection layer and a sacrificial layer are sequentially arranged on the active layer of the metal oxide thin film transistor; the sacrificial layer is any one or a combination of at least two of amorphous oxide thin film, nitride thin film, oxynitride thin film, fluoride thin film or sulfide thin film.

[0009] The metal oxide thin film transistor of the present application additionally arranges a channel protection layer and a sacrificial layer on the active layer, the sacrificial layer can effectively prevent the "diffusion" or "injection" of metal atoms from the source electrode and the drain electrode to the active layer during sputtering, and then be completely etched clean in the etching or other subsequent processes of the source electrode and the drain electrode, thereby avoiding the influence of metal atoms on the device; the channel protection layer can effectively resist the influence of the etching liquid of the sacrificial layer and the etching liquid of the source and drain electrodes. The sacrificial layer of the present application is any one or a combination of at least two of amorphous oxide thin film, nitride thin film, oxynitride thin film, fluoride thin film or sulfide thin film, which is easy to be etched and removed, and the oxide thin film, nitride thin film, oxynitride thin film, fluoride thin film or sulfide thin film can be prepared by magnetron sputtering, chemical vapor deposition or solution method, and the manufacturing process is simple, diverse and compatible. Key, the active layer of the metal oxide thin film transistor of the present application is not affected by the deposition of the source and drain electrodes, and is not eroded by the etching liquid, and can maintain its intrinsic characteristics. Therefore, the present application can effectively improve the poor uniformity of large-area devices, and greatly improve the stability of the devices. In addition, the channel protection layer film of the present application has high oxygen binding energy and stable chemical properties, can effectively resist the influence of hydrogen ions and related plasma elements in the subsequent passivation layer deposition process, can effectively inhibit the formation of high carrier concentration area, thereby avoiding the shortening of the effective channel length, and solving the problem of short channel device preparation.

[0010] The channel protection layer is composed of a metal oxide semiconductor thin film (AO)x(BO)y(ReO)z, wherein x+y+z=1, 0≤z≤0.1. Element A includes any one or a combination of at least two of In, Ga or Sn, wherein a typical but non-limiting combination includes a combination of In and Ga, a combination of Sn and In or a combination of Sn, In and Ga; element B includes any one or a combination of at least two of Zn, Si, Al, Ti, Mg, Zr, Hf, Ta, Bi or Nb, wherein a typical but non-limiting combination includes a combination of Zn and Si, a combination of Al and Ti, a combination of Mg and Zr or a combination of Hf, Ta, Bi and Nb; and element Re includes any one or a combination of at least two of Ce, Pr, Tb, Dy or Yb, wherein a typical but non-limiting combination includes a combination of Ce and Pr, a combination of Tb and Dy, a combination of Yb and Ce or a combination of Pr, Tb and Dy.

[0011] Preferably, the channel protection layer is a rare earth doped compound thin film, and the rare earth ions have two valence states. The rare earth oxide doped thin film includes cerium oxide, praseodymium oxide, terbium oxide and ytterbium oxide, and the praseodymium and terbium compound (such as boride, silicide, nitride, sulfide, fluoride, chloride, etc.) doped thin film. On the one hand, the rare earth oxide has a high binding energy for oxygen, which can effectively control the carrier concentration in the thin film; on the other hand, the rare earth ions in the double valence state of the rare earth compound can form a conversion center of photo-generated carriers, which can shield the influence of light on the active layer; in addition, the double valence state of the rare earth ions can “passivate” the influence of the hydrogen-related ion group, that is, the combination energy of the rare earth ions and the hydrogen group is strong, which inhibits the diffusion of hydrogen. Therefore, the protection layer thin film is beneficial to realize a short channel device.

[0012] More preferably, the channel protection layer is a tin oxide doped thin film, wherein the proportion of tin atoms in all metal atoms is >20%, for example, it can be 20.5%, 21%, 25%, 30%, 40% or 60%, etc., but is not limited to the listed values, and other values not listed in the value range are also applicable.

[0013] Preferably, the channel protection layer is a thin film in a crystalline form, which is not easily affected by etching liquid and plasma.

[0014] Preferably, the thickness of the channel protection layer is 5-60 nm, for example, it can be 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm or 60 nm, etc., but is not limited to the listed values, and other values not listed in the value range are also applicable.

[0015] The thickness of the channel protection layer is preferably 5-60 nm. When the thickness of the channel protection layer is less than 5 nm, the thin film cannot form a dense continuous film, and cannot resist the corrosion of acid solution well. When the thickness of the channel protection layer is greater than 60 nm, the thick film can cause the source and drain electrodes and the active layer to fail to form a good ohmic contact, thereby affecting the performance of the device.

[0016] More preferably, the channel protection layer is a crystalline thin film made by atomic layer deposition, including oxide thin films and nitride thin films, and multi-layer structure thin films stacked thereon. For example, tin oxide, zinc oxide, indium oxide, indium zinc oxide, gallium zinc oxide, tin zinc oxide, aluminum zinc oxide, aluminum nitride, titanium nitride, and rare earth doped oxides, etc. The thickness of the thin film is preferably 5-20 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, etc. The thin film made by this method has high density and good crystallinity. In particular, the active layer of the device can effectively control the carrier concentration distribution after being combined with the protection layer thin film made by this method, which is beneficial to the manufacture of short channel devices.

[0017] Preferably, the channel protection layer is made by magnetron sputtering, and the oxygen content in the sputtering atmosphere is more than 20%, for example, 20.5%, 25%, 30%, 40%, 50%, or 80%, etc. However, the values are not limited to the listed values, and other values not listed in the range are also applicable, and the oxygen content is preferably more than 50%.

[0018] Preferably, the oxygen content in the sputtering atmosphere of the channel protection layer is more than 20%, which has good chemical stability and can effectively resist the influence of hydrogen during the deposition of the passivation layer and subsequent preparation processes.

[0019] The channel protection layer has the characteristics of resisting etching, and can resist etching by dilute sulfuric acid, dilute hydrochloric acid, phosphoric acid, glacial acetic acid, or mixed acid containing nitric acid or hydrogen peroxide-based copper acid, and the etching rate is less than 0.01 nm / s.

[0020] The sacrificial layer is an amorphous A m B n compound thin film, and m+n=1. Wherein A is any one or a combination of at least two of In, Ga, Zn, B, Si, Al, Ti, Mg, Mo, Zr, V, Hf, Ta, Nb, and B is any one or a combination of at least two of O, S, F, and N.

[0021] The sacrificial layer of the present application is any one or a combination of at least two of amorphous oxide thin film, amorphous nitride thin film, amorphous oxynitride thin film, amorphous fluoride thin film or amorphous sulfide thin film, wherein typical but non-limiting combinations include a combination of oxide thin film and oxynitride thin film, a combination of sulfide thin film and oxide thin film or a combination of oxynitride thin film, sulfide thin film and oxide thin film.

[0022] Preferably, the sacrificial layer of the present application is an amorphous oxide thin film, including zinc oxide-based thin film, titanium oxide-based thin film, molybdenum oxide-based thin film, vanadium oxide-based thin film, etc. For example, zinc oxide, zinc aluminum oxide, zinc indium oxide, titanium oxide, molybdenum oxide, vanadium oxide, etc.

[0023] Preferably, the sacrificial layer of the present application is an amorphous nitride thin film, including zinc nitride, aluminum nitride, titanium nitride, zirconium nitride, boron nitride, etc.

[0024] Preferably, the sacrificial layer of the present application is an amorphous oxynitride thin film, including zinc oxynitride, molybdenum oxynitride, titanium oxynitride, niobium oxynitride, etc.

[0025] Preferably, the sacrificial layer of the present application is an amorphous fluoride thin film, including aluminum fluoride, zinc fluoride, molybdenum fluoride, titanium fluoride, niobium fluoride, etc.

[0026] Preferably, the sacrificial layer of the present application is an amorphous sulfide thin film, including zinc sulfide, molybdenum sulfide, vanadium sulfide, etc.

[0027] Preferably, the thickness of the sacrificial layer is 6-30 nm, for example, it can be 6 nm, 8 nm, 10 nm, 15 nm, 20 nm or 30 nm, etc., but is not limited to the listed values, and other values not listed within this range are also applicable.

[0028] Preferably, the thickness of the sacrificial layer of the present application is 6-30 nm. When the thickness of the sacrificial layer is less than 6 nm, the sacrificial layer is too thin, and it cannot effectively resist the "injection" or "diffusion" of metal atoms during sputtering of the source-drain electrode layer, causing metal atoms to enter the channel protection layer and thus affecting device performance. When the thickness of the sacrificial layer is greater than 30 nm, the sacrificial layer is too thick, which can cause the source-drain electrode to fail to form a good ohmic contact with the active layer, thus affecting device performance.

[0029] Preferably, the thickness of the active layer is 2-100 nm, for example, it can be 2 nm, 5 nm, 10 nm, 30 nm, 50 nm, 80 nm or 100 nm, etc., but is not limited to the listed values, and other values not listed within this range are also applicable, preferably 5-50 nm, more preferably 10-40 nm.

[0030] Preferably, the active layer is a single-layer structure or a stacked structure.

[0031] The stack structure can be two layers, three layers, four layers, five layers or six layers, etc.

[0032] Preferably, the metal oxide thin film transistor comprises, from bottom to top, a substrate, a gate, a gate insulating layer, an active layer, a channel protection layer and a sacrificial layer; the metal oxide thin film transistor further comprises a source electrode and a drain electrode covering on the sacrificial layer and electrically connected to both ends of the active layer; the metal oxide thin film transistor further comprises a passivation layer covering on the source electrode, the drain electrode and the channel protection layer.

[0033] Preferably, the channel protection layer replaces the active layer in the metal oxide thin film transistor.

[0034] The channel protection layer can replace the active layer in the metal oxide thin film transistor, because the channel protection layer itself is an oxide material and can also exhibit good semiconductor properties by proper composition.

[0035] Preferably, the metal oxide thin film transistor comprises, from bottom to top, a substrate, a gate, a gate insulating layer, a channel protection layer and a sacrificial layer; the metal oxide thin film transistor further comprises a source electrode and a drain electrode covering on the sacrificial layer and electrically connected to both ends of the channel protection layer; the metal oxide thin film transistor further comprises a passivation layer covering on the source electrode, the drain electrode and the channel protection layer.

[0036] In the second aspect, the application further provides a preparation method of the metal oxide thin film transistor according to the first aspect, which comprises sequentially depositing a channel protection layer and a sacrificial layer on an active layer and completing patterning in the same etching process.

[0037] Preferably, the preparation method comprises the following steps:

[0038] (1) forming a gate on a substrate and patterning;

[0039] (2) covering a gate insulating layer on the gate and patterning;

[0040] (3) sequentially depositing an active layer, a channel protection layer and a sacrificial layer on the gate insulating layer and completing patterning in the same etching process;

[0041] (4) after forming a source electrode and a drain electrode electrically connected to both ends of the active layer on the sacrificial layer, etching; in the process of etching the source and drain electrodes, the sacrificial layer not protected by the source and drain electrodes is etched at the same time;

[0042] (5) forming a passivation layer on the source electrode, the drain electrode and the channel protection layer.

[0043] The method for preparing the metal oxide thin film transistor has the advantages that the active layer, the channel protection layer and the sacrificial layer can be continuously deposited, one etching process can be realized, the complexity and cost of the preparation process are not obviously increased, and the method is suitable for large-scale popularization and application.

[0044] Preferably, in the etching of step (4), the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is greater than 20:1, for example, can be 21:1, 23:1, 25:1, 50:1, 100:1 or 1000:1, but is not limited to the listed values, and other values not listed in the value range are also applicable.

[0045] More preferably, before step (5) is performed, an etching process is added to etch the sacrificial layer.

[0046] When the sacrificial layer in the present application is not completely etched in the etching process of the source and drain electrodes, an etching process is added to etch the sacrificial layer before step (5) is performed; when the sacrificial layer is completely etched in the etching process of the source and drain electrodes, the etching process can not be added.

[0047] Preferably, in the etching of the sacrificial layer, the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is greater than 20:1, for example, can be 21:1, 23:1, 25:1, 50:1, 100:1 or 1000:1, but is not limited to the listed values, and other values not listed in the value range are also applicable.

[0048] Preferably, after the etching of the sacrificial layer, an atmosphere heat treatment or a plasma treatment is performed, which mainly functions to repair and adjust the active layer, and this step can be determined according to actual conditions.

[0049] Preferably, the gas source of the atmosphere heat treatment includes any one or a combination of at least two of air, oxygen, nitrogen, ozone or argon, and a typical but non-limiting combination includes a combination of air and oxygen, a combination of nitrogen and ozone, or a combination of argon, air and nitrogen.

[0050] Preferably, the temperature of the atmosphere heat treatment is 200-450°C, for example, can be 200°C, 250°C, 300°C, 350°C, 400°C or 450°C, but is not limited to the listed values, and other values not listed in the value range are also applicable.

[0051] Preferably, the time of the atmosphere heat treatment is 30-120 min, for example, can be 30 min, 50 min, 80 min, 100 min, 110 min or 120 min, but is not limited to the listed values, and other values not listed in the value range are also applicable.

[0052] Preferably, the gas source of the plasma treatment includes any one or a combination of at least two of argon, nitrous oxide, oxygen, ozone, sulfur fluoride, carbon fluoride or nitrogen, wherein typical but non-limiting combinations include a combination of argon and nitrous oxide, a combination of oxygen and ozone, a combination of sulfur fluoride and carbon fluoride or a combination of nitrogen, ozone and sulfur fluoride.

[0053] Preferably, the time of the plasma treatment is 5-300s, for example, can be 5s, 20s, 40s, 90s, 100s, 120s or 300s, etc., but is not limited to the listed values, and other unlisted values within the range are also applicable.

[0054] The metal oxide semiconductor forming the active layer in the present application adopts a vacuum magnetron sputtering process, which can be single-target sputtering or multi-target co-sputtering, preferably single-target sputtering. Because single-target sputtering can provide better and more stable thin films with more controllable microstructures, and the sputtering particles are not disturbed by more factors in the recombination process as in co-sputtering thin films.

[0055] The patterning process of the active layer in the present application adopts a photolithography process combined with a wet etching method. The etching solution used in the wet etching includes a mixture of phosphoric acid, nitric acid and glacial acetic acid, a commercial oxalic acid-based etching solution, a dilute hydrochloric acid etching solution and a hydrofluoric acid etching solution.

[0056] The preparation method of the source-drain electrode in the present application can be sputtering, thermal evaporation or other deposition methods, and the preferred method is sputtering deposition because the thin film prepared by this method has good adhesion to the substrate, excellent uniformity and can be prepared in a large area. The patterning process of the source-drain electrode adopts a photolithography process combined with a wet etching method. The etching solution used in the wet etching includes a mixture of phosphoric acid, nitric acid and glacial acetic acid or a mixture based on hydrogen peroxide.

[0057] The etching solution used in the wet etching in the present application can be a conventional metal etching solution in the industry (such as a hydrogen peroxide-based etching solution, an aluminate etching solution). On the one hand, the channel protection layer of the present application can effectively resist the etching of the wet hydrogen peroxide-based etching solution, and has a very high etching selectivity with metals (such as molybdenum, molybdenum alloy, molybdenum / copper, molybdenum / copper / molybdenum, etc.), the channel protection layer is basically not affected by the etching solution, and the prepared device has excellent performance and good stability. On the other hand, the channel protection layer of the present application can effectively resist the etching of the aluminate etching solution, and has a very high etching selectivity with metals (such as molybdenum / aluminum, molybdenum / aluminum / molybdenum, etc.), the channel protection layer is basically not affected by the etching solution, and the prepared device has excellent performance and good stability.

[0058] The thin film prepared by the vacuum magnetron sputtering process is generally fast in deposition rate due to the participation of high-energy plasma; and the thin film has not enough time to perform relaxation process in the deposition process, which causes a certain proportion of dislocation and stress to remain in the thin film. This needs a post-heating annealing treatment to continue to achieve the required relative stability and improve the performance of the thin film.

[0059] The annealing treatment of the present application is mostly arranged after the deposition of the active layer and after the deposition of the passivation layer. On the one hand, the annealing treatment after the deposition of the active layer can effectively improve the in-situ defects in the active layer and improve the ability of the active layer to resist possible damage in the subsequent process. On the other hand, in the subsequent deposition process of the passivation layer, due to the participation of plasma and the modification effect of active groups, an "activation" process is needed to further eliminate the interface state and some donor doping effects. Heating treatment can be used, and plasma treatment of the interface (such as the gate insulating layer / semiconductor interface, the active layer / passivation layer interface, etc.) can be used.

[0060] Through the above-mentioned treatment process, the performance of the device can be effectively improved, and the stability of the device can be improved.

[0061] As a preferred technical solution of the present application, the preparation method comprises the following steps:

[0062] (1) forming a gate on a substrate and patterning; the preparation method of the gate is sputtering deposition;

[0063] (2) covering a gate insulating layer on the gate and patterning;

[0064] (3) sequentially depositing an active layer, a channel protection layer and a sacrifice layer on the gate insulating layer, and completing patterning in the same etching process; the method for depositing the active layer is single-target sputtering; the patterning process of the active layer adopts a photolithography process combined with a wet etching method;

[0065] (4) after forming source and drain electrodes electrically connected to both ends of the active layer on the sacrifice layer, etching; in the etching, the ratio of the etching rate of the sacrifice layer thin film to the etching rate of the protection layer thin film is > 20:1; the preparation method of the source and drain electrodes is sputtering deposition; the patterning process of the source and drain electrodes adopts a photolithography process combined with a wet etching method;

[0066] (5) after the sacrifice layer is etched clean, forming a passivation layer on the source and drain electrodes and the channel protection layer.

[0067] Compared with the prior art, the present application has at least the following beneficial effects:

[0068] (1) The channel protection layer of the metal oxide thin film transistor provided by the application can effectively block the influence of etching liquid and plasma in the deposition process of the passivation layer; the sacrificial layer can effectively prevent the "diffusion" or "injection" of metal atoms to the active layer in the sputtering process of the source and drain electrodes, and the area of the sacrificial layer not covered by the source and drain electrode layer will be completely etched clean in the etching or subsequent process of the source and drain electrode, thereby avoiding the influence of metal atoms on the device;

[0069] (2) The introduction of the sacrificial layer avoids the "bombardment" influence of metal atoms on the channel protection layer and the active layer in the metal thin film deposition process, effectively inhibits the formation of the high oxygen vacancy concentration area in the channel protection layer and the active layer, thereby avoiding the shortening of the effective channel length and being conducive to the preparation of short channel devices; in addition, the channel protection layer thin film used in the application has a high binding energy to oxygen, can effectively control the carrier concentration in the thin film, and can form a conversion center of photo-generated carriers, which can shield the influence of light on the active layer; furthermore, the binding energy of the channel protection layer thin film to hydrogen groups is strong, and the diffusion of hydrogen is inhibited. Therefore, the protection layer thin film is also conducive to the realization of short channel devices.

[0070] (3) The active layer, the channel protection layer and the sacrificial layer in the preparation method of the metal oxide thin film transistor provided by the application can be continuously deposited, and one etching pattern can be realized, which is simple to operate, low in preparation cost and has a large-scale industrialized application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0071] Figure 1 is a cross-sectional schematic view of the metal oxide thin film transistor in Example 1 of the application.

[0072] Figure 2 is a flowchart of the preparation method of the metal oxide thin film transistor in Example 1 of the application.

[0073] Figure 3 is a cross-sectional schematic view of the metal oxide thin film transistor in Example 4 of the application.

[0074] Figure 4 is a uniformity graph of the metal oxide thin film transistor in Example 1 of the application.

[0075] Figure 5 is a uniformity graph of the metal oxide thin film transistor in Comparative Example 1 of the application.

[0076] Figure 6 is a positive thermal bias stability graph of the metal oxide thin film transistor in Example 1 of the application.

[0077] Figure 7 is a positive thermal bias stability graph of the metal oxide thin film transistor in Comparative Example 1 of the application.

[0078] Figure 8 is the device transfer characteristic curve of the metal oxide thin film transistor in Example 1 at different channel lengths.

[0079] Figure 9 is the device transfer characteristic curve of the metal oxide thin film transistor in Comparative Example 1 at different channel lengths.

[0080] Figure 10 is the percentage spectrum of each element at the channel protection layer / passivation layer interface of the metal oxide thin film transistor in Example 1 of the present application with etching time.

[0081] Figure 11 is the percentage spectrum of each element at the channel protection layer / passivation layer interface of the metal oxide thin film transistor in Comparative Example 2 of the present application with etching time.

[0082] Figure 12 is the Mo element spectrum at the channel protection layer / passivation layer interface of the metal oxide thin film transistor in Comparative Example 2 of the present application. DETAILED DESCRIPTION

[0083] The technical solutions of the present application are further illustrated below by specific embodiments in combination with the accompanying drawings.

[0084] The present application is further described below in detail. However, the following examples are only simple examples of the present application and do not represent or limit the protection scope of the present application, and the protection scope of the present application is subject to the claims.

[0085] Example 1

[0086] The present embodiment provides a metal oxide thin film transistor, a cross-sectional schematic view of which is shown in Figure 1 .

[0087] The metal oxide thin film transistor sequentially comprises, from bottom to top, a substrate 01, a gate 02, a gate insulating layer 03, an active layer 04-1, a channel protection layer 04-2, and a sacrificial layer 04-3; the metal oxide thin film transistor further comprises a source electrode 05-1 and a drain electrode 05-2 covering the sacrificial layer 04-3 and electrically connected to both ends of the active layer 04-1; the metal oxide thin film transistor further comprises a passivation layer 06 covering the source electrode 05-1, the drain electrode 05-2, and the channel protection layer 04-2.

[0088] The present embodiment also provides a preparation method of the above-mentioned metal oxide thin film transistor, a flowchart of which is shown in Figure 2 .

[0089] The preparation method comprises the following steps:

[0090] (1) Forming a gate electrode on a substrate and patterning;

[0091] (2) Forming a gate insulating layer on the gate electrode and patterning;

[0092] (3) Depositing an active layer, a channel protection layer and a sacrificial layer on the gate insulating layer in sequence and patterning in the same etching process;

[0093] (4) After forming source and drain electrodes electrically connected to both ends of the active layer on the sacrificial layer, etching is performed; in the etching, the ratio of the sacrificial layer film etching rate to the protection layer film etching rate is 21:1; in the process of etching the source and drain electrodes, the sacrificial layer not protected by the source and drain electrodes is etched at the same time;

[0094] (5) Etching the substrate in aluminate etching solution for 10s to further etch the sacrificial layer, and forming a passivation layer on the source and drain electrodes and the channel protection layer after the sacrificial layer is etched clean; in the etching of the sacrificial layer, the ratio of the sacrificial layer film etching rate to the protection layer film etching rate is 100:1.

[0095] The substrate in the embodiment is a hard glass substrate;

[0096] The gate electrode is a 200nm-thick metal molybdenum (Mo) electrode prepared by magnetron sputtering and patterned by wet etching;

[0097] The gate insulating layer is a laminated structure of silicon nitride (SiNx, 300nm) and silicon oxide (SiOx, 100nm) prepared by chemical vapor deposition, wherein the silicon nitride contacts the metal gate electrode; and the gate insulating layer is patterned by dry etching;

[0098] The active layer is a praseodymium-doped indium gallium zinc oxide thin film (Pr:IGZO), wherein Pr:In:Ga:Zn=0.05:2:0.5:1mol, and the thickness is 20nm;

[0099] The channel protection layer is a praseodymium-doped indium tin zinc oxide thin film (Pr:ITZO), wherein Pr:In:Sn:Zn=0.05:2:2:1mol, and the thickness is 10nm; the channel protection layer is a crystalline thin film; the oxygen content in the sputtering atmosphere during sputtering of the channel protection layer is 22%;

[0100] The sacrificial layer is an indium zinc oxide thin film, wherein In:Zn=1:2mol, and the thickness is 30nm; the sacrificial layer is an amorphous oxide thin film;

[0101] The active layer, the channel protection layer and the sacrificial layer are all prepared continuously by magnetron sputtering, and after annealing in a 350℃ oven for 60 minutes in air, the thin film is patterned by etching with oxalic acid etching solution. The specific steps are as follows: first, apply a photoresist (such as Ruisheng 304 positive photoresist) on the annealed thin film, and after pre-baking at 90℃, use a mask to perform ultraviolet light irradiation by an exposure machine. The area covered by the mask is not irradiated by ultraviolet light, while the area not covered by the mask is irradiated by ultraviolet light. The substrate is sprayed in the developing solution for 40s, and the photoresist in the area irradiated by ultraviolet light is dissolved. The substrate is further post-baked on a hot table at 120℃ for two minutes, thereby forming the required photoresist pattern on the thin film. The substrate is immersed in oxalic acid etching solution for etching for 60s, and the required pattern is etched out. Further processing in the photoresist remover for 5 minutes, and after cleaning, the required substrate is obtained.

[0102] The source and drain electrodes are a Mo / Cu / Mo (molybdenum / copper / molybdenum) stack structure, with thicknesses of 30 / 300 / 30nm respectively. The patterning process of the source and drain electrodes is performed by photolithography combined with wet etching, and the etching solution is a hydrogen peroxide-based fluorine-free copper acid etching solution. After etching the source and drain electrodes, no photoresist removal treatment is required, and then the substrate is etched in aluminum acid etching solution for 10s, further completing the etching of the sacrificial layer.

[0103] The passivation layer is a silicon oxide thin film prepared by chemical vapor deposition, with a thickness of 400nm. After deposition, the passivation layer is annealed in a 300℃ oven for 60 minutes in air, and then patterned by dry etching.

[0104] Example 2

[0105] This embodiment provides a metal oxide thin film transistor, a cross-sectional schematic view of which is shown in Figure 1 .

[0106] The metal oxide thin film transistor sequentially includes a substrate, a gate, a gate insulating layer, an active layer, a channel protection layer and a sacrificial layer from bottom to top. The metal oxide thin film transistor further includes a source electrode and a drain electrode covering the sacrificial layer and electrically connected to both ends of the active layer. The metal oxide thin film transistor further includes a passivation layer covering the source electrode, the drain electrode and the channel protection layer.

[0107] This embodiment also provides a preparation method of the above-mentioned metal oxide thin film transistor, which includes the following steps:

[0108] (1) Forming a gate on a substrate and patterning;

[0109] (2) Covering a gate insulating layer on the gate and patterning;

[0110] (3) Depositing successively the active layer, the channel protection layer and the sacrificial layer on the gate insulating layer, and completing patterning in the same etching process;

[0111] (4) After forming the source electrode and the drain electrode electrically connected to both ends of the active layer on the sacrificial layer, etching is performed; in the etching, the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is 1000:1; in the etching of the source and drain electrodes, the sacrificial layer not protected by the source and drain electrodes is etched at the same time;

[0112] (5) Forming the passivation layer on the source electrode, the drain electrode and the channel protection layer.

[0113] The substrate in the embodiment is a hard glass substrate;

[0114] The gate electrode is a metal molybdenum-aluminum-molybdenum (Mo / Al / Mo, 30 / 300 / 30 nm) electrode prepared by magnetron sputtering and patterned by wet etching;

[0115] The gate insulating layer is a laminated structure of silicon nitride (SiNx, 300 nm) and silicon oxide (SiOx, 50 nm) prepared by chemical vapor deposition, wherein the silicon nitride contacts the metal gate electrode; and the gate insulating layer is patterned by dry etching;

[0116] The active layer is a terbium-doped indium gallium oxide film (Tb:IGO) with Tb:In:Ga = 0.05:4:1 mol and a thickness of 10 nm;

[0117] The channel protection layer is a terbium-doped indium tin zinc oxide film (Tb:ITZO) with Tb:In:Sn:Zn = 0.05:2:1:1 mol and a thickness of 20 nm; the channel protection layer is a crystalline film; and the oxygen content in the sputtering atmosphere during sputtering of the channel protection layer is 50%;

[0118] The sacrificial layer is a zinc oxynitride film (ZnON) with a thickness of 20 nm; the sacrificial layer is an amorphous oxynitride film;

[0119] The active layer, the channel protection layer and the sacrificial layer are continuously prepared by magnetron sputtering, and are patterned by etching with oxalic acid after annealing in an air atmosphere at 350°C for 60 minutes; the specific steps are the same as those in Embodiment 1.

[0120] The source and drain electrodes are a laminated structure of Mo / Al / Mo with thicknesses of 30 / 300 / 30 nm; the patterning process of the source and drain electrodes is performed by photolithography combined with wet etching, and the etching solution is a mixture of phosphoric acid, nitric acid and glacial acetic acid; in the etching of the source and drain electrodes, the sacrificial layer of the device is etched completely by the etching solution without the need for an additional etching process.

[0121] The passivation layer is a laminated film of silicon oxide and silicon nitride prepared by chemical vapor deposition, with thicknesses of 300 nm and 100 nm respectively; the passivation layer is annealed in an air atmosphere at 300℃ for 60 minutes after deposition of silicon oxide, and then silicon nitride is deposited, and the pattern is formed by dry etching.

[0122] Embodiment 3

[0123] The metal oxide thin film transistor comprises, from bottom to top, a substrate, a gate electrode, a gate insulating layer, an active layer, a channel protection layer and a sacrificial layer; the metal oxide thin film transistor further comprises a source electrode and a drain electrode covering the sacrificial layer and electrically connected to both ends of the active layer; the metal oxide thin film transistor further comprises a passivation layer covering the source electrode, the drain electrode and the channel protection layer.

[0124] The embodiment also provides a preparation method of the metal oxide thin film transistor, comprising the following steps:

[0125] (1) forming a gate electrode on a substrate and patterning;

[0126] (2) covering a gate insulating layer on the gate electrode and patterning;

[0127] (3) sequentially depositing an active layer, a channel protection layer and a sacrificial layer on the gate insulating layer, and completing patterning in the same etching process;

[0128] (4) after forming a source electrode and a drain electrode electrically connected to both ends of the active layer on the sacrificial layer, etching; in the etching, the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is > 20:1; in the etching of the source and drain electrodes, the sacrificial layer not protected by the source and drain electrodes is etched at the same time;

[0129] (5) forming a passivation layer on the source electrode, the drain electrode and the channel protection layer.

[0130] The substrate in the embodiment is a hard glass substrate;

[0131] The gate electrode is a metal molybdenum-titanium alloy / copper / molybdenum-titanium alloy (MoTi / Cu / MoTi, 30 / 300 / 50 nm) electrode prepared by magnetron sputtering, and is patterned by wet etching;

[0132] The gate insulating layer is a laminated structure of silicon nitride (SiNx, 300 nm) and silicon oxide (SiOx, 100 nm) prepared by chemical vapor deposition, wherein the silicon nitride contacts the metal gate electrode; the pattern is formed by dry etching;

[0133] The active layer is a thin film of terbium-doped indium gallium tin oxide (Tb:IGZO) with Tb:In:Ga:Zn = 0.05:4:1:2 mol, and a thickness of 20 nm;

[0134] The channel protection layer is a thin film of terbium-doped zinc tin oxide (Tb:ZTO) prepared by a solution method, with Tb:Sn:Zn = 0.01:1:1 mol, and a thickness of 5 nm; the channel protection layer is a crystalline thin film;

[0135] The sacrificial layer is a thin film of molybdenum sulfide (MoS2) prepared by a chemical vapor deposition method, with a thickness of 6 nm; the sacrificial layer is an amorphous sulfide thin film;

[0136] The active layer is prepared continuously by a magnetron sputtering method, the channel protection layer is prepared by a solution method, and the sacrificial layer is prepared by a chemical vapor deposition method; the above-mentioned stacked thin film is combined with argon plasma treatment and etched by oxalic acid etching solution to form a pattern; other related steps are the same as those in Example 1.

[0137] The source-drain electrode is a stacked structure of MoTi / Cu / MoTi with thicknesses of 30 / 300 / 50 nm; the source-drain electrode is patterned by a photolithography process combined with a wet etching method, and the etching solution is a hydrogen peroxide-based etching solution containing fluorine. In the process of etching the source-drain electrode, the sacrificial layer of the device is partially etched.

[0138] Before depositing the passivation layer, the substrate is treated in a mixed plasma of nitrogen (N2) and sulfur fluoride (SF6) for 20 s, and then the passivation layer is prepared.

[0139] The passivation layer is a stacked thin film of silicon oxide and silicon nitride prepared by a chemical vapor deposition method, with thicknesses of 300 nm and 100 nm, respectively;

[0140] The passivation layer is annealed in an air atmosphere at 300°C for 60 minutes after depositing silicon oxide, and then silicon nitride is deposited and patterned by dry etching.

[0141] Example 4

[0142] This example provides a metal oxide thin film transistor, which is the same as Example 2 except that the channel protection layer replaces the active layer, and a cross-sectional schematic view thereof is shown in Figure 3 .

[0143] The metal oxide thin film transistor comprises, from bottom to top, a substrate, a gate electrode, a gate insulating layer, a channel protection layer and a sacrificial layer; the metal oxide thin film transistor further comprises a source electrode and a drain electrode which are covered on the sacrificial layer and electrically connected to both ends of the channel protection layer; and the metal oxide thin film transistor further comprises a passivation layer which is covered on the source electrode, the drain electrode and the channel protection layer.

[0144] Embodiment 5

[0145] The metal oxide thin film transistor of the embodiment has a double-layer structure of the active layer, and the rest is the same as that of the embodiment 1.

[0146] Specifically, the bottom active layer in contact with the gate insulating layer of silicon oxide is an indium gallium zinc oxide film (IGZO) with In:Ga:Zn = 1:1:1 mol and a thickness of 10 nm; and the upper active layer covered thereon is a praseodymium-doped indium gallium zinc oxide film (Pr:IGZO) with Pr:In:Ga:Zn = 0.05:3:0.5:1 mol and a thickness of 20 nm.

[0147] Embodiment 6

[0148] The metal oxide thin film transistor of the embodiment has a three-layer structure of the active layer, and the rest is the same as that of the embodiment 1.

[0149] Specifically, the bottom active layer in contact with the gate insulating layer of silicon oxide is an indium gallium zinc oxide film (IGZO) with In:Ga:Zn = 1:1:1 mol and a thickness of 10 nm; the middle active layer is a praseodymium-doped indium gallium zinc oxide film (Pr:IGZO) with Pr:In:Ga:Zn = 0.05:4:0.5:1 mol and a thickness of 10 nm; and the top active layer covered thereon is an indium gallium zinc oxide film (IGZO) with In:Ga:Zn = 1:1:1 mol and a thickness of 10 nm.

[0150] Embodiment 7

[0151] The metal oxide thin film transistor of the embodiment is the same as that of the embodiment 1 except that the thickness of the channel protection layer is 60 nm.

[0152] Embodiment 8

[0153] The metal oxide thin film transistor of the embodiment is the same as that of the embodiment 1 except that the channel protection layer is a 5-nm-thick tin zinc oxide film prepared by atomic layer deposition.

[0154] Embodiment 9

[0155] This example provides a metal oxide thin film transistor, which is the same as example 1 except that the thickness of the channel protection layer is 3 nm.

[0156] Example 10

[0157] This example provides a metal oxide thin film transistor, which is the same as example 1 except that the thickness of the channel protection layer is 70 nm.

[0158] Example 11

[0159] This example provides a metal oxide thin film transistor, which is the same as example 1 except that the thickness of the sacrificial layer is 3 nm.

[0160] Example 12

[0161] This example provides a metal oxide thin film transistor, which is the same as example 1 except that the thickness of the sacrificial layer is 40 nm.

[0162] Example 13

[0163] This example provides a method for preparing a metal oxide thin film transistor, which is the same as example 1 except that in step (4), the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is 15:1.

[0164] Comparative Example 1

[0165] This comparative example provides a metal oxide thin film transistor, which is the same as example 1 except that no channel protection layer and sacrificial layer are provided on the active layer, so that only the process of etching the source-drain electrode is performed when the source-drain electrode is patterned, and no subsequent alumina treatment process is performed.

[0166] The uniformity graph of the metal oxide thin film transistor in example 1 is shown in FIG. 1, and the uniformity graph of the metal oxide thin film transistor in comparative example 1 is shown in FIG. 2. By comparison, it can be seen that the device uniformity of the metal oxide thin film transistor in example 1 is significantly better than that in comparative example 1, and the hysteresis phenomenon of the device is not obvious. Figure 4 Figure 5 The forward thermal bias stability graph of the metal oxide thin film transistor in example 1 is shown in FIG. 3, and the forward thermal bias stability graph of the metal oxide thin film transistor in comparative example 1 is shown in FIG. 4. By comparison, it can be seen that the forward thermal bias stability of the metal oxide thin film transistor in example 1 is significantly better than that in comparative example 1.

[0167] The forward thermal bias stability graph of the metal oxide thin film transistor in example 1 is shown in FIG. 3, and the forward thermal bias stability graph of the metal oxide thin film transistor in comparative example 1 is shown in FIG. 4. By comparison, it can be seen that the forward thermal bias stability of the metal oxide thin film transistor in example 1 is significantly better than that in comparative example 1. Figure 6 Figure 7 ​​As shown in the figure. By comparison, it can be seen that the threshold voltage drift of the metal oxide thin film transistor in Example 1 is 0.5V, while the threshold voltage drift of Comparative Example 1 is 4.2V. It can be seen that the stability of the device is significantly improved after adding the protective layer and the sacrificial layer.

[0168] The device transfer characteristic curves of the metal oxide thin film transistor in Example 1 at different channel lengths are as follows: Figure 8 As shown, the device transfer characteristic curves of the metal oxide thin-film transistor in Comparative Example 1 at different channel lengths are as follows: Figure 9 As shown, in Comparative Example 1, the threshold voltage of the device shifts negatively as the channel length decreases. When L = 1.5 μm, the device is in a "conducting" state and loses its switching characteristics. However, in Example 1, the threshold voltage of the device does not show a significant negative shift as the channel length decreases, and it is possible to fabricate a device with a shorter channel (L = 1.5 μm).

[0169] Comparative Example 2

[0170] This comparative example provides a metal oxide thin film transistor. Except for the absence of a sacrificial layer on the active layer, the metal oxide thin film transistor is the same as in Example 1. The performance parameters of the fabricated device are listed in Table 1.

[0171] To verify that source and drain electrode metals can "inject" or "diffuse" metal atoms into the underlying metal oxide layer during sputtering deposition, we conducted related experiments using time-of-flight secondary ion mass spectrometry (TOF-SIMS) to observe the elemental distribution characteristics at the interface between the channel guard layer and the passivation layer with and without a sacrificial layer.

[0172] Depend on Figure 10 It can be seen that no obvious molybdenum elemental signal spectrum was observed at the interface between the channel guard layer and the passivation layer of the device with the sacrificial layer, while the device without the sacrificial layer in Comparative Example 2 showed a more obvious molybdenum elemental signal spectrum at the interface, as detailed below. Figure 11 As shown. It should be noted that, as... Figure 12 As shown, although the molybdenum content at this interface is low, the peak spectrum at this interface matches the molybdenum content well, further indicating the presence of molybdenum at this interface.

[0173] As can be seen from the above, during sputtering deposition, metal atoms from the source and drain electrodes can be "injected" or "diffused" into the underlying thin film functional layer. However, the influence of this interface layer can be mitigated by setting a sacrificial layer. Therefore, this confirms that metal atoms from the source and drain electrodes in Comparative Example 1 may remain in the thin film in contact with them during deposition through "diffusion" or "injection," thereby affecting the uniformity and stability of the device.

[0174] The performance parameters of the metal oxide thin film transistors in the above examples and the comparative examples are measured by using a semiconductor parameter analyzer, including threshold voltage, field effect mobility, thermal bias stability, etc.

[0175] The channel width (W) and the channel length (L) of the device are unified as W / L=10 / 5 μm without special indication. The threshold voltage of the device corresponds to the gate-source voltage (Vgs) when the source-drain current is 1 nA in the threshold voltage value transfer curve (Vds=10 V), and the field effect mobility corresponds to the maximum value of the saturation mobility.

[0176] The uniformity of the device is an important parameter for evaluating the performance of the driving backplane, and determines the application products that can be corresponded. The threshold voltage (V th ) of the device is evaluated by using the standard deviation in the present application, so as to reflect the uniformity of the backplane device. The calculation method of the standard deviation σ of V th is as follows:

[0177]

[0178] Wherein, n is the number of the device V th , is the average value of V th . In the present application, the corresponding area of the substrate is unified as 200 mm*200 mm, and the standard deviation σ of V th of the substrate prepared in each example is shown in Table 1.

[0179] The test method of the thermal bias stability (PBTS) is as follows: firstly, the substrate is placed on the hot plate of a test machine at 60 ℃, and the initial transfer characteristic of the device is tested after the temperature of the substrate reaches 60 ℃ and is stable for a certain time; then, a positive bias of 30 V is applied between the gate and the source, and the source-drain voltage is kept as 0 V, and the transfer characteristic curve of the device is tested again after 3600 s; the drift of the threshold voltage is obtained by extracting the difference between the threshold voltage parameters in the two transfer characteristic curves, so as to obtain the PBTS characteristic of the device.

[0180] The results of the device parameters in each example and the comparative example are shown in Table 1.

[0181] Table 1: Related parameter table of each example

[0182]

[0183]

[0184] It can be seen from Table 1 that:

[0185] In Examples 1-8, the metal oxide thin film transistor device has relatively good performance, good uniformity of threshold voltage, and good stability, and the short channel (L = 1.5 μm) device has normal performance and the threshold voltage thereof is consistent with that of the long channel (L = 5 μm) device.

[0186] For the channel protection layer, when the thickness of the channel protection layer is relatively thin (Example 9, the channel protection layer is 3 nm), the channel protection layer film fails to form a continuous film, the active layer is affected by the etching liquid in the process of etching the sacrificial layer, the threshold voltage of the device is positively shifted, the uniformity of the device is degraded, the mobility of the device is decreased, the stability is degraded, and the threshold voltage of the short channel device is negatively shifted; when the thickness of the channel protection layer is relatively thick (Example 10, the channel protection layer is 70 nm), since the channel protection layer is also a film material with a certain carrier concentration, the absolute carrier number of the device is too high, the threshold voltage of the device is negatively shifted, the short channel device is in the "on" state, and the device loses the "switching" characteristic.

[0187] In addition, for the sacrificial layer, when the thickness of the sacrificial layer is relatively thin (Example 11, the sacrificial layer is 3 nm), the sacrificial layer fails to form an effective function layer for blocking the "injection" or "diffusion" of metal atoms, the threshold voltage of the device is relatively negatively shifted, the uniformity of the device is degraded, the stability is degraded, and the short channel device is in the "on" state; when the thickness of the sacrificial layer is relatively thick (Example 12, the sacrificial layer is 40 nm), since the carrier concentration of the sacrificial layer is generally low, the source and drain electrodes cannot form a good ohmic contact with the active layer, and the mobility of the device is severely decreased.

[0188] In terms of the etching selectivity ratio of the sacrificial layer and the channel protection layer, when the etching selectivity ratio is relatively low (Example 13, the etching selectivity ratio is 15:1), that is, the etching process of the sacrificial layer also has a certain etching effect on the protection layer, thereby easily causing the threshold voltage of the device to be positively shifted, the uniformity of the device to be degraded, the mobility to be decreased, the stability to be degraded, and the short channel device to be negatively shifted.

[0189] To better verify the effectiveness of the present application, we set two key comparative examples 1 and 2. As can be seen from Table 1, when the device is not provided with a channel protection layer and a sacrificial layer (comparative example 1), the active layer of the device is subjected to the phenomenon of "injection" or "diffusion" of metal atoms during the deposition of the source and drain electrodes, and the active layer is easily affected by the etching liquid during the etching of the electrodes, resulting in a positive shift of the threshold voltage of the device, a serious decrease in the mobility, a degradation in stability, a negative shift of the threshold voltage of the short channel device, and a certain degree of degradation in the uniformity of the device. In addition, when the device is not provided with a sacrificial layer (comparative example 2), the channel protection layer of the device is subjected to the phenomenon of "injection" or "diffusion" of metal atoms during the deposition of the source and drain electrodes, the threshold voltage of the device is negatively shifted, the mobility is decreased, the stability is degraded, and the short channel device cannot be successfully manufactured. Therefore, this further proves the superiority of the present application in terms of device uniformity, stability, and the realization of short channel devices.

[0190] The applicant declares that the above description is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. It should be understood by those skilled in the art that any changes or replacements within the technical scope disclosed by the present application can be easily thought of by any person skilled in the art, and all such changes or replacements fall within the protection scope and disclosure scope of the present application.

Claims

1. A metal oxide thin film transistor, characterized by, The active layer of the metal oxide thin film transistor is sequentially provided with a channel protection layer and a sacrifice layer; the channel protection layer is a metal oxide semiconductor thin film (AO) x (BO) y (ReO) z , wherein x+y+z=1, 0 wherein element A comprises any one or a combination of at least two of In, Ga or Sn; element B comprises any one or a combination of at least two of Zn, Si, Al, Ti, Mg, Zr, Hf, Ta, Bi or Nb; and element Re comprises any one or a combination of at least two of Ce, Pr, Tb, Dy or Yb; The channel protection layer is a rare earth doped oxide film, and the rare earth ions contain two valence states simultaneously. The sacrificial layer is amorphous A m B n Compound thin film, m+n = 1; wherein A is any one or a combination of at least two of In, Ga, Zn, B, Si, Al, Ti, Mg, Mo, Zr, V, Hf, Ta, Nb, B is any one or a combination of at least two of S, F, N; The sacrificial layer is any one or a combination of at least two of an amorphous nitride film, an amorphous fluoride film or an amorphous sulfide film.

2. The metal oxide thin film transistor according to claim 1, wherein The channel protection layer is a crystalline film.

3. The metal oxide thin film transistor according to claim 1, wherein The thickness of the channel protection layer is 5-60 nm.

4. The metal oxide thin film transistor according to claim 1, wherein The channel protection layer is a tin oxide doped film, and the proportion of tin atoms in all metal atoms is greater than 20%.

5. The metal oxide thin film transistor according to claim 1, wherein The channel protection layer is prepared by a magnetron sputtering method, and the oxygen content in the sputtering atmosphere is greater than 20%.

6. The metal oxide thin film transistor according to claim 5, wherein The channel protection layer is prepared by a magnetron sputtering method, and the oxygen content in the sputtering atmosphere is greater than 50%.

7. The metal oxide thin film transistor according to claim 1, wherein The thickness of the sacrificial layer is 6-30 nm.

8. The metal oxide thin film transistor according to claim 1, wherein The active layer is a single-layer structure or a stacked structure.

9. The metal oxide thin film transistor according to claim 1, wherein The metal oxide thin film transistor comprises, from bottom to top, a substrate, a gate, a gate insulating layer, an active layer, a channel protection layer and a sacrificial layer; the metal oxide thin film transistor further comprises a source electrode and a drain electrode covering the sacrificial layer and electrically connected to both ends of the active layer; and the metal oxide thin film transistor further comprises a passivation layer covering the source electrode, the drain electrode and the channel protection layer.

10. The metal oxide thin film transistor according to claim 1, wherein The channel protection layer replaces the active layer in the metal oxide thin film transistor.

11. The metal oxide thin film transistor according to claim 1, wherein The metal oxide thin film transistor comprises, from bottom to top, a substrate, a gate, a gate insulating layer, a channel protection layer and a sacrificial layer; the metal oxide thin film transistor further comprises a source electrode and a drain electrode covering the sacrificial layer and electrically connected to both ends of the channel protection layer; and the metal oxide thin film transistor further comprises a passivation layer covering the source electrode, the drain electrode and the channel protection layer.

12. A method of manufacturing the metal oxide thin film transistor according to any one of claims 1 to 11, characterized by, The preparation method comprises sequentially depositing the channel protection layer and the sacrificial layer on the active layer and completing patterning in the same etching process.

13. The method of claim 12, wherein, The preparation method comprises the following steps: (1) forming and patterning a gate on a substrate; (2) covering and patterning a gate insulating layer on the gate; (3) sequentially depositing an active layer, a channel protection layer and a sacrificial layer on the gate insulating layer and completing patterning in the same etching process; (4) after forming a source electrode and a drain electrode electrically connected to both ends of the active layer on the sacrificial layer, etching is performed; in the process of etching the source and drain electrodes, the sacrificial layer not protected by the source and drain electrodes is etched at the same time; (5) forming a passivation layer on the source electrode, the drain electrode and the channel protection layer.

14. The method of claim 13, wherein, In the etching of step (4), the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is greater than 20:

1.

15. The preparation method according to claim 13, characterized in that, Before step (5) is performed, an etching process for etching the sacrificial layer is added.

16. The method of claim 15, wherein, In the etching of the sacrificial layer, the ratio of the etching rate of the sacrificial layer film to the etching rate of the protection layer film is greater than 20:

1.

17. The preparation method according to claim 15, characterized in that, After the etching of the sacrificial layer, an atmosphere heat treatment or a plasma treatment is performed.

18. The method of claim 17, wherein, The gas source for the plasma treatment includes any one of argon, nitrous oxide, oxygen, ozone, sulfur fluoride, carbon fluoride, or nitrogen, or a combination of at least two thereof.

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