A vertical structure tunnel junction gallium nitride light emitting diode and its preparation method

Abstract

The present invention discloses a vertical tunnel junction gallium nitride light-emitting diode and its preparation method. In this method, an epitaxial wafer containing a tunnel junction is first epitaxially grown. A p-type nitride layer in the tunnel junction is exposed to the environment by forming a trench. The p-type nitride layer in the tunnel junction is thermally activated, allowing hydrogen in the p-type nitride layer to diffuse into the environment through the trench, thereby achieving a higher hole concentration in the p-type nitride layer in the tunnel junction. Furthermore, the gallium nitride light-emitting diode containing the tunnel junction has a vertical structure, with a bottom metal reflector electrode located on the ridge of the trench and a top metal n-electrode positioned directly opposite the trench. This staggered electrode distribution design not only facilitates current expansion but also reduces light loss. The present invention can activate buried p-type nitride layers in large-scale tunnel junctions, facilitating the application of large-scale tunnel junction gallium nitride light-emitting diodes.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical structure tunnel junction gallium nitride light emitting diode and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN)-based light-emitting diodes have the advantages of high electro-optical conversion efficiency, energy saving, environmental protection, high brightness, and long service life. They are currently widely used in various lighting, display, decoration, indication and other fields.

[0003] The p-type nitride layer in traditional gallium nitride (GaN)-based light-emitting diodes uses Mg doping to provide holes. Due to the high ionization energy of Mg acceptors in nitride, less than 10% of the Mg acceptors are ionized. As a result, the hole concentration in the p-type nitride material is low, and the contact resistance between the p-type nitride layer and the electrode is large. This leads to high operating voltages and severe heat generation in the device, seriously affecting its performance and reliability.

[0004] Because ohmic contacts on p-type nitride layers are more difficult to prepare than those on n-type nitride layers, some have proposed epitaxially growing an n-type nitride layer on the p-type nitride layer, and fabricating the ohmic contact electrode originally prepared on the p-type nitride layer on the n-type nitride layer. A tunnel junction forms at the interface between the heavily doped p-type nitride and n-type nitride layers. When a GaN-based light-emitting diode is operating and a reverse bias is applied, electrons in the p-type nitride valence band tunnel into the n-type nitride conduction band, and the holes left in the p-type nitride valence band are injected into the active region.

[0005] Gallium nitride (GaN) light-emitting diodes (LEDs) with tunnel junctions are typically grown epitaxially using metal-organic chemical vapor deposition (MOCVD). During tunnel junction growth, a p-type nitride layer is first grown, followed by an n-type nitride layer. During growth, Mg acceptors are easily passivated by hydrogen in the growth atmosphere, forming Mg-H complexes in the p-type nitride layer, resulting in a high-resistance state. To obtain a p-type layer with a high hole concentration, thermal annealing or electron beam irradiation is required to break the Mg-H bonds, allowing hydrogen to diffuse and activate the Mg. However, the p-type nitride layer in the tunnel junction is surrounded by n-type nitride layers above and below. The large diffusion barrier for hydrogen in the n-type nitride layer hinders hydrogen diffusion, preventing effective activation of the p-type nitride layer in the tunnel junction. When growing a tunnel junction, even if the p-type nitride layer is activated before the n-type nitride layer is grown, as in CN 109616557 A, the hydrogen in the growth atmosphere will still re-passivate the activated Mg acceptors in the p-type nitride layer during the subsequent growth of the n-type nitride layer, resulting in a still-high resistance tunnel junction. Existing methods for activating tunnel junctions include "sidewall activation," which involves reducing device size or vertically drilling holes to allow hydrogen to diffuse laterally within the p-type nitride layer, escaping the p-type nitride layer through the sidewalls.

[0006] For large-area, high-power GaN LED applications, the devices are typically fabricated in flip-chip or vertical configurations to address current expansion and heat dissipation issues. However, in large-area flip-chip or vertical configurations, it is difficult to continue using the "sidewall activation" method to activate GaN LEDs containing tunnel junctions. This is because drilling holes not only reduces the device's light-emitting area, but the location of the holes may also affect device leakage. Summary of the Invention

[0007] A first object of the present invention is to provide a vertical tunnel junction gallium nitride light emitting diode.

[0008] A second objective of the present invention is to provide a method for preparing a vertical tunnel-junction gallium nitride light-emitting diode. This method employs a trench method to address the difficulty in activating the p-type nitride layer in large-sized tunnel-junction gallium nitride light-emitting diodes in the prior art. Furthermore, the specially designed arrangement of electrodes not only improves the current expansion of the device but also reduces light loss.

[0009] The first object of the present invention is specifically achieved in this way:

[0010] A vertical tunnel junction gallium nitride light-emitting diode is characterized by comprising, from bottom to top, a substrate, an adhesive layer, a metal reflector electrode layer, a first insulating dielectric layer, a first n-type nitride layer, a p-type nitride layer, an electron blocking layer, an active layer, a second n-type nitride layer, a second insulating dielectric layer, and a metal n-electrode. The first n-type nitride layer and the p-type nitride layer each comprise at least two nitride layers with different n-type doping concentrations and two nitride layers with different p-type doping concentrations, and a tunnel junction is formed at the interface between the first n-type nitride layer and the p-type nitride layer. The metal n-electrode is a gate line structure, with a trench correspondingly provided directly below each metal n-electrode, and the trench is filled with a first insulating dielectric layer having a first opening. The metal reflector electrode layer contacts the first n-type nitride layer through the first opening in the first insulating dielectric layer.

[0011] Preferably, the distance L between two adjacent metal n-electrodes is ≤ 200 μm.

[0012] Preferably, the trench is engraved through the first n-type nitride layer to the surface or interior of the p-type nitride layer, the width d of the trench is ≤ 20 μm, and the distance between two adjacent trenches is L.

[0013] Further preferably, the opening of the first insulating dielectric layer is located on a ridge between two trenches.

[0014] Preferably, the metal mirror electrode is on the ridge between the two grooves, and the metal n-electrode is located at the position of the groove, and the metal mirror electrode and the metal n-electrode form a staggered distribution.

[0015] The second object of the present invention is specifically achieved in this way:

[0016] A method for preparing a vertical structure tunnel junction gallium nitride light emitting diode is characterized by comprising the following steps:

[0017] Step S1, sequentially growing a nitride epitaxial wafer comprising a second n-type nitride layer, an active layer, an electron blocking layer, a p-type nitride layer and a first n-type nitride layer on a substrate;

[0018] Step S2, etching a groove on the surface of the nitride epitaxial wafer with a mask, wherein the groove penetrates the first n-type nitride layer and reaches the surface or the interior of the p-type nitride layer;

[0019] Step S3, performing heat treatment to activate the nitride epitaxial wafer with the grooves etched therein;

[0020] Step S4, performing surface cleaning on the activated nitride epitaxial wafer;

[0021] Step S5, depositing a first insulating dielectric layer on the first n-type nitride layer of the cleaned nitride epitaxial wafer, etching a first opening in the first insulating dielectric layer to allow the metal reflector electrode layer to contact the first n-type nitride layer, wherein the first opening is located on a ridge between the two trenches;

[0022] Step S6: forming a metal reflector electrode layer on the first insulating dielectric layer, wherein the metal reflector electrode layer contacts the first n-type nitride layer through the first opening;

[0023] Step S7, evaporating a bonding layer on the metal reflector electrode layer;

[0024] Step S8: bonding the substrate and the adhesive layer by a bonding method;

[0025] Step S9, removing the substrate of the nitride epitaxial wafer;

[0026] Step S10, removing edge materials of the nitride epitaxial wafer;

[0027] Step S11: depositing a second insulating dielectric layer around and on the surface of the GaN epitaxial wafer, and etching a second opening on the surface of the second insulating dielectric layer to allow the metal n-electrode to contact the second n-type nitride layer, with the second opening coinciding with the position of the underlying trench;

[0028] Step S12: A metal n-electrode is formed in the second opening.

[0029] The present invention has the following beneficial effects:

[0030] 1. A trench is etched on the nitride epitaxial wafer containing the tunnel junction to provide an escape channel for hydrogen activation and diffusion in the p-type nitride layer, enabling activation of the p-type nitride layer in large-scale tunnel junctions. This solves the problem that during the actual tunnel junction growth process, the p-type nitride layer is passivated again during the subsequent growth of the n-type nitride layer, resulting in the p-type nitride layer being covered by the subsequently grown n-type nitride layer, making it difficult for hydrogen to activate and diffuse.

[0031] 2. The metal reflector electrode in the present invention is on the ridge between the two grooves, and the metal n-electrode is located at the position of the groove. The metal reflector electrode and the metal n-electrode form a staggered distribution, which is conducive to the diffusion of current;

[0032] 3. The present invention adopts a vertical structure, and the positions of the metal n-electrode and the groove correspond to each other, which does not occupy the light-emitting area of ​​the device and reduces the light-emitting loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic diagram corresponding to step S1 in the preparation method provided by the present invention;

[0034] Figure 2This is a schematic diagram corresponding to step S2 in the preparation method provided by the present invention;

[0035] Figure 3 A top view of the groove distribution in the preparation method provided by the present invention;

[0036] Figure 4 This is a schematic diagram corresponding to step S5 in the preparation method provided by the present invention;

[0037] Figure 5 This is a schematic diagram corresponding to step S6 in the preparation method provided by the present invention;

[0038] Figure 6 This is a schematic diagram corresponding to step S7 in the preparation method provided by the present invention;

[0039] Figure 7 This is a schematic diagram corresponding to step S8 in the preparation method provided by the present invention;

[0040] Figure 8 This is a schematic diagram corresponding to step S9 in the preparation method provided by the present invention;

[0041] Figure 9 This is a schematic diagram corresponding to step S10 in the preparation method provided by the present invention;

[0042] Figure 10 This is a schematic diagram corresponding to step S11 in the preparation method provided by the present invention;

[0043] Figure 11 This is a schematic diagram corresponding to step S12 in the preparation method provided by the present invention;

[0044] Figure 12 A top view of the distribution of the metal n-electrode in the preparation method provided by the present invention;

[0045] Description of Reference Numerals

[0046] Substrate 101, second n-type nitride layer 102, active layer 103, electron blocking layer 104, p-type nitride layer 105, p-type lightly doped nitride layer 1051, p-type heavily doped nitride layer 1052, first n-type nitride layer 106, n-type heavily doped nitride layer 1061, n-type lightly doped nitride layer 1062, first insulating dielectric layer 107, metal mirror electrode layer 108, bonding layer 109, substrate 110, second insulating dielectric layer 111, metal n-electrode 112, trench 113, first opening 114, second opening 115. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, a detailed description will be given below with reference to specific embodiments.

[0048] Example 1:

[0049] A method for preparing a vertical tunnel junction gallium nitride light-emitting diode comprises the following steps:

[0050] Step S1: epitaxially grow a second n-type nitride layer 102, an active layer 103, an electron blocking layer 104, a p-type lightly doped nitride layer 1051, a p-type heavily doped nitride layer 1052, an n-type heavily doped nitride layer 1061, and an n-type lightly doped nitride layer 1062 on a silicon substrate 101 by metal organic chemical vapor deposition (MOCVD). The entire nitride epitaxial wafer structure is as follows: Figure 1 As shown;

[0051] Step S2: A groove 113 is formed on the nitride epitaxial wafer by photolithography plus ICP etching. The depth of the groove 113 is greater than the thickness of the first n-type nitride layer 106. The groove 113 reaches the surface or the inner layer of the p-type nitride layer 105. Figure 2 As shown; Figure 3 This is a top view of the distribution of the grooves 113. The width of the grooves 113 is 5 μm, and the distance between two adjacent grooves 113 is 150 μm.

[0052] Step S3: Place the nitride epitaxial wafer with the grooves 113 etched therein into a rapid annealing furnace and perform high-temperature activation in a nitrogen atmosphere at 800° C. for 20 minutes. During this activation process, hydrogen in the p-type nitride layer 105 can diffuse into the grooves 113 and be released into the environment, thereby activating the p-type nitride layer 105.

[0053] Step S4: cleaning the surface of the activated epitaxial wafer by first using a mixture of sulfuric acid and hydrogen peroxide to remove organic matter from the surface of the activated epitaxial wafer, and then using dilute hydrochloric acid to remove metal impurities from the surface of the activated epitaxial wafer;

[0054] Step S5: Using PECVD to deposit a first insulating dielectric layer 107 on the cleaned nitride epitaxial wafer, and then etching through photolithography, development, and etching to form a first opening 114 on the first insulating dielectric layer 107 for the metal reflector electrode layer 108 to contact the first n-type nitride layer 106, as shown in FIG. Figure 4 As shown, the first opening 114 is prepared on the ridge of the groove 113 in order to form a misalignment with the metal n-electrode 112, which is beneficial to the expansion of the current;

[0055] Step S6: evaporate a metal reflector electrode layer 108 on the first insulating dielectric layer 107. The metal reflector electrode layer 108 contacts the n-type nitride layer 106 through the first opening 114 and serves as an electrode. Figure 5 As shown;

[0056] Step S7: Evaporating a bonding layer 109 on the metal reflector electrode layer 108, such as Figure 6 As shown;

[0057] Step S8: Bond the substrate 110 and the adhesive layer 109 by bonding. Figure 7 As shown;

[0058] Step S9: remove the Si substrate 101 by wet etching process. Figure 8 As shown;

[0059] Step S10: remove the second n-type nitride layer 102, the active layer 103, the electron blocking layer 104, the p-type nitride layer 105 and the side of the first n-type nitride layer 106. Figure 9 As shown;

[0060] Step S11: using PECVD to deposit a second insulating dielectric layer 111 on the surface of the second n-type nitride layer 102, the active layer 103, the electron blocking layer 104, the p-type nitride layer 105, the first n-type nitride layer 106, and the second n-type nitride layer 102, and etching a second opening 115 on the surface of the second insulating dielectric layer 111 to allow the metal n-electrode 112 to contact the second n-type nitride layer 102, as shown in FIG. Figure 10 As shown, the second opening 115 is prepared right above the groove 113 in order to make the metal n-electrode 112 and the groove 113 overlap and reduce light loss;

[0061] Step S12: The metal n-electrode 112 is formed at the second opening 115. Figure 11 As shown; Figure 12 It is a top view of the metal n-electrode 112. The distance between two adjacent metal n-electrodes 112 is 150 μm. The metal n-electrode 112 and the metal reflector electrode layer 108 are misaligned, which is beneficial to the lateral expansion of the current when the device is working.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A vertical tunnel junction gallium nitride light emitting diode, characterized by: The invention comprises, from bottom to top, a substrate, an adhesive layer, a metal reflector electrode layer, a first insulating dielectric layer, a first n-type nitride layer, a p-type nitride layer, an electron blocking layer, an active layer, a second n-type nitride layer, a second insulating dielectric layer, and a metal n-electrode; characterized in that: the first n-type nitride layer and the p-type nitride layer each comprise at least two nitride layers with different n-type doping concentrations and two nitride layers with different p-type doping concentrations, and a tunnel junction is formed at the interface between the first n-type nitride layer and the p-type nitride layer; the metal n-electrode is a gate line structure, with a trench corresponding to each metal n-electrode directly below, and the trench is filled with a first insulating dielectric layer having a first opening; the metal reflector electrode layer contacts the first n-type nitride layer through the first opening in the first insulating dielectric layer; The trench is carved through the first n-type nitride layer to the surface or the interior of the p-type nitride layer, the width d of the trench is ≤ 20 μm, and the distance between two adjacent trenches is L; The opening of the first insulating dielectric layer is located on the ridge between the two trenches.

2. The vertical tunnel junction gallium nitride light emitting diode according to claim 1, characterized in that: The distance L between two adjacent metal n-electrodes is ≤ 200 μm.

3. The vertical tunnel junction gallium nitride light emitting diode according to claim 1, characterized in that: The metal reflector electrode is on the ridge between the two grooves, the metal n-electrode is at the position of the groove, and the metal reflector electrode and the metal n-electrode form a staggered distribution.

4. A method for preparing a vertical tunnel junction gallium nitride light-emitting diode according to claim 1, characterized by comprising the following steps: Step S1, sequentially growing a nitride epitaxial wafer comprising a second n-type nitride layer, an active layer, an electron blocking layer, a p-type nitride layer and a first n-type nitride layer on a substrate; Step S2, etching a groove on the surface of the nitride epitaxial wafer with a mask, wherein the groove penetrates the first n-type nitride layer and reaches the surface or the interior of the p-type nitride layer; Step S3, performing heat treatment to activate the nitride epitaxial wafer with the grooves etched therein; Step S4, performing surface cleaning on the activated nitride epitaxial wafer; Step S5, depositing a first insulating dielectric layer on the first n-type nitride layer of the cleaned nitride epitaxial wafer, etching a first opening in the first insulating dielectric layer to allow the metal reflector electrode layer to contact the first n-type nitride layer, wherein the first opening is located on a ridge between the two trenches; Step S6: forming a metal reflector electrode layer on the first insulating dielectric layer, wherein the metal reflector electrode layer contacts the first n-type nitride layer through the first opening to form a lower electrode; Step S7, evaporating a bonding layer on the metal reflector electrode layer; Step S8: bonding the substrate and the adhesive layer by a bonding method; Step S9, removing the substrate of the nitride epitaxial wafer; Step S10, removing edge materials of the nitride epitaxial wafer; Step S11: depositing a second insulating dielectric layer around and on the surface of the gallium nitride epitaxial wafer, and etching a second opening on the surface of the second insulating dielectric layer to allow the metal n-electrode to contact the second n-type nitride layer; Step S12: preparing a metal n-electrode.

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