An all-integrated drive chip architecture based on current slope detection, electronic device

Abstract

The application provides a full-integrated driving chip architecture based on current slope detection, and an electronic device, which are used for driving a first power tube; the architecture comprises a feedback unit for feedback voltage division of an induced voltage of the first power tube; a control unit for providing a control signal; an integrated driving unit comprising an opening three-stage driving branch and a closing three-stage driving branch; the opening three-stage driving branch is used for comparing the induced voltage with a first reference voltage and outputting a first driving current to a third driving current to a gate of the first power tube for stage-by-stage opening of the first power tube to simultaneously optimize opening loss and peak current of the first power tube; and the closing three-stage driving branch is used for comparing the induced voltage with a second reference voltage and outputting a fourth driving current to a sixth driving current to the gate of the first power tube for stage-by-stage closing of the first power tube to simultaneously optimize closing loss and peak voltage of the first power tube.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide driving, and more particularly to a fully integrated driving chip architecture and electronic device based on current slope detection. Background Technology

[0002] With the development of wide-bandgap devices, SiC MOSFETs have seen rapid development and application in recent years due to their faster switching speed and frequency compared to Si IGBTs, effectively improving power system efficiency. However, the excessively fast switching speed also introduces voltage and current spikes into SiC MOSFETs. Traditional drive circuits struggle to simultaneously optimize both voltage and current spikes and switching losses. Therefore, a multi-stage drive circuit is needed to control the drive current at different stages of the SiC MOSFET's driving process. The drive current is reduced during stages with voltage and current spikes and increased during other stages, thus optimizing both voltage and current spikes and switching losses during the SiC MOSFET's driving process.

[0003] Please refer to Figure 1 Existing multi-segment drive circuits consist of an off-chip FPGA and a digitally programmable driver chip. Since the programmable driver chip can control a large number of segments within a single switching cycle, the FPGA needs to generate control clock signals, segment number signals, and control switching signals for these segments. Therefore, the overall control delay of existing multi-segment drive circuits is determined by the FPGA's control frequency, which is typically between 100 and 300 MHz. This makes existing technology unsuitable for SiC MOSFETs with control delays in the tens of nanosecond range. Furthermore, to achieve multi-segment control, the digital control within the digitally programmable driver chip requires numerous level shifting circuits, multi-segment triggering circuits, and encoding / decoding circuits. This large-scale digital circuitry leads to longer control delays and higher circuit costs, further hindering the reduction of control delays for SiC MOSFETs. Summary of the Invention

[0004] This invention provides a fully integrated driver chip architecture and electronic device based on current slope detection, which simultaneously optimizes the voltage and current spike problems and switching loss problems of SiC MOSFETs through a low-latency and low-cost solution.

[0005] According to a first aspect of the present invention, a fully integrated driver chip architecture based on current slope detection is provided for driving a first power transistor, wherein a first terminal of the first power transistor is coupled to ground, and a second terminal of the first power transistor is connected to a load power supply terminal through a load unit; the architecture includes:

[0006] The feedback unit includes a feedback inductor and a voltage divider branch. A first terminal of the feedback inductor is coupled to a first terminal of the first power transistor, and a second terminal is coupled to the input terminal of the voltage divider branch. The feedback inductor generates a first induced voltage and outputs it to the voltage divider branch. The voltage divider branch is coupled to the load unit and divides the first induced voltage, outputting a first feedback voltage. The first feedback voltage characterizes the changes in peak current and peak voltage caused by the change in current slope during the turn-on and turn-off processes of the first power transistor.

[0007] A control unit, used to output a control signal based on an input level;

[0008] An integrated drive unit includes a three-stage turn-on drive branch and a three-stage turn-off drive branch; the three-stage turn-on drive branch includes a positive current slope detection component and a three-stage turn-on processing circuit; the three-stage turn-off drive branch includes a negative current slope detection component and a three-stage turn-off processing circuit; wherein:

[0009] The positive current slope detection component is coupled to the output terminal of the voltage divider branch. It is used to receive the first feedback voltage, compare the first feedback voltage with a first reference voltage, and output a first turn-on level signal.

[0010] The three-stage turn-on processing circuit is coupled to the control unit, the positive current slope detection component, and the gate of the first power transistor, respectively. It is used to receive the first turn-on level signal and the control signal, and to form a first drive current, a second drive current, and a third drive current based on the first turn-on level signal and the control signal, and output them to the gate of the first power transistor. The first drive current, the second drive current, and the third drive current are used to sequentially control the turn-on of the first power transistor in different turn-on stages.

[0011] The negative current slope detection component is coupled to the output terminal of the voltage divider branch. It is used to receive the first feedback voltage, compare the first feedback voltage with a second reference voltage, and output a first turn-off level signal.

[0012] The three-stage shutdown processing circuit is coupled to the control unit, the negative current slope detection component, and the gate of the first power transistor, respectively. It is used to receive the first shutdown level signal and the control signal, and to form a fourth drive current, a fifth drive current, and a sixth drive current based on the first shutdown level signal and the control signal, and output them to the gate of the first power transistor. The fourth drive current, the fifth drive current, and the sixth drive current are used to sequentially control the shutdown of the first power transistor in different shutdown stages.

[0013] Furthermore, the three-stage drive branch for opening and the three-stage drive branch for shutting down are both integrated into the same chip.

[0014] Optionally, the three-stage activation processing circuit includes a level shifting circuit and a three-stage activation push-pull circuit;

[0015] The level shifting circuit is coupled to the output terminal of the positive current slope detection component, the output terminal of the control unit, and the input terminal of the three-stage push-pull circuit. The level shifting circuit is used to receive the first turn-on level signal and the control signal, and after level shifting the first turn-on level signal and the control signal respectively, output the corresponding first turn-on signal and second turn-on signal respectively.

[0016] The output terminal of the three-stage push-pull circuit is coupled to the gate of the first power transistor; the three-stage push-pull circuit is used to receive the first turn-on signal and the second turn-on signal, and output the first drive current, the second drive current and the third drive current to the outside in sequence according to the first turn-on signal and the second turn-on signal.

[0017] Optionally, the three-stage shutdown processing circuit includes a first inverter and a three-stage shutdown push-pull circuit.

[0018] The input and output terminals of the first inverter are respectively coupled to the output terminal of the control unit and the input terminal of the three-stage push-pull shutdown circuit; the first inverter is used to invert the control signal to obtain a second shutdown level signal and output it to the three-stage push-pull shutdown circuit.

[0019] The output terminal of the three-stage push-pull circuit is coupled to the gate of the first power transistor, and its input terminal is also coupled to the output terminal of the negative current slope detection component. The three-stage push-pull circuit is used to receive the first turn-off level signal and the second turn-off level signal, and output the fourth drive current, the fifth drive current and the sixth drive current in sequence according to the first turn-off level signal and the second turn-off level signal.

[0020] Optionally, the positive current slope detection component includes a first comparator.

[0021] Optionally, the negative current slope detection component includes a second comparator.

[0022] Optionally, the three-stage push-pull circuit includes a first-stage push-pull branch and a second-stage push-pull branch.

[0023] The first-stage turn-on push-pull branch includes a first-stage push-pull circuit and a first MOSFET; the input terminal of the first-stage push-pull circuit is coupled to the output terminal of the level shift circuit, and its output terminal is coupled to the gate of the first MOSFET; the second terminal of the first MOSFET is coupled to the gate of the first power transistor; the first-stage push-pull circuit is used to receive the first turn-on signal, and output the first turn-on signal to the gate of the first MOSFET after push-pull processing; the first MOSFET is used to output a first current or not output current under the action of the first turn-on signal after push-pull processing.

[0024] The second-stage turn-on push-pull branch includes a second-stage push-pull circuit and a second MOSFET; the input terminal of the second-stage push-pull circuit is coupled to the output terminal of the level shift circuit, and its output terminal is coupled to the gate of the second MOSFET; the second terminal of the second MOSFET is coupled to the gate of the first power transistor; the second-stage push-pull circuit is used to receive the second turn-on signal, and output the second turn-on signal to the gate of the second MOSFET after push-pull processing; the second MOSFET is used to output a second current under the action of the second turn-on signal after push-pull processing.

[0025] Wherein, the first driving current is composed of the first current and the second current; the second driving current is composed of the second current; and the third driving current is composed of the first current and the second current.

[0026] Optionally, the three-stage turn-off push-pull circuit includes a first-stage turn-off push-pull branch and a second-stage turn-off push-pull branch.

[0027] The first-stage turn-off push-pull branch includes a third-stage push-pull circuit and a third MOSFET; the input terminal of the third-stage push-pull circuit is coupled to the output terminal of the first inverter, and its output terminal is coupled to the gate of the third MOSFET; the second terminal of the third MOSFET is coupled to the gate of the first power transistor; the third-stage push-pull circuit is used to receive the first turn-off level signal, and output the first turn-off signal to the gate of the third MOSFET after push-pull processing; the third MOSFET is used to output the third current or not output it under the action of the first turn-off signal after push-pull processing.

[0028] The second-stage turn-off push-pull branch includes a fourth-stage push-pull circuit and a fourth MOSFET; the input terminal of the fourth-stage push-pull circuit is coupled to the output terminal of the first inverter, and its output terminal is coupled to the gate of the fourth MOSFET; the second terminal of the fourth MOSFET is coupled to the gate of the first power transistor; the fourth-stage push-pull circuit is used to receive the second turn-off level signal, and outputs the second turn-off level signal to the gate of the fourth MOSFET after push-pull processing; the fourth MOSFET is used to output the fourth drive current under the action of the second turn-off level signal after push-pull processing.

[0029] The fourth driving current is composed of the third current and the fourth current; the fifth driving current is composed of the fourth current; and the sixth driving current is composed of the third current and the fourth current.

[0030] Optionally, both the first-stage push-pull circuit and the second-stage push-pull circuit are composed of five inverters connected in series.

[0031] Optionally, both the third-stage push-pull circuit and the fourth-stage push-pull circuit are composed of six inverters connected in series.

[0032] Optionally, both the first MOSFET and the second MOSFET are PLDMOS transistors.

[0033] Optionally, the third MOS transistor and the fourth MOS transistor are both NLDMOS transistors.

[0034] Optionally, the voltage divider branch includes a first voltage divider resistor and a second voltage divider resistor;

[0035] The first end of the first voltage divider resistor serves as the input end of the voltage divider branch to receive the first induced voltage, and its second end serves as the output end of the voltage divider branch to output the first feedback voltage. Its second end is also connected to the first end of the second feedback resistor.

[0036] The first terminal of the second voltage divider resistor is connected to a first negative voltage source.

[0037] Optionally, the load unit includes a second power transistor, a load inductor, a load capacitor, a first constant voltage source, and a second constant voltage source;

[0038] The second terminal of the first constant voltage source is connected to the gate of the second power transistor, and its first terminal is connected to the second terminal of the load inductor.

[0039] The first terminal of the second power transistor is coupled to the second terminal of the first power transistor and the second terminal of the load inductor, respectively.

[0040] The second terminal of the second power transistor, the first terminal of the load inductor, the first terminal of the load capacitor, and the first terminal of the second constant voltage source are all connected to the load power supply terminal;

[0041] The second terminal of the load capacitor and the second terminal of the second constant voltage source are both connected to the input terminal of the voltage divider branch.

[0042] Optionally, the second power transistor may be an NMOS transistor.

[0043] Optionally, the first power transistor is a silicon carbide single transistor.

[0044] Optionally, the feedback inductor is the drain-source parasitic inductance of the first power transistor.

[0045] According to a second aspect of the present invention, an electronic device is provided, comprising the fully integrated driver chip architecture based on current slope detection provided by the first aspect and alternative solutions of the present invention.

[0046] The fully integrated driver chip architecture based on current slope detection provided by this invention simulates and integrates the driving circuit composed of an off-chip FPGA and a digitally programmable driver chip in the prior art to form a fully integrated driver chip. It also integrates positive and negative current slope detection circuits inside the chip and adds a feedback unit outside the chip to feed back the leakage inductance voltage of the first power transistor. This chip solves the delay and circuit complexity problems caused by the low control frequency of the off-chip FPGA and the large scale of the digital circuit inside the digitally programmable driver chip. Compared with the open-loop control scheme of the prior art, this invention can perform adaptive control according to the different operating states of the first power transistor and has better control effect. Attached Figure Description

[0047] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0048] Figure 1 This is a schematic diagram of the structure of a multi-segment drive circuit in the prior art;

[0049] Figure 2 This is the circuit structure block diagram of the fully integrated driver chip architecture based on current slope detection provided in the embodiments of the present invention. Figure 1 ;

[0050] Figure 3 This is the circuit structure block diagram of the fully integrated driver chip architecture based on current slope detection provided in the embodiments of the present invention. Figure 2 ;

[0051] Figure 4 This is a circuit structure diagram of the level shifting circuit provided in an embodiment of the present invention;

[0052] Figure 5 This is a circuit structure diagram of the three-segment push-pull circuit provided in the embodiment of the present invention;

[0053] Figure 6 This is a circuit structure diagram of the three-stage push-pull circuit for shutdown provided in an embodiment of the present invention;

[0054] Figure 7 This is the circuit structure block diagram of the fully integrated driver chip architecture based on current slope detection provided in the embodiments of the present invention. Figure 3 ;

[0055] Figure 8 This is the circuit structure block diagram of the fully integrated driver chip architecture based on current slope detection provided in the embodiments of the present invention. Figure 4 ;

[0056] Figure 9 This is a timing diagram of turning on and off the first power transistor according to an embodiment of the present invention. Attached image description:

[0058] 10-Feedback Unit:

[0059] 11-Voltage divider branch;

[0060] 20 - Control Unit;

[0061] 30 - Integrated drive unit;

[0062] 31- Open the three-stage drive branch;

[0063] 32-Shut down the three-stage drive branch;

[0064] 311-Positive current slope detection component;

[0065] 312 - Enable the three-stage processing circuit;

[0066] 3121 - Level shifting circuit;

[0067] 3122 - Enable three-stage push-pull circuit;

[0068] 31221 - First-level opening of push-pull branch road;

[0069] 312211 - First-stage push-pull circuit;

[0070] 31222 - Second-level opening of push-pull branch road;

[0071] 312221 - Second-stage push-pull circuit;

[0072] 321 - Negative Current Slope Detection Component;

[0073] 322 - Shutdown three-stage processing circuit;

[0074] 3221 - Turn off three-stage push-pull circuit;

[0075] 32211 - First-level shut-off push-pull branch;

[0076] 322111 - Third-stage push-pull circuit;

[0077] 32212 - Second-level shut-off push-pull branch;

[0078] 322121 - Fourth-stage push-pull circuit;

[0079] 40-Load Unit;

[0080] VDC - Power supply terminal;

[0081] Vfb - First feedback voltage;

[0082] Vref1 - First reference voltage;

[0083] Vref2-;

[0084] VA - First Constant Voltage Source;

[0085] IG1 - First drive current;

[0086] IG2 - Second drive current;

[0087] IG3 - Third drive current;

[0088] IG4 - Fourth drive current;

[0089] IG5 - Fifth drive current;

[0090] IG6 - Sixth drive current;

[0091] IP1 - First Current;

[0092] IP2 - Second Current;

[0093] IN1 - Third current;

[0094] IN2 - Fourth current;

[0095] R1 - First voltage divider resistor;

[0096] R2 - Second voltage divider resistor;

[0097] LKS - Feedback Inductor;

[0098] PWM - control signal;

[0099] CP1 - First comparator;

[0100] CP2 - Second comparator;

[0101] D1 - First inverter;

[0102] ON1 - First turn-on level signal;

[0103] Son1 - First activation signal;

[0104] Son2 - Second activation signal;

[0105] OFF1 - First shutdown level signal;

[0106] OFF2 - Second shutdown level signal;

[0107] H1 - First power transistor;

[0108] H2 - Second power transistor;

[0109] Lp - Load inductance;

[0110] CDC - Load capacitor;

[0111] V1 - First constant pressure source. Detailed Implementation

[0112] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0113] Before describing the embodiments of the present invention, the design concept of the present invention will be briefly introduced as follows:

[0114] Excessive switching speed in SiC MOSFETs leads to excessively high voltage and current spikes, which undoubtedly increases the voltage and current stress during operation and reduces the reliability of SiC MOSFETs in long-term operation. Conversely, overly conservative consideration of the operating stress of SiC MOSFETs will significantly limit their power output and increase drive losses. Therefore, it is necessary to optimize both the voltage and current spikes and the switching losses of SiC MOSFETs. Since current and voltage spikes only occur in specific stages of SiC MOSFET turn-on and turn-off, it is necessary to differentiate between these stages. A slower switching speed should be used during the current and voltage spike stages, while a faster switching speed should be maintained in other stages. Furthermore, since the switching speed of SiC MOSFETs is positively correlated with the drive current, a smaller drive current should be used during the current and voltage spike stages, while a larger drive current should be maintained in other stages. This approach suppresses drive spike levels while maintaining low switching losses. To achieve this multi-stage drive, the feedback and detection circuits need to be able to detect in a timely manner the stages when current and voltage spikes occur in the SiC MOSFET during switching, as well as the stages when current and voltage spikes do not occur. The subsequent logic control and adjustment circuits then adjust the output magnitude of the drive current accordingly. Therefore, reducing the feedback control delay is crucial. To reduce the feedback control delay, the detection circuit, logic control circuit, and subsequent adjustment circuit of this invention are all integrated into a single chip using analog circuitry, thereby minimizing the feedback control delay.

[0115] Please refer to Figure 2 Based on the above design concept, this embodiment of the invention provides a fully integrated driver chip architecture based on current slope detection for driving a first power transistor H1. The first end of the first power transistor H1 is coupled to ground, and the second end of the first power transistor H1 is connected to the load power supply terminal through a load unit 40. This fully integrated driver chip architecture based on current slope detection includes:

[0116] Feedback unit 10 includes a feedback inductor LKS and a voltage divider branch 11. The first terminal of the feedback inductor LKS is coupled to the first terminal of the first power transistor H1, and its second terminal is coupled to the input terminal of the voltage divider branch 11. The feedback inductor LKS generates a first induced voltage and outputs it to the voltage divider branch 11. The voltage divider branch 11 is coupled to the load unit 40 and divides the first induced voltage, outputting a first feedback voltage Vfb. The first feedback voltage Vfb characterizes the changes in peak current and peak voltage caused by the change in current slope during the turn-on and turn-off processes of the first power transistor H1. The principle behind the changes in peak current and peak voltage caused by the change in current slope during the turn-on and turn-off processes of the first feedback voltage Vfb is as follows: The formulas for the peak current and peak voltage generated by the first power transistor H1 during the turn-on and turn-off processes are as follows:

[0117]

[0118] Where Ios is used to characterize the peak current; Vos is used to characterize the peak current; C oss Used to characterize the output capacitance of the first power transistor H1; Q rr Used to characterize the reverse recovery charge of the body diode of the first power transistor H1; L loop Parasitic inductance used to characterize power circuits.

[0119] The formula for the first feedback voltage Vfb is:

[0120]

[0121] Wherein Vfb is used to characterize the first feedback voltage Vfb; R1 and R2 are used to characterize the voltage dividing resistors in the voltage dividing branch 11; Vks is used to characterize the first induced voltage; Lks is used to characterize the feedback inductor LKS; VA is used to characterize a first constant voltage source. Specifically, in this embodiment of the invention, the first constant voltage source VA is selected as 5V to reduce the magnitude of the feedback voltage. Of course, the magnitude of the first constant voltage source VA can also be adjusted according to actual needs, and is not limited here.

[0122] As can be seen from the above formula, both the peak voltage and peak current are related to the current slope of the first power transistor H1 during the turn-on and turn-off processes. Therefore, changes in the current slope will alter the magnitude of the peak voltage and peak current. At the same time, the first feedback voltage Vfb is also related to the current slope. Therefore, the first feedback voltage Vfb can be used to characterize the changes in peak current and peak voltage caused by changes in the current slope during the turn-on and turn-off processes of the first power transistor H1.

[0123] Control unit 20 is used to output a control signal PWM based on an input level;

[0124] The integrated drive unit 30 includes an on-state three-stage drive branch 31 and an off-state three-stage drive branch 32; the on-state three-stage drive branch 31 includes a positive current slope detection component 311 and an on-state three-stage processing circuit 312; the off-state three-stage drive branch 32 includes a negative current slope detection component 321 and an off-state three-stage processing circuit 322; wherein:

[0125] The positive current slope detection component 311 is coupled to the output terminal of the voltage divider branch 11. It is used to receive the first feedback voltage Vfb, compare the first feedback voltage Vfb with a first reference voltage Vref1, and output a first turn-on level signal ON1. Specifically, the positive current slope detection component 311 includes a first comparator CP1. The non-inverting input terminal of the first comparator CP1 receives the first feedback voltage Vfb, and the inverting input terminal of the first comparator CP1 receives the first reference voltage Vref1. The first reference voltage Vref1 is output by a second constant voltage source. The first reference voltage Vref1 is 0.5V-1V lower than 1 / A of the first constant voltage source VA. Of course, how much the first reference voltage Vref1 is lower than 1 / A of the first constant voltage source VA can be adjusted according to actual needs and is not limited here.

[0126] Where 1 / A equals

[0127] The three-stage turn-on processing circuit 312 is coupled to the control unit 20, the positive current slope detection component 311, and the gate of the first power transistor H1. It receives the first turn-on level signal ON1 and the control signal PWM, and generates a first drive current IG1, a second drive current IG2, and a third drive current IG3 based on the first turn-on level signal ON1 and the control signal PWM. These are then output to the gate of the first power transistor H1. The first drive current IG1, the second drive current IG2, and the third drive current IG3 are used to sequentially control the turn-on of the first power transistor H1 at different turn-on stages. Specifically, the first drive current IG1 and the third drive current IG3 are both large currents, while the second drive current IG2 is a small current. Specifically, the range of the first drive current IG1 is 1-1.5A; the range of the second drive current IG2 is 0.5-1A; and the range of the third drive current IG3 is 1-1.5A. Of course, the above current data are only experimental data from this embodiment of the invention, and the specific range may change depending on the actual application environment, which is not limited here.

[0128] The negative current slope detection component 321 is coupled to the output terminal of the voltage divider branch 11. It is used to receive the first feedback voltage Vfb, compare the first feedback voltage Vfb with a second reference voltage, and output a first turn-off level signal OFF1. Specifically, the negative current slope detection component 321 includes a second comparator CP2. The inverting input terminal of the second comparator CP2 receives the first feedback voltage Vfb, and the non-inverting input terminal of the second comparator CP2 receives the first reference voltage Vref1. The second reference voltage is output through a third constant voltage source. The second reference voltage is 0.5V-1V higher than 1 / A of the first constant voltage source VA. Of course, how much higher the second reference voltage is than 1 / A of the first constant voltage source VA can be adjusted according to actual needs and is not limited here.

[0129] The three-stage turn-off processing circuit 322 is coupled to the control unit 20, the negative current slope detection component 321, and the gate of the first power transistor H1. It receives the first turn-off level signal OFF1 and the control signal PWM, and generates a fourth drive current IG4, a fifth drive current IG5, and a sixth drive current IG6 based on the first turn-off level signal OFF1 and the control signal PWM. These are then output to the gate of the first power transistor H1. The fourth drive current IG4, the fifth drive current IG5, and the sixth drive current IG6 are used to sequentially control the turn-off of the first power transistor H1 at different turn-off stages. Specifically, the fourth drive current IG4 and the sixth drive current IG6 are both large currents, while the fifth drive current IG5 is a small current. Specifically, the range of the fourth drive current IG4 is 1-1.5A; the range of the fifth drive current IG5 is 0.5-1A; and the range of the sixth drive current IG6 is 1-1.5A. Of course, the above current data are only experimental data from this embodiment of the invention, and the specific range may change depending on the actual application environment, which is not limited here.

[0130] Furthermore, the three-stage drive branch 31 for opening and the three-stage drive branch 32 for closing are both integrated into the same chip.

[0131] In one specific implementation, the first power transistor H1 is a silicon carbide single transistor.

[0132] In one specific implementation, the feedback inductor LKS is the drain-source parasitic inductance of the first power transistor H1.

[0133] Please refer to Figure 3 In one specific implementation, the three-stage activation processing circuit 312 includes a level shifting circuit 3121 and a three-stage activation push-pull circuit 3122.

[0134] The level shifting circuit 3121 is coupled to the output terminal of the positive current slope detection component 311, the output terminal of the control unit 20, and the input terminal of the three-stage push-pull circuit 3122. The level shifting circuit 3121 receives the first turn-on level signal ON1 and the control signal PWM, and after level shifting the first turn-on level signal ON1 and the control signal PWM, outputs the corresponding first turn-on signal Son1 and second turn-on signal Son2. Specifically, the level shifting circuit 3121 shifts the level range of the first turn-on level signal ON1 and the control signal PWM from -5V-0V to 10V-15V. The total voltage drop across the circuit remains unchanged; only the reference voltage is increased, which helps drive the subsequent three-stage push-pull circuit 3122. Of course, the level range and its variation can be adjusted according to different application scenarios, and are not limited here. Please refer to [reference needed]. Figure 4 The level shifting circuit 3121 specifically includes: a first level shifting unit and a second level shifting unit; the first level shifting unit is used to level shift the first turn-on level signal ON1 and output the first turn-on signal Son1; the second level shifting unit is used to level shift the control signal PWM and output the second turn-on signal Son2; the specific structure of both the first level shifting unit and the second level shifting unit includes: two PMOS transistors, two capacitors, and one inverter;

[0135] The output terminal of the three-stage push-pull circuit 3122 is coupled to the gate of the first power transistor H1. The three-stage push-pull circuit 3122 receives the first turn-on signal Son1 and the second turn-on signal Son2, and sequentially outputs the first drive current IG1, the second drive current IG2, and the third drive current IG3 according to the first turn-on signal Son1 and the second turn-on signal Son2. Please refer to [reference needed]. Figure 5 The three-stage push-pull circuit 3122 specifically includes: a first-stage push-pull branch 31221 and a second-stage push-pull branch 31222.

[0136] The first-stage push-pull branch 31221 includes a first-stage push-pull circuit 312211 and a first MOSFET; the input terminal of the first-stage push-pull circuit 312211 is coupled to the output terminal of the level shift circuit 3121, and its output terminal is coupled to the gate of the first MOSFET; the second terminal of the first MOSFET is coupled to the gate of the first power transistor H1; the first-stage push-pull circuit 312211 is used to receive the first turn-on signal Son1, and output the first turn-on signal Son1 to the gate of the first MOSFET after push-pull processing; the first MOSFET is used to output a first current IP1 or not output under the action of the first turn-on signal Son1 after push-pull processing.

[0137] The second-stage push-pull branch 31222 includes a second-stage push-pull circuit 312221 and a second MOSFET; the input terminal of the second-stage push-pull circuit 312221 is coupled to the output terminal of the level shift circuit 3121, and its output terminal is coupled to the gate of the second MOSFET; the second terminal of the second MOSFET is coupled to the gate of the first power transistor H1; the second-stage push-pull circuit 312221 is used to receive the second turn-on signal Son2, and output the second turn-on signal Son2 to the gate of the second MOSFET after push-pull processing; the second MOSFET is used to output a second current IP2 under the action of the second turn-on signal Son2 after push-pull processing;

[0138] Wherein, the first driving current IG1 is composed of the first current IP1 and the second current IP2; the second driving current IG2 is composed of the second current IP2; and the third driving current IG3 is composed of the first current IP1 and the second current IP2.

[0139] In a preferred embodiment, both the first-stage push-pull circuit 312211 and the second-stage push-pull circuit 312221 are composed of five inverters connected in series; each inverter is a CMOS inverter. Both the first-stage push-pull circuit 312211 and the second-stage push-pull circuit 312221 are used to improve the current driving capability. The principle is that the larger the size of the CMOS inverter, the greater its current driving capability. In this embodiment, the size of each CMOS inverter in the push-pull circuit increases progressively, so each time the CMOS inverter flips the input level, it improves the current driving capability.

[0140] Please refer to Figure 3 In one specific implementation, the three-stage shutdown processing circuit 322 includes a first inverter D1 and a three-stage shutdown push-pull circuit 3221.

[0141] The input and output terminals of the first inverter D1 are respectively coupled to the output terminal of the control unit 20 and the input terminal of the three-stage push-pull circuit 3221 for shutdown; the first inverter D1 is used to invert the control signal PWM to obtain the second shutdown level signal OFF2 and output it to the three-stage push-pull circuit 3221 for shutdown; wherein, the first inverter D1 is an off-chip device.

[0142] The output terminal of the three-stage push-pull circuit 3221 is coupled to the gate of the first power transistor H1, and its input terminal is also coupled to the output terminal of the negative current slope detection component 321. The three-stage push-pull circuit 3221 receives the first turn-off level signal OFF1 and the second turn-off level signal OFF2, and sequentially outputs the fourth drive current IG4, the fifth drive current IG5, and the sixth drive current IG6 according to the first turn-off level signal OFF1 and the second turn-off level signal OFF2. Please refer to [reference needed]. Figure 6 The three-stage push-pull circuit 3221 specifically includes: a first-stage push-pull branch 32211 and a second-stage push-pull branch 32212.

[0143] The first-stage turn-off push-pull branch 32211 includes a third-stage push-pull circuit 322111 and a third MOSFET; the input terminal of the third-stage push-pull circuit 322111 is coupled to the output terminal of the first inverter D1, and its output terminal is coupled to the gate of the third MOSFET; the second terminal of the third MOSFET is coupled to the gate of the first power transistor H1; the third-stage push-pull circuit 322111 is used to receive the first turn-off level signal OFF1, and output the first turn-off signal to the gate of the third MOSFET after push-pull processing; the third MOSFET is used to output the third current IN1 or not output it under the action of the first turn-off signal after push-pull processing.

[0144] The second-stage turn-off push-pull branch 32212 includes a fourth-stage push-pull circuit 322121 and a fourth MOSFET. The input terminal of the fourth-stage push-pull circuit 322121 is coupled to the output terminal of the first inverter D1, and its output terminal is coupled to the gate of the fourth MOSFET. The second terminal of the fourth MOSFET is coupled to the gate of the first power transistor H1. The fourth-stage push-pull circuit 322121 is used to receive the second turn-off level signal OFF2, and output the second turn-off level signal OFF2 to the gate of the fourth MOSFET after push-pull operation. The fourth MOSFET is used to output the fourth current IN2 under the action of the second turn-off level signal OFF2 after push-pull operation.

[0145] The fourth driving current IG4 is composed of the third current IN1 and the fourth current IN2; the fifth driving current IG5 is composed of the fourth current IN2; and the sixth driving current IG6 is composed of the third current IN1 and the fourth current IN2.

[0146] In a preferred embodiment, both the third-stage push-pull circuit 322111 and the fourth-stage push-pull circuit 322121 are composed of six inverters connected in series; each inverter is a CMOS inverter. The third-stage push-pull circuit 322111 and the fourth-stage push-pull circuit 322121 are used to improve the driving capability of current. The principle is that the larger the size of the CMOS inverter, the greater its driving current capability. In this embodiment, the size of each CMOS inverter in the push-pull circuit increases progressively, so each time the CMOS inverter flips the input level, it improves the driving capability of current.

[0147] In a preferred embodiment, the first MOSFET and the second MOSFET are both PLDMOS transistors. The third MOSFET and the fourth MOSFET are both NLDMOS transistors. The size of the PLDMOS transistor and the NLDMOS transistor affects the driving capability of the integrated driving unit 30 for the first power transistor H1; the larger the size, the stronger the driving capability for the first power transistor H1.

[0148] Please refer to Figure 7 In one specific implementation, the voltage divider branch 11 includes a first voltage divider resistor R1 and a second voltage divider resistor R2;

[0149] The first end of the first voltage divider resistor R1 serves as the input end of the voltage divider branch 11 to receive the first induced voltage, and its second end serves as the output end of the voltage divider branch 11 to output the first feedback voltage Vfb. Its second end is also connected to the first end of the second feedback resistor.

[0150] The first terminal of the second voltage divider resistor R2 is connected to a first negative voltage source.

[0151] Please refer to Figure 8 In one specific implementation, the load unit 40 includes a second power transistor, a load inductor, a load capacitor, a first constant voltage source VA, and a second constant voltage source;

[0152] The second terminal of the first constant voltage source VA is connected to the gate of the second power transistor, and its first terminal is connected to the second terminal of the load inductor;

[0153] The first end of the second power transistor is coupled to the second end of the first power transistor H1 and the second end of the load inductor, respectively.

[0154] The second terminal of the second power transistor, the first terminal of the load inductor, the first terminal of the load capacitor, and the first terminal of the second constant voltage source are all connected to the load power supply terminal;

[0155] The second terminal of the load capacitor and the second terminal of the second constant voltage source are both connected to the input terminal of the voltage divider branch 11. Of course, the internal components of the load unit 40 can also be changed according to different actual circuits, and are not limited here.

[0156] In one specific implementation, the second power transistor includes an NMOS transistor; wherein, since the second terminal, i.e. the negative terminal, of the first constant voltage source VA is connected to the gate of the second power transistor, the second power transistor remains normally closed, the purpose of which is to prevent the first power transistor H1 from being broken down by high voltage.

[0157] Please refer to Figure 8 In a preferred embodiment, the fully integrated driver chip architecture based on current slope detection further includes an off-chip first diode and an off-chip second diode; the forward terminal of the first diode is connected to the reverse terminal of the second diode, and its forward terminal is also connected to the output terminal of the voltage divider branch 11, while its reverse terminal is connected to the first power supply terminal; the forward terminal of the second diode is connected to the first ground terminal. The off-chip first diode and the off-chip second diode constitute a clamping circuit to limit the magnitude of the first feedback voltage Vfb, preventing the first feedback voltage Vfb from becoming too large during the turn-off process and damaging subsequent circuitry.

[0158] Please refer to Figure 9 The workflow of the fully integrated driver chip architecture based on current slope detection provided in this embodiment of the invention is as follows:

[0159] During the conduction of the first power transistor H1, the control signal PWM is always at a high level, so the second turn-on signal Son2 is always at a high level.

[0160] t0-t1: In the initial stage of the first power transistor H1's conduction, the slope of the drain current flowing through the first power transistor H1 is 0. When the drain current flowing through the first power transistor H1 increases, the current slope also increases positively. According to the formula for the first feedback voltage Vfb, the positive increase of the current slope will reduce the first feedback voltage Vfb. The first reference voltage Vref1 is set lower than the initial first feedback voltage Vfb, and the first feedback voltage Vfb is input to the non-inverting input of the first comparator CP1, while the first reference voltage Vref1 is input to the inverting input of the first comparator CP1. Therefore, in the initial stage of the first power transistor H1's conduction, the first turn-on level signal ON1 output by the positive current slope detection component 311 is at a high level. Consequently, the first turn-on signal Son1 and the second turn-on signal Son2 received by the three-stage push-pull circuit 3122 are also at a high level, and its output is the first current IP1 plus the second current IP2, which is the first driving current IG1.

[0161] t2: When the current slope increases to the point that the first feedback voltage Vfb is lower than the first reference voltage Vref1, it indicates that the peak current in the first power transistor H1 is too large. Then, the first turn-on level signal ON1 output by the positive current slope detection component 311 changes from high level to low level. Then, the first turn-on signal Son1 and the second turn-on signal Son2 received by the turn-on three-stage push-pull circuit 3122 are low level and high level, respectively, and it outputs the second current IP2, which is the second drive current IG2.

[0162] t3-t4: When the current flowing through the first power transistor H1 rises to its peak value, the current slope gradually decreases until the first feedback voltage Vfb is higher than the first reference voltage Vref1 again. Then, the first turn-on level signal ON1 output by the positive current slope detection component 311 becomes high again. Then, the turn-on three-stage push-pull circuit 3122 outputs the first current IP1 plus the second current IP2, which is the third drive current IG3.

[0163] During the turn-off process of the first power transistor H1, the control signal PWM is always at a low level, so after the control signal PWM is inverted, the second turn-off level signal OFF2 is always at a high level.

[0164] t5-t6: In the initial stage of the first power transistor H1's turn-off, the slope of the drain current flowing through the first power transistor H1 is 0. When the drain current flowing through the first power transistor H1 decreases, the slope of the drain current will also increase in the opposite direction. According to the formula for the first feedback voltage Vfb, the reverse increase of the current slope will increase the first feedback voltage Vfb. The second reference voltage is set to be higher than the initial first feedback voltage Vfb, and the first feedback voltage Vfb is input to the inverting input of the second comparator CP2, while the second reference voltage is input to the non-inverting input of the second comparator CP2. Therefore, in the initial stage of the first power transistor H1's turn-off, the first turn-off level signal OFF1 output by the negative current slope detection component 321 is at a high level. Then, the turn-off three-stage push-pull circuit 3221 outputs the third current IN1 plus the fourth current IN2, which is the fourth driving current IG4.

[0165] t7: When the current slope increases in the reverse direction to the point that the first feedback voltage Vfb is higher than the second reference voltage, it indicates that the peak voltage in the first power transistor H1 is too large. Then, the first turn-off level signal OFF1 output by the negative current slope detection component 321 changes from high level to low level, and the turn-off three-stage push-pull circuit 3221 outputs the fourth current IN2, which is the fifth driving current IG5.

[0166] t8-t9: When the current flowing through the first power transistor H1 drops to 0, the current slope gradually increases until the first feedback voltage Vfb is lower than the second reference voltage again. Then, the first turn-off level signal OFF1 output by the negative current slope detection component 321 becomes high again. Then, the three-stage push-pull circuit 3221 outputs the third current IN1 plus the fourth current IN2, which is the sixth driving current IG6.

[0167] The fully integrated driver chip architecture based on current slope detection provided in this invention has the following advantages:

[0168] 1. Low latency: The fully integrated driver chip architecture based on current slope detection integrates the existing off-chip FPGA and digital programmable driver chip-based driving circuits to form a fully integrated driver chip. It also integrates a detection circuit within the chip and adds a feedback unit 10 outside the chip to provide feedback on the leakage inductance voltage of the first power transistor H1. This solves the latency problems caused by the low control frequency of the off-chip FPGA and the large scale of the digital circuits inside the digital programmable driver chip. The control latency of the first power transistor H1 in the prior art is generally between 30ns and 80ns, while the fully integrated driver chip architecture provided in this embodiment can be reduced to about 10ns.

[0169] 2. Low cost: Similar to low latency, the analog integration of existing off-chip FPGAs and digital programmable driver chips into a fully integrated driver chip not only reduces control latency but also reduces circuit size and saves circuit costs.

[0170] 3. The operating state of the SiC MOSFET can be adaptively controlled. By setting a feedback unit 10, the current slope of the drain induced voltage of the SiC MOSFET is fed back in real time. When the current slope of the drain induced voltage of the SiC MOSFET changes significantly, it can be fed back to the integrated drive unit 30 to change the drive current acting on the gate of the SiC MOSFET, so as to reduce the turn-on speed of the SiC MOSFET.

[0171] This invention also provides an electronic device, including the fully integrated driver chip architecture based on current slope detection.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully integrated driver chip architecture based on current slope detection for driving a first power transistor, characterized in that, The first end of the first power tube is coupled to the ground, and the second end of the first power tube is coupled to a load power end through a load unit; the architecture comprises: a feedback unit, the feedback unit comprising a feedback inductor and a voltage dividing branch; the first end of the feedback inductor is coupled to the first end of the first power tube, and the second end of the feedback inductor is coupled to the input end of the voltage dividing branch; the feedback inductor is used to generate a first induced voltage and output the first induced voltage to the voltage dividing branch; the voltage dividing branch is coupled to the load unit, and the voltage dividing branch is used to divide the first induced voltage and output a first feedback voltage; wherein the first feedback voltage represents the changes of the peak current and the peak voltage caused by the changes of the current slope in the process of turning on and turning off of the first power tube; a control unit, used to output a control signal according to an input level; an integrated driving unit, comprising a turn-on three-stage driving branch and a turn-off three-stage driving branch; the turn-on three-stage driving branch comprises a positive current slope detection component and a turn-on three-stage processing circuit; the turn-off three-stage driving branch comprises a negative current slope detection component and a turn-off three-stage processing circuit; wherein: the positive current slope detection component is coupled to the output end of the voltage dividing branch, and is used to receive the first feedback voltage, compare the first feedback voltage with a first reference voltage, and output a first turn-on level signal; the turn-on three-stage processing circuit is coupled to the control unit, the positive current slope detection component and the gate of the first power tube respectively, and is used to receive the first turn-on level signal and the control signal, form a first driving current, a second driving current and a third driving current according to the first turn-on level signal and the control signal, and output the first driving current, the second driving current and the third driving current to the gate of the first power tube, so as to control the turn-on of the first power tube in different turn-on stages in sequence; the negative current slope detection component is coupled to the output end of the voltage dividing branch, and is used to receive the first feedback voltage, compare the first feedback voltage with a second reference voltage, and output a first turn-off level signal; the turn-off three-stage processing circuit is coupled to the control unit, the negative current slope detection component and the gate of the first power tube respectively, and is used to receive the first turn-off level signal and the control signal, form a fourth driving current, a fifth driving current and a sixth driving current according to the first turn-off level signal and the control signal, and output the fourth driving current, the fifth driving current and the sixth driving current to the gate of the first power tube, so as to control the turn-off of the first power tube in different turn-off stages in sequence; and the turn-on three-stage driving branch and the turn-off three-stage driving branch are integrated in the same chip.

2. The current slope detection based fully integrated driver chip architecture of claim 1, wherein, the turn-on three-stage processing circuit comprises a level shift circuit and a turn-on three-stage push-pull circuit. The level shift circuit is coupled to an output end of the positive current slope detection component, an output end of the control unit and an input end of the turn-on three-stage push-pull circuit respectively. The level shift circuit is used for connecting the first turn-on level signal and the control signal, and outputting corresponding first and second turn-on signals after level shifting the first turn-on level signal and the control signal respectively. An output end of the turn-on three-stage push-pull circuit is coupled to a gate of the first power tube, and the turn-on three-stage push-pull circuit is used for connecting the first and second turn-on signals and sequentially outputting the first, second and third drive currents according to the first and second turn-on signals.

3. The current slope detection based fully integrated driver chip architecture of claim 2, wherein, The turn-off three-stage processing circuit includes a first inverter and a turn-off three-stage push-pull circuit. An input end and an output end of the first inverter are coupled to an output end of the control unit and an input end of the turn-off three-stage push-pull circuit respectively, and the first inverter is used for inverting the control signal to obtain a second turn-off level signal and outputting the second turn-off level signal to the turn-off three-stage push-pull circuit. An output end of the turn-off three-stage push-pull circuit is coupled to a gate of the first power tube, and an input end of the turn-off three-stage push-pull circuit is also coupled to an output end of the negative current slope detection component; the turn-off three-stage push-pull circuit is used for connecting the first and second turn-off level signals and sequentially outputting the fourth, fifth and sixth drive currents according to the first and second turn-off level signals.

4. The current slope detection based fully integrated driver chip architecture according to claim 3, wherein, The positive current slope detection component includes a first comparator.

5. The current slope detection based fully integrated driver chip architecture according to claim 4, wherein, The negative current slope detection component includes a second comparator.

6. The current slope detection based fully integrated driver chip architecture of claim 3, wherein, The turn-on three-stage push-pull circuit includes a first-stage turn-on push-pull branch and a second-stage turn-on push-pull branch. The first-stage turn-on push-pull branch includes a first-stage push-pull circuit and a first MOS tube; an input end of the first-stage push-pull circuit is coupled to an output end of the level shift circuit, and an output end of the first-stage push-pull circuit is coupled to a gate of the first MOS tube. A second end of the first MOS tube is coupled to a gate of the first power tube, and the first-stage push-pull circuit is used for connecting the first turn-on signal and outputting the first turn-on signal to the gate of the first MOS tube after push-pull processing; The first MOS tube is used for outputting a first current or not outputting under the action of the first turn-on signal after push-pull processing; The second-stage turn-on push-pull branch includes a second-stage push-pull circuit and a second MOS tube; an input end of the second-stage push-pull circuit is coupled to an output end of the level shift circuit, and an output end of the second-stage push-pull circuit is coupled to a gate of the second MOS tube; a second end of the second MOS tube is coupled to a gate of the first power tube. The second-stage push-pull circuit is used for connecting the second turn-on signal and outputting the second turn-on signal to the gate of the second MOS tube after push-pull processing; The second MOS tube is used for outputting a second current under the action of the second turn-on signal after push-pull processing. The first drive current is composed of the first current and the second current; the second drive current is composed of the second current; and the third drive current is composed of the first current and the second current.

7. The current slope detection based fully integrated driver chip architecture according to claim 6, wherein, The off three-stage push-pull circuit comprises a first-stage off push-pull branch and a second-stage off push-pull branch. The first-stage off push-pull branch comprises a third-stage push-pull circuit and a third MOS transistor; an input end of the third-stage push-pull circuit is coupled to an output end of the first inverter, and an output end thereof is coupled to a gate of the third MOS transistor; a second end of the third MOS transistor is coupled to a gate of the first power transistor; the third-stage push-pull circuit is configured to receive the first off level signal, and output the first off level signal after push-pull to the gate of the third MOS transistor; and the third MOS transistor is configured to output a third current or not under the action of the first off level signal after push-pull. The second-stage off push-pull branch comprises a fourth-stage push-pull circuit and a fourth MOS transistor; an input end of the fourth-stage push-pull circuit is coupled to the output end of the first inverter, and an output end thereof is coupled to a gate of the fourth MOS transistor; a second end of the fourth MOS transistor is coupled to the gate of the first power transistor; the fourth-stage push-pull circuit is configured to receive the second off level signal, and output the second off level signal after push-pull to the gate of the fourth MOS transistor; and the fourth MOS transistor is configured to output a fourth drive current under the action of the second off level signal after push-pull. The fourth drive current is composed of the third current and a fourth current; the fifth drive current is composed of the fourth current; and the sixth drive current is composed of the third current and the fourth current. The first-stage push-pull circuit and the second-stage push-pull circuit are both composed of five-stage inverters in series.

8. The current slope detection based fully integrated driver chip architecture according to claim 7, wherein, The third-stage push-pull circuit and the fourth-stage push-pull circuit are both composed of six-stage inverters in series.

9. The current slope detection based fully integrated driver chip architecture of claim 7, wherein, The first MOS transistor and the second MOS transistor are both PLDMOS transistors.

10. The current slope detection based fully integrated driver chip architecture of claim 7, wherein, The third MOS transistor and the fourth MOS transistor are both NLDMOS transistors.

11. The current slope detection based fully integrated driver chip architecture of claim 7, wherein, The voltage dividing branch comprises a first voltage dividing resistor and a second voltage dividing resistor.

12. The current slope detection based fully integrated driver chip architecture of claim 1, wherein, A first end of the first voltage dividing resistor is used as an input end of the voltage dividing branch, and is configured to receive the first induced voltage; a second end thereof is used as an output end of the voltage dividing branch, and is configured to output the first feedback voltage; and the second end is further connected to a first end of the second voltage dividing resistor. A second end of the second voltage dividing resistor is connected to a first negative voltage source. The load unit comprises a second power transistor, a load inductor, a load capacitor, a first constant voltage source and a second constant voltage source.

13. The current slope detection based fully integrated driver chip architecture of claim 1, wherein, A second end of the first constant voltage source is connected to a gate of the second power transistor, and a first end thereof is connected to a second end of the load inductor. A first end of the second power transistor is coupled to a second end of the first power transistor and a second end of the load inductor, respectively. A second end of the second power transistor, a first end of the load inductor, a first end of the load capacitor and a first end of the second constant voltage source are all connected to the load power end. ​ The second end of the load capacitor and the second end of the second constant voltage source are connected to an input end of the voltage division branch.

14. The current slope detection based fully integrated driver chip architecture according to claim 13, wherein, The second power tube comprises an NMOS tube.

15. The current slope detection based fully integrated driver chip architecture according to any one of claims 1 to 14, characterized in that, The first power tube is a silicon carbide single tube.

16. The current slope detection based fully integrated driver chip architecture according to any one of claims 1 to 14, characterized in that, The feedback inductor is a drain-source parasitic inductor of the first power tube.

17. An electronic device, comprising: An all-integrated driving chip architecture based on current slope detection is provided.

Images