Gate phased drive circuit based on DAC digital signal feedback

Abstract

The present invention discloses a gate staged drive circuit based on DAC digital signal feedback, comprising a main controller, DAC1, DAC2, an operational amplifier, a comparator, a push-pull drive circuit, and a drive resistor. The two digital signal output terminals of the main controller are connected to the input terminals of DAC1 and DAC2, respectively. The output terminal of DAC2 is connected to the input terminal of the operational amplifier. The output terminal of DAC1 is connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the gate of the power switch tube. The output terminal of the operational amplifier is connected to the input terminal of the push-pull circuit. The push-pull circuit generates a gate drive signal via the drive resistor. The closed-loop feedback control generates the drive command. The gate active drive controls the drive voltage to influence the switching speed at different stages of the IGBT switching process, thereby optimizing the overvoltage, overcurrent, and loss characteristics of the IGBT during the switching process.

Description

Technical Field

[0001] The present invention relates to a semiconductor device driving circuit, in particular to a gate stage driving circuit based on DAC digital signal feedback. Background Art

[0002] With the rapid development of power electronics technology, converters based on wide-bandgap semiconductors have achieved higher system efficiency and power density. However, these higher switching speeds mean higher dv / dt and di / dt during the switching process, making them more susceptible to system stray parameters, manifesting as non-ideal electromagnetic energy pulse characteristics such as larger switching overvoltages and overcurrents. For high-voltage, high-capacity power electronic conversion systems, the electromagnetic energy conversion during the switching process is greater, and the switching losses, spike stresses, and electromagnetic interference (EMI) generated during the switching process are more prominent. These issues have become bottlenecks that affect converter reliability and hinder system optimization design.

[0003] Commonly used technologies for EMI suppression include snubber circuits, soft switching technology, and active gate drive technology. Active gate drive technology, as a new drive circuit, optimizes switching characteristics by adding active devices and adjusting drive parameters.

[0004] Currently, the commonly used gate drive technology has the following shortcomings in application:

[0005] 1. The traditional gate drive method uses a fixed drive voltage and drive resistance to adjust the switching characteristics of the device. It cannot optimize EMI and switching loss at the same time, and a trade-off must be made between EMI and switching loss.

[0006] 2. The gate active drive circuit of the high-speed ADC chip has a long control delay time and high hardware cost. Compared with DAC, it is expensive and most of them are from foreign manufacturers. It is difficult to obtain high-precision ADC chips.

[0007] 3. The gate active drive circuit using analog circuits is not precise enough in the switching process. When the controlled power device changes, the control parameters and control strategy cannot be changed online, and the circuit parameters need to be redesigned, which lacks adaptability. Summary of the Invention

[0008] The present invention provides a gate stage drive circuit based on DAC digital signal feedback, which can accurately control the gate voltage V in a closed loop. GE , reducing device overvoltage and overcurrent during the switching process, and can optimize EMI and switching losses at the same time.

[0009] According to one aspect of an embodiment of the present invention, a phased gate drive circuit based on DAC digital signal feedback is provided, comprising a main controller, DAC 1, DAC 2, an operational amplifier, a comparator, a push-pull drive circuit, and a drive resistor. The two digital signal output terminals of the main controller are connected to the input terminals of DAC 1 and DAC 2, respectively. The output terminal of DAC 2 is connected to the input terminal of the operational amplifier. The output terminal of DAC 1 is connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the gate of the power switch tube. The output terminal of the operational amplifier is connected to the input terminal of the push-pull circuit.

[0010] The main controller sends a digital signal V to DAC1 D1 , and give DAC1 a fixed clock signal; DAC1 simulates the digital control signal output by the main controller to obtain the analog reference value V of the staged control signal ref ; The comparator will reference the value V ref and gate voltage V GE For comparison: If V ref Greater than V GE , the comparator output V f Is 1; if V ref Less than V GE , the comparator output V f is 0, the comparator output V f Feedback to the main controller input; the main controller will be based on the feedback V f The signal is identified to determine the current stage of the power switch tube, and different drive control signals V are applied to the power switch tubes in different stages. D2 , thereby controlling the transient state of the switching process and the switching speed at different stages, and optimizing the switching loss without affecting the overvoltage and current, thereby achieving decoupling control of electrical stress and switching loss; the main controller outputs V D2 After DAC2 digital-to-analog conversion, the analog signal V OP , V OP After being proportionally amplified by an operational amplifier, a drive voltage is generated through a push-pull circuit, and the drive voltage is applied to the gate of the power switch tube through a drive resistor.

[0011] Beneficial effects of the present invention: 1. The present invention can accurately calculate the gate voltage V of the IGBT. GE The system automatically adjusts the gate potential based on the size of the gate, selecting the optimal drive voltage for each switching phase. This effectively suppresses IGBT voltage and current overshoots and EMI. High-speed ADCs are expensive and difficult to obtain. High-speed DACs and comparators are inexpensive and available in a wide variety of models. Using a high-speed DAC and comparator feedback solution can avoid the need for a high-speed ADC, improving feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings of the embodiments.

[0013] Figure 1 This is a gate staged drive circuit topology based on DAC digital signal feedback provided by an embodiment of the present invention.

[0014] Figure 2 This is a waveform diagram of the turn-on transient of the DAC digital signal feedback provided by one embodiment of the present invention.

[0015] Figure 3 This is a typical waveform diagram of the IGBT turn-on transient process provided by an embodiment of the present invention.

[0016] Figure 4 This is a typical waveform diagram of the IGBT turn-off transient process provided by an embodiment of the present invention.

[0017] Description of reference numerals:

[0018] V D1 - One digital signal output from FPGA;

[0019] V D2 -Another digital signal output by FPGA;

[0020] V ref -Analog voltage reference for DAC1 output;

[0021] V f -Comparator output;

[0022] V OP -DAC2 output result;

[0023] V CC -The upper limit voltage of the push-pull drive circuit;

[0024] V EE -The lower limit voltage of the push-pull drive circuit;

[0025] V drive - Output voltage of the push-pull drive circuit;

[0026] R G - driving resistor;

[0027] The gate of G-IGBT;

[0028] Collector of C-IGBT;

[0029] Emitter of E-IGBT;

[0030] V GE-The voltage between the IGBT gate and emitter;

[0031] V CE -The voltage between the collector and emitter of the IGBT;

[0032] i c -IGBT collector current;

[0033] V CC1 -Higher turn-on driving voltage;

[0034] V CC2 - Lower turn-on driving voltage;

[0035] V ml - the voltage of the Miller plateau;

[0036] V EE1 - Lower turn-off drive voltage;

[0037] V EE2 -Higher off-drive voltage. DETAILED DESCRIPTION

[0038] Figure 1 A gate staged drive circuit topology based on DAC digital signal feedback is presented. Figure 1 As shown, the staged gate drive circuit includes an FPGA, a DAC, an operational amplifier, a comparator, a push-pull drive circuit, and a drive resistor. The power switches driven by the staged gate drive circuit include, but are not limited to, MOSFETs and IGBTs. The switching process of a MOSFET is essentially the same as that of an IGBT. This embodiment uses an IGBT as an example to illustrate the staged gate drive circuit.

[0039] The two digital signal output ends of the main controller FPGA are respectively connected to the two digital-to-analog converter DAC input ends, one DAC output end is connected to the operational amplifier input end, and the other DAC output end is connected to the positive input end of the comparator. The negative input end of the comparator is connected to the IGBT gate, and the operational amplifier output end is connected to the push-pull circuit input end to generate a gate drive signal through the drive resistor.

[0040] The digital control unit (FPGA) receives and calculates the signals sent by the comparator. It generates drive commands through closed-loop feedback control and controls the drive voltage through gate active drive. This influences the switching speed at different stages of the IGBT switching process, optimizing the IGBT's overvoltage, overcurrent, and loss characteristics during the switching process. The push-pull drive circuit converts the signals from the digital control unit into usable drive signals for the IGBT.

[0041] Figure 1 The control process of the gate stage drive circuit shown includes the following steps:

[0042] Step 1: Output an initial digital signal V through FPGA D1 , and give DAC1 a fixed clock signal;

[0043] Step 2: Use DAC1 to simulate the digital control signal output by FPGA to obtain the analog reference value V of the staged control signal. ref ;

[0044] Step 3: The comparator converts the reference value V ref and gate voltage V GE For comparison: If V ref Greater than V GE , the comparator output V f =1; V ref Less than V GE , the comparator output V f is 0, the comparator output V f Feedback to the FPGA input. Figure 2 Figure 2 shows the waveform of the turn-on transient of the DAC digital signal feedback. Figure 2 As shown, 1) If the output gate voltage V GE Exceeds the voltage reference V ref , the comparator output V f is 0, the FPGA will control V ref Increase ΔV ref ,ΔV ref =0.25V; 2) If the output gate voltage V GE Lower than the voltage reference V ref , the comparator output V f is 1, the FPGA will control V ref Reduce ΔV ref , ΔV ref =0.25V, V ref The waveform will follow V GE .

[0045] Step 4: FPGA will generate the V signal according to the feedback from step 3. f The signal is identified to determine the current stage of the IGBT and different drive control signals V are applied to the IGBTs in different stages. D2 , thereby controlling the switching process transient.

[0046] Step 5, FPGA output V D2 After DAC2 digital-to-analog conversion, the analog signal V OP , V OP After proportional amplification by the operational amplifier, the driving voltage V is generated through the push-pull circuit. drive , applied to the IGBT gate through the driving resistor.

[0047] Figure 3 The typical waveform of IGBT turn-on transient process is shown. The turn-on transient of IGBT can be divided into four stages.

[0048] S1 (t0-t1) turn-on delay stage: PWM high level command is received at time t0. The gate circuit can be regarded as a charged first-order RC circuit. In order to minimize this delay time, a high drive voltage is used, which is V CC1 , the duration of S1 stage is expressed by formula (1).

[0049]

[0050] Among them, C ies =C ge +C gc , C ge is the parasitic capacitance between the IGBT gate and emitter, C gc is the parasitic capacitance between the IGBT gate and collector, V th This is the IGBT turn-on threshold voltage.

[0051] S2 (t1-t2) current rising stage: at t1 time i c It starts to increase from 0 and reaches the peak current i at time t2. peak In order to suppress EMI, di / dt needs to be as small as possible, so the driving voltage is reduced and adjusted to V CC2 .i c The rising slope of is expressed by formula (2), and the duration of S2 stage is expressed by formula (3).

[0052]

[0053]

[0054] Among them, g m is the transconductance of the IGBT, I L is the load current of the IGBT.

[0055] S3 (t2-t3) voltage drop phase: t2 starts the Miller platform phase, V CE Start to drop, V GE The device remains unchanged in the Miller platform stage. Most of the losses generated by the device come from this stage. It is necessary to shorten the time in the S3 stage as much as possible, so a high driving voltage is used. At this time, the driving voltage is V CC1 ,The Miller platform voltage is shown in formula (4), and the duration of the S3 stage is shown in formula (5).

[0056] V ml =IL / g m +V th (4)

[0057]

[0058] Among them, V bus is the DC bus voltage, ΔV CE V in S2 stage CE of pressure drop.

[0059] S4 (t3-t4) full conduction stage: v gs Will be from V ml Increase to V CC1 , at this stage the driving voltage is V CC1 .

[0060] In summary, during the power switch tube turn-on transient process: in the turn-on delay phase, the S1 drive circuit outputs a large drive voltage V CC1 In the current rising phase S2, the driving circuit outputs a small driving voltage V CC2 In the voltage drop phase S3, the driving circuit outputs a large driving voltage V CC1 In the full conduction stage S4, the drive circuit outputs a large drive voltage V CC1 . V CC2 Less than V CC1 .

[0061] Figure 4 The typical waveform of IGBT turn-off transient process is shown. The turn-off transient of IGBT can also be divided into four stages.

[0062] S5 (t5-t6) shutdown delay stage: PWM low level command is received at time t5. This delay time needs to be minimized as much as possible. Because it is a negative voltage drive, a low drive voltage is used. At this time, the drive voltage is V EE1 ,The duration of S5 stage is expressed by formula (6).

[0063]

[0064] S6 (t6-t7) voltage rising stage: at t6, V CE It starts to rise and reaches V at t7 bus , V GE The device remains unchanged in the Miller platform stage. Most of the losses generated by the device come from this stage. It is necessary to make the time in the S6 stage as short as possible, so a low negative drive voltage is used. At this time, the drive voltage is V EE1 , the duration of S6 stage is expressed as formula (7).

[0065]

[0066] S7 (t7-t8) Current drop phase: In order to suppress EMI, di / dt needs to be as small as possible. At this time, the driving voltage is adjusted to a higher negative driving voltage V EE2 The duration of the S7 stage is given by formula (3).

[0067]

[0068] Among them, i tail is the tail current of the IGBT.

[0069] S8 (t8-t9) tail current stage: the driving voltage is V EE1 .

[0070] In summary, during the power switch tube turn-off transient process: in the turn-off delay phase S5, the drive circuit outputs a drive voltage V with a larger absolute value. EE1 In the voltage rising stage S6, the driving circuit outputs a driving voltage V with a larger absolute value EE1 In the current drop phase S7, the drive circuit outputs a smaller absolute value of the drive voltage V EE2 In the tail current stage S8, the driving circuit outputs a driving voltage V with a larger absolute value. EE1 . Where V EE2 Greater than V EE1 ,|V EE2 |<|V EE1 |.

[0071] FPGA determines V f and V ref The value of V f In high-low level transition, and V ref The value is less than V th When in S1 stage, FPGA controls V D2 Output a higher turn-on driving voltage V CC1 When V f Keep less than 0, and V ref The value is V th With V ml When it is in the S2 stage, FPGA controls V D2 Outputs a lower turn-on drive voltage V CC2 When V f In high-low level transition, and V ref The value of V ml When the voltage changes near the S3 stage, the FPGA controls V D2 Output a higher turn-on driving voltage V CC1 When V f Keep less than 0, and Vref The value is greater than V ml When it is in S4 stage, FPGA controls V D2 Output a higher turn-on driving voltage V CC1 .

Claims

1. A gate staged drive circuit based on DAC digital signal feedback, characterized in that: The device comprises a main controller, a DAC1, a DAC2, an operational amplifier, a comparator, a push-pull drive circuit and a drive resistor, wherein the two digital signal output terminals of the main controller are respectively connected to the input terminals of the DAC1 and the DAC2, the output terminal of the DAC2 is connected to the input terminal of the operational amplifier, the output terminal of the DAC1 is connected to the positive phase input terminal of the comparator, the negative phase input terminal of the comparator is connected to the gate of the power switch tube, and the output terminal of the operational amplifier is connected to the input terminal of the push-pull drive circuit; The main controller transmits a digital signal V to the DAC1 D1 , and give the DAC1 a fixed clock signal; the DAC1 simulates the digital control signal output by the main controller to obtain the analog reference value V of the staged control signal ref ; The comparator will reference value V ref and gate voltage V GE For comparison: If V ref Greater than V GE , then the comparator outputs V f Is 1; if V ref Less than V GE , then the comparator outputs V f is 0, the comparator output V f Feedback to the main controller input terminal; the main controller will be based on the feedback V f The signal is identified to determine the current stage of the power switch tube, and different drive control signals V are applied to the power switch tubes in different stages. D2 , thereby controlling the switching process transient and the switching speed at different stages, and optimizing the switching loss without affecting the overvoltage and current, thereby achieving decoupling control of electrical stress and switching loss; the main controller outputs V D2 The analog signal V is obtained by the DAC2 digital-to-analog conversion OP , V OP The operational amplifier performs proportional amplification, and then the push-pull driving circuit generates a driving voltage, which is applied to the gate of the power switch tube through the driving resistor.

2. The gate staged drive circuit based on DAC digital signal feedback according to claim 1, characterized in that: 1) If the output gate voltage V GE Exceeds the voltage reference V ref , the comparator output V f is 0, the main controller will control V ref Increase ΔV ref ;2) If the output gate voltage V GE Lower than the voltage reference V ref , the comparator output V f is 1, the main controller will control V ref Reduce ΔV ref .

3. The gate staged drive circuit based on DAC digital signal feedback according to claim 1, characterized in that: Different driving control signals are applied to the power switch tubes at different stages of the turn-on process. The turn-on transient process includes: the turn-on delay stage, the drive circuit outputs a large driving voltage V CC1 During the current rising phase, the drive circuit outputs a small drive voltage V CC2 ; Voltage drop stage, the drive circuit outputs a large drive voltage V CC1 During the entire conduction phase, the drive circuit outputs a large drive voltage V CC1 , where V CC2 Less than V CC1 .

4. The gate staged driving circuit based on DAC digital signal feedback according to claim 1, characterized in that: Different driving control signals are applied to the power switch tubes at different stages of the shutdown process. The shutdown transient process includes: the shutdown delay stage, the driving circuit outputs a driving voltage V with a larger absolute value. EE1 ; Voltage rising stage, the drive circuit outputs a larger absolute value of the drive voltage V EE1 During the current drop phase, the drive circuit outputs a smaller absolute value drive voltage V EE2 ; In the tail current stage, the driving circuit outputs a driving voltage V with a larger absolute value EE1 , where V EE2 Greater than V EE1 ,|V EE2 |<|V EE1 |.

Images