Boot capacitor power supply method and device, chip and electronic equipment

Abstract

This disclosure provides a method, apparatus, chip, and electronic device for charging a bootstrap capacitor, belonging to the field of integrated circuit technology. The method includes: acquiring the operating state of a DC-DC chip, the voltage state across the bootstrap capacitor, and the pulse width timing clock of the upper power transistor; when the operating state is at maximum duty cycle, the falling edge of the pulse width timing clock is acquired, and the voltage state is undervoltage, controlling the lower power transistor to start charging the bootstrap capacitor for a first set time; when the operating state is within a specified time period after exiting sleep mode, controlling the lower power transistor to start charging the bootstrap capacitor for a second set time; when the operating state is at a non-maximum duty cycle and the voltage state is undervoltage, controlling the lower power transistor to start charging the bootstrap capacitor with a refresh clock, wherein the first set time is less than the standard full-charge time of the bootstrap capacitor, the second set time is greater than the standard full-charge time, and the pulse width of the refresh clock is greater than or equal to the standard full-charge time.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of integrated circuit technology, and more specifically to a method, apparatus, chip, and electronic device for replenishing small-value bootstrap capacitors under a COT (Constant On Time) architecture. Background Technology

[0002] Currently, widely used DC-DC converters require a bootstrap capacitor coupled between the BOOT and SW pins to provide energy for the power transistor to turn on. This bootstrap capacitor typically has a capacitance of 100nF to 470nF. However, when the capacitance of this bootstrap capacitor becomes too small, the energy provided for the power transistor to turn on is insufficient, preventing the system from properly turning on the power transistor.

[0003] Additionally, to improve efficiency, the system enters sleep mode under low load. In this mode, the high-power transistor, low-power transistor, and other internal modules are all turned off, preventing the bootstrap capacitor from being powered. When the system exits sleep mode, the bootstrap capacitor cannot provide enough energy to turn on the high-power transistor, causing the output voltage to drop and making it unable to stably power the next stage of the system.

[0004] Furthermore, when the system operates at its maximum duty cycle, the high-power transistor's on-time is very long while the low-power transistor's on-time is very short, resulting in a shortage of energy stored in the bootstrap capacitor. After the high-power transistor is turned on too many times, it becomes insufficient to turn on again, causing the output voltage to drop. This continues until the internal refresh clock for the bootstrap capacitor arrives, fully charging it before the high-power transistor is turned on again, raising the output voltage. This repeated process leads to very large output voltage ripple. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method, apparatus, chip, and electronic device for powering a bootstrap capacitor. This enables a small-value bootstrap capacitor under a COT architecture to operate stably under different duty cycles, reducing output voltage ripple. In addition, the small-value bootstrap capacitor can save PCB board space and reduce costs in applications.

[0006] To achieve the above objectives, a first aspect of this disclosure provides a method for charging a bootstrap capacitor, comprising: acquiring the operating state of a DC-DC chip, the voltage state across the bootstrap capacitor on the DC-DC chip, and the pulse width timing clock of the upper power transistor on the DC-DC chip; when the operating state is a first operating state, the falling edge of the pulse width timing clock is acquired, and the voltage state is undervoltage, controlling the lower power transistor on the DC-DC chip to turn on for a first set time to charge the bootstrap capacitor; when the operating state is a second operating state, controlling the lower power transistor to turn on for a second set time. The time is used to charge the bootstrap capacitor; when the operating state is the third operating state and the voltage state is undervoltage, the power transistor is turned on under the control of the refresh clock to charge the bootstrap capacitor, wherein the first operating state is the maximum duty cycle operating state, the second operating state is the operating state within a specified time period after exiting sleep mode, the third operating state is the normal operating state with a non-maximum duty cycle, the first set time is less than the standard time for fully charging the bootstrap capacitor, the second set time is greater than the standard time for fully charging, and the pulse width of the refresh clock is greater than or equal to the standard time for fully charging.

[0007] In some embodiments of this disclosure, the voltage state includes an undervoltage state and a non-undervoltage state. When the voltage difference across the bootstrap capacitor is less than a first set voltage value, the voltage state is an undervoltage state; when the voltage difference across the bootstrap capacitor is greater than a second set voltage value, the voltage state is a non-undervoltage state. The first set voltage value is related to the operating limit voltage value of the power transistor drive on the DC-DC chip.

[0008] In some embodiments of this disclosure, the method further includes: when the operating state is a third operating state and the voltage state is a non-undervoltage state, controlling the upper power transistor and the lower power transistor to alternately turn on according to the internal control logic of the DC-DC chip.

[0009] In some embodiments of this disclosure, the standard time for the bootstrap capacitor to fully charge can be obtained in the following manner:

[0010] according to The standard time for fully charging the bootstrap capacitor is obtained, where t st For the standard time to fully charge, C Boot I is the capacitance of the bootstrap capacitor, ΔV is the standard voltage across the bootstrap capacitor, and I is the standard voltage across the bootstrap capacitor. Boot The current is provided by the DC voltage source on the DC-DC chip.

[0011] In some embodiments of this disclosure, the first set time is at least greater than the time required to charge the voltage difference across the bootstrap capacitor from the operating limit voltage value to the standard voltage value.

[0012] In some embodiments of this disclosure, the method further includes: when the operating state is a first operating state and the rising edge of the pulse width timing clock is obtained, controlling the upper power transistor to turn off.

[0013] In some embodiments of this disclosure, the capacitance value of the bootstrap capacitor ranges from 2.2nF to 3.3nF.

[0014] According to a second aspect of this disclosure, a device for charging a bootstrap capacitor is provided, comprising: an acquisition module, configured to acquire the operating state of a DC-DC chip, the voltage state across the bootstrap capacitor on the DC-DC chip, and the pulse width timing clock of the upper power transistor on the DC-DC chip; and a control module, configured to, when the operating state is a first operating state, the falling edge of the pulse width timing clock is acquired, and the voltage state is an undervoltage state, control the lower power transistor on the DC-DC chip to turn on for a first set time to charge the bootstrap capacitor; and when the operating state is a second operating state, control the lower power transistor to turn on for a second set time. A set time is used to charge the bootstrap capacitor; when the operating state is the third operating state and the voltage state is undervoltage, the power transistor is turned on under the control of the refresh clock to charge the bootstrap capacitor. The first operating state is the maximum duty cycle operating state, the second operating state is the operating state within a specified time period after exiting sleep mode, and the third operating state is the normal operating state with a non-maximum duty cycle. The first set time is less than the standard time for fully charging the bootstrap capacitor, the second set time is greater than the standard time for fully charging, and the pulse width of the refresh clock is greater than or equal to the standard time for fully charging.

[0015] According to a third aspect of this disclosure, a DC-DC chip is provided. The DC-DC chip includes a power supply device for the bootstrap capacitor as described in a second aspect of this disclosure.

[0016] According to a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a third aspect of this disclosure.

[0017] Other features and advantages of the embodiments disclosed herein will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate embodiments of the present disclosure and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the drawings:

[0019] Figure 1 This is a schematic diagram of the topology circuit for the Cboot capacitor power supply method for small-value bootstrap capacitors according to embodiments of the present disclosure.

[0020] Figure 2 This is a schematic flowchart of a method for replenishing power to a bootstrap capacitor according to an embodiment of the present disclosure.

[0021] Figure 3 This is a waveform diagram of the maximum duty cycle operating state according to an embodiment of the present disclosure;

[0022] Figure 4 This is another waveform diagram of the maximum duty cycle operating state according to an embodiment of the present disclosure;

[0023] Figure 5 This is a waveform diagram illustrating the working state of exiting sleep mode according to an embodiment of the present disclosure;

[0024] Figure 6 This is another waveform diagram of the working state of exiting sleep mode according to an embodiment of the present disclosure;

[0025] Figure 7 This is a waveform diagram of the refresh clock supplying power to the bootstrap capacitor according to an embodiment of the present disclosure;

[0026] Figure 8 This is a schematic flowchart of a method for replenishing power to a bootstrap capacitor according to an embodiment of the present disclosure.

[0027] Figure 9 This is a schematic block diagram of a bootstrap capacitor charging device according to an embodiment of the present disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0029] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. Furthermore, terms such as “first” and “second” are used only to distinguish one element (or part of an element) from another element (or another part of an element).

[0030] As mentioned above, when the bootstrap capacitor in the DC-DC chip has a small capacitance value, there will be insufficient energy provided when the upper power transistor is turned on, which will prevent the system from turning on the upper power transistor normally. There will also be insufficient energy provided when the upper power transistor is turned on when exiting sleep mode, which will reduce the output voltage and make it impossible to stably power the next stage system. Furthermore, when the DC-DC chip is working at its maximum duty cycle, after the upper power transistor is turned on many times, the energy stored in the bootstrap capacitor will be insufficient to meet the demand, resulting in very large output voltage ripple.

[0031] To reduce the output voltage ripple of the DC-DC chip and ensure the normal turn-on of the power transistor in the DC-DC chip, the embodiments of this disclosure propose to add power replenishment after exiting sleep mode and power replenishment when operating at the maximum duty cycle, on the basis of replenishing the bootstrap capacitor with a fixed refresh clock. By replenishing the bootstrap capacitor with reasonable logic control, it can meet the current capability required to turn on the power transistor at any duty cycle.

[0032] Figure 1 This diagram illustrates a DC-DC chip and a topology circuit for powering a small-value bootstrap capacitor (Cboot) according to an embodiment of the present disclosure. Figure 1 As shown, the internal control logic of the DC-DC chip generates an upper transistor drive signal hsdr to control the upper power transistor drive Drv_hs, generates an upper transistor control signal hsg to control the switching of the upper power transistor Mn_H, and generates a lower transistor drive signal lsdr to control the lower power transistor drive Drv_ls, and generates a lower transistor control signal lsg to control the switching of the lower power transistor Mn_L. The upper transistor drive signal hsdr and the lower transistor drive signal lsdr are mutually exclusive signals. When the DC-DC chip powers on, switch S is closed, and a refresh clock clk with a fixed frequency and fixed pulse width turns on the lower power transistor Mn_L to refresh the bootstrap capacitor Cboot. During this time, the upper power transistor Mn_H remains closed. After the bootstrap capacitor Cboot is fully charged, the internal control logic of the DC-DC chip sequentially and alternately turns on the upper and lower power transistors to supply power to the external capacitor Cout, ultimately causing the output voltage Vout to reach the target value.

[0033] The charging process of the bootstrap capacitor Cboot is as follows: The power supply voltage Vin generates a DC voltage source VDD (e.g., 5V) through the internal LDO (Low Dropout Regulator). The lower power transistor Mn_L turns on. After the switch S is closed, the external bootstrap capacitor Cboot of the DC-DC chip is charged through the diode. The discharging process of the bootstrap capacitor Cboot is as follows: When the upper transistor drive signal hsdr is high, the bootstrap capacitor Cboot powers the upper power transistor drive Drv_hs, slowly charging the capacitor Cgs_hs between the gate and pin SW of the upper power transistor. This causes the voltage difference between the gate and pin SW of the upper power transistor to exceed the threshold Vth for the upper power transistor to turn on, thus successfully turning on the upper power transistor Mn_H and charging the external capacitor Cout.

[0034] To achieve small-value bootstrap capacitor charging under the COT architecture, in this embodiment, the bootstrap capacitor Cboot has a capacitance range of 2.2nF to 3.3nF. Figure 2 A schematic flowchart illustrating a method for replenishing the power of a bootstrap capacitor according to an embodiment of the present disclosure is shown. Figure 2 As shown, the method includes the following steps:

[0035] Step S210: Obtain the operating state of the DC-DC chip, the voltage state across the bootstrap capacitor on the DC-DC chip, and the pulse width timing clock of the power transistor on the DC-DC chip.

[0036] The voltage difference across the bootstrap capacitor Cboot is the voltage difference between pin BOOT and pin SW, and the voltage state across Cboot represents the various states of this voltage difference. In some embodiments of this disclosure, the voltage state across the bootstrap capacitor includes an undervoltage state and a non-undervoltage state. Specifically, when the voltage difference across Cboot is less than a first preset voltage value, the voltage state is undervoltage, and the corresponding voltage state signal Bootuv is a high-level signal. When the voltage difference across Cboot is greater than a second preset voltage value, the voltage state is non-undervoltage, and the corresponding voltage state signal Bootuv is a low-level signal. The selection of the first preset voltage value is related to the operating limit voltage of the upper power transistor driving Drv_hs on the DC-DC chip. That is, the first preset voltage value is related to the driving capability of the upper power transistor driving Drv_hs, and the selection of the first preset voltage value must ensure that the logic signal of the upper power transistor driving Drv_hs can toggle normally. For example, in this embodiment of the disclosure, when the DC voltage source VDD generated by the LDO is 5V and the operating limit voltage of the upper power transistor driving Drv_hs is 1.7V, in order to ensure the normal operation of the driving capability, this embodiment of the disclosure can set a certain margin, such as setting the first set voltage value to 2.3V. For the setting of the second set voltage value, it can be set to half of the DC voltage source VDD 5V plus a certain margin, for example, the second set voltage value is 2.8V. That is, when the voltage difference across the bootstrap capacitor Cboot is less than 2.3V, the voltage state is undervoltage, and the corresponding generated voltage state signal Bootuv is a high-level signal; when the voltage difference across the bootstrap capacitor Cboot is greater than 2.8V, the voltage state is not undervoltage, and the corresponding generated voltage state signal Bootuv is a low-level signal.

[0037] In some embodiments of this disclosure, the operating states of the DC-DC chip include a first operating state, a second operating state, and a third operating state. The first operating state is the maximum duty cycle operating state. The second operating state is the operating state for a specified time period after exiting sleep mode; in this embodiment, the specified time period can be any time period within the range of 1µs to 10µs. Furthermore, the following three conditions are used to determine whether to exit sleep mode: the first condition is entering sleep mode from a normal operating state where the upper and lower power transistors are alternately and orderly turned on; the second condition is that the voltage divider of the DC-DC chip's output voltage and the comparison signal with the internal reference are in a specified state; and the third condition is that the specified state lasts for a fixed time. In this embodiment, the specified state of the comparison signal is set to a low-level signal output when the voltage divider of the output voltage is lower than the internal reference, and the fixed duration can be selected as 5µs. The third operating state is the normal operating state without the maximum duty cycle.

[0038] Since this embodiment is applied to a COT architecture, the turn-on time of the upper power transistor Mn_H on the DC-DC chip is fixed. The turn-on time of the upper power transistor Mn_H is timed using a pulse width timing clock ON_timer. When the rising edge of the pulse width timing clock ON_timer arrives, the upper power transistor Mn_H is turned off, and when the falling edge of the pulse width timing clock ON_timer arrives, the lower power transistor Mn_L is turned on.

[0039] Step S220: When the working state is the first working state, the falling edge of the pulse width timing clock is obtained, and the voltage state is undervoltage state, the lower power transistor on the DC-DC chip is controlled to turn on for a first set time to charge the bootstrap capacitor.

[0040] When the operating state is the maximum duty cycle operating state, the turn-on time of the upper power transistor Mn_H is much longer than that of the lower power transistor Mn_L. This will cause the energy stored in the bootstrap capacitor Cboot to be consumed, resulting in a decreasing voltage difference across the bootstrap capacitor Cboot, eventually falling below the first set voltage value (e.g., 2.3V). Consequently, the voltage state across the bootstrap capacitor Cboot (i.e., the voltage difference between pin BOOT and pin SW) is in an undervoltage state, and the corresponding voltage state signal Bootuv is a high-level signal. In the embodiments of this disclosure, since the DC-DC chip is in a COT architecture, the turn-off of the upper power transistor Mn_H is controlled by the rising edge of the pulse width timing clock ON_timer. That is, even if the voltage state across the bootstrap capacitor Cboot is in an undervoltage state before the rising edge of the pulse width timing clock ON_timer arrives, the voltage difference across the bootstrap capacitor Cboot will still be low. Figure 3As shown, the voltage status signal Bootuv is a high-level signal, and the bootstrap capacitor Cboot will not be charged. This is because the first set voltage value in this embodiment has a margin, and even if the upper power transistor Mn_H remains on, it will not affect the normal toggling of the upper power transistor driving Drv_hs. In this embodiment, the upper power transistor Mn_H needs to be turned off only after the rising edge of the pulse width timing clock ON_timer arrives, thereby ensuring that the turn-on time of the upper power transistor Mn_H is consistent and the ripple of the output voltage of the DCDC chip is uniform. Figure 3 The turn-on time of the upper power transistor Mn_H shown is controlled by the rising edge of the pulse width timing clock ON_timer. If it remains on for an extended period, the bootstrap capacitor Cboot will draw excessive power. Therefore, it is necessary to recharge the bootstrap capacitor Cboot. Specifically, when the falling edge of the pulse width timing clock ON_timer is detected, and the voltage across the bootstrap capacitor Cboot is in an undervoltage state (i.e., the corresponding voltage state signal Bootuv is high), the lower power transistor Mn_L on the DC-DC chip is controlled to turn on for a first predetermined time to charge the bootstrap capacitor Cboot.

[0041] In this embodiment of the disclosure, the standard time for the bootstrap capacitor Cboot to fully charge can be obtained by the following formula (1):

[0042]

[0043] Among them, t st The standard charging time is given in nanoseconds (ns) and voltmeters (C). Boot ΔV is the capacitance of the bootstrap capacitor, in nF; ΔV is the standard voltage across the bootstrap capacitor, in V; I Boot The current supplied by the DC voltage source VDD on the DC-DC chip is expressed in mA. In some embodiments of this disclosure, when ΔV = 5V, C Boot =3.3nF, I Boot When the current is 70mA, the standard time t for full charging is obtained. st It is around 236ns.

[0044] Since the voltage difference across the bootstrap capacitor Cboot will not decrease to 0V under maximum duty cycle operation, it can be seen from the above formula (1) that the first set time can be less than the standard charging time of the bootstrap capacitor Cboot, and the first set time is at least greater than the time required to charge the voltage difference across the bootstrap capacitor from the operating limit voltage value to the standard voltage value. In this embodiment, the first set time is selected in the range of 150ns to 200ns. It can be seen from the above formula (1) that when the standard charging time t stWhen the value is around 236ns, the first set time can be set to 200ns, such as... Figure 4 As shown, when the falling edge of the pulse width timing clock ON_timer is received, and the voltage state across the bootstrap capacitor Cboot is undervoltage (i.e., the corresponding voltage state signal Bootuv is high), the lower power transistor Mn_L on the DC-DC chip is turned on for 200ns to charge the bootstrap capacitor Cboot. This charge is sufficient to make the voltage difference across the bootstrap capacitor Cboot greater than a second set voltage value (e.g., 2.8V), thus changing the voltage state across the bootstrap capacitor Cboot from undervoltage to non-undervoltage. In other words, the voltage state signal Bootuv flips from high to low, thereby achieving the following... Figure 4 In the example shown, the output voltage of the DC-DC chip has a regular, small ripple.

[0045] Step S230: When the operating state is the second operating state, control the lower power transistor to turn on for a second set time to charge the bootstrap capacitor.

[0046] When the DC-DC chip operates in sleep mode, all internal modules are shut down to improve its efficiency under light loads, and the bootstrap capacitor Cboot experiences power loss. When the DC-DC chip exits sleep mode, two scenarios exist: First, the voltage difference across the bootstrap capacitor Cboot is not less than a first preset voltage value. Figure 5 As shown, when the first set voltage value is 2.3V, if the voltage difference is 2.4V, the current voltage state is not undervoltage, and the corresponding voltage state signal Bootuv is a low-level signal. If normal operation begins at this time, after the upper power transistor Mn_H is turned on normally, as the bootstrap capacitor Cboot supplies power to it, the voltage difference across it will immediately decrease to below 2.3V, resulting in the upper power transistor Mn_H being turned on and then immediately turned off again, causing many small fluctuations in the output voltage of the DC-DC chip. The second situation is that the voltage difference across the bootstrap capacitor Cboot is less than the first set voltage value, such as... Figure 6 As shown, the current voltage state is undervoltage, and the corresponding voltage state signal Bootuv is a high-level signal. Since the DC-DC chip has just exited sleep mode, the refresh clock has not yet been established. If we wait for it to be established before refreshing and powering the bootstrap capacitor Cboot, the output voltage of the DC-DC chip will collapse because the power transistor Mn_H has not been turned on for a long time.

[0047] Therefore, in this embodiment, for the second operating state, regardless of which of the above-mentioned situations occurs with the bootstrap capacitor Cboot, the lower power transistor Mn_L will be forcibly turned on for a second set time to charge the bootstrap capacitor Cboot, while the upper power transistor Mn_H remains off. The second set time is longer than the standard full-charge time to ensure that the bootstrap capacitor Cboot is fully charged, allowing the DC-DC chip to generate waveforms normally. Figure 5 The example in the text corresponds to the first case, forcibly turning on the lower power transistor Mn_L for 300ns; such as... Figure 6 The example in the text corresponds to the second case, which also involves forcibly turning on the lower power transistor Mn_L for 300ns.

[0048] Step S240: When the operating state is the third operating state and the voltage state is undervoltage state, the power transistor is turned on under the control of the refresh clock to charge the bootstrap capacitor.

[0049] When the DC-DC chip is in normal operation with a non-maximum duty cycle, if the voltage difference across the bootstrap capacitor Cboot is less than a first set voltage value, the voltage state across Cboot is undervoltage, and the corresponding voltage state signal Bootuv is a high-level signal. Figure 7 As shown, at this time, the power transistor Mn_L is turned on under the control of the refresh clock clk to charge the bootstrap capacitor. The pulse width of the refresh clock clk is greater than or equal to the standard full-charge time. For example, when the standard full-charge time is 236ns calculated by formula (1), the pulse width of the refresh clock clk can be set to 240ns. The period of the refresh clock clk can be set according to requirements, for example, 2us, 5us, or 10us.

[0050] When the voltage difference across the bootstrap capacitor Cboot is greater than the second set voltage value, the voltage state across the bootstrap capacitor Cboot is in a non-undervoltage state, and the corresponding voltage state signal Bootuv is a low-level signal. According to the internal control logic of the DC-DC chip, the upper power transistor and the lower power transistor are turned on alternately.

[0051] To further understand the embodiments of this disclosure, Figure 8 A schematic flowchart of a method for replenishing power to a bootstrap capacitor according to an embodiment of the present disclosure is shown, as follows: Figure 8 As shown, it includes the following steps:

[0052] Step S810: The DC-DC chip powers on and starts up.

[0053] Step S820: The bootstrap capacitor is pre-charged using a refresh clock within a preset time period. The preset time can be set as needed, for example, to 0.1 ms.

[0054] Step S830: Obtain the operating status of the DC-DC chip;

[0055] Step S840: Determine the working state as the first working state, i.e., the working state with the maximum duty cycle.

[0056] Step S841: Detect the pulse width timing clock of the power transistor;

[0057] Step S842: When the rising edge of the pulse width timing clock is detected, the upper power transistor is turned off. When the falling edge of the pulse width timing clock is detected, while keeping the upper power transistor off, it is determined whether the voltage state across the bootstrap capacitor is undervoltage. If it is undervoltage, step S843 is executed. If it is not undervoltage, the process returns to step S844.

[0058] Step S843: Control the lower power transistor on the DC-DC chip to turn on for a first set time to charge the bootstrap capacitor, then return to step S830. Since the voltage state across the bootstrap capacitor is undervoltage, the lower power transistor needs to be turned on for a first set time to charge the bootstrap capacitor. Since the voltage difference across the bootstrap capacitor will not decrease to 0V in the maximum duty cycle operating state, it can be seen from the above formula (1) that the first set time can be less than the standard time for fully charging the bootstrap capacitor, and the first set time is at least greater than the time required to charge the voltage difference across the bootstrap capacitor from the operating limit voltage value to the standard voltage value, which is sufficient to make the voltage difference across the bootstrap capacitor reach a value greater than the second set voltage value (e.g., 2.8V), so that the voltage state across the bootstrap capacitor changes from undervoltage to non-undervoltage.

[0059] In step S844, the lower power transistor is turned on according to the internal control logic of the DC-DC chip, and then the process returns to step S830. Since the voltage across the bootstrap capacitor is not undervoltage, there is no need to charge the bootstrap capacitor excessively. The turn-on of the lower power transistor can be controlled normally by the internal control logic of the DC-DC chip when it is in the maximum duty cycle operating state. For example, when the turn-on time of the upper power transistor accounts for 90%, the turn-on time of the lower power transistor accounts for 10%. For example, the turn-on time range of the lower power transistor is 50ns to 100ns.

[0060] Step S850: Determine the working state as the second working state, that is, the working state of exiting sleep mode;

[0061] In step S851, while keeping the upper power transistor off, the lower power transistor is controlled to turn on for a second set time to charge the bootstrap capacitor, and then the process returns to step S830.

[0062] Step S860: Determine the working state as the third working state, that is, the normal working state without maximum duty cycle.

[0063] Step S861: Determine whether the voltage across the bootstrap capacitor is undervoltage. If it is undervoltage, proceed to step S862. If it is not undervoltage, proceed to step S863.

[0064] Step S862: The lower power transistor is turned on to charge the bootstrap capacitor under the control of the refresh clock, while the upper power transistor remains off.

[0065] Step S863: Control the upper power transistor and the lower power transistor to turn on alternately according to the internal control logic of the DC-DC chip.

[0066] The embodiments disclosed herein propose a method for powering small-value bootstrap capacitors under a COT architecture. In addition to powering the bootstrap capacitor with a fixed refresh clock, powering is added after exiting sleep mode and at maximum duty cycle. Through reasonable logic control, the bootstrap capacitor is powered to meet the current requirement for turning on the upper power transistor at any duty cycle, while ensuring the normal operation of the DC-DC chip and minimizing the ripple of the DC-DC chip's output voltage. Furthermore, the small-value bootstrap capacitor saves PCB board space, achieving cost savings.

[0067] Figure 9 A schematic block diagram of a bootstrap capacitor charging device 900 according to an embodiment of the present disclosure is shown. Figure 9As shown, the bootstrap capacitor charging device 900 can be applied to charge small-value bootstrap capacitors, for example, the capacitance range of the bootstrap capacitor is 2.2nF to 3.3nF. The bootstrap capacitor charging device 900 may include: an acquisition module 910, used to acquire the operating state of the DC-DC chip, the voltage state across the bootstrap capacitor on the DC-DC chip, and the pulse width timing clock of the upper power transistor on the DC-DC chip; and a control module 920, used to control the lower power transistor on the DC-DC chip to turn on for a first set time to charge the bootstrap capacitor when the operating state is a first operating state, the falling edge of the pulse width timing clock is acquired, and the voltage state is undervoltage; and to control the lower power transistor to turn on for a second set time when the operating state is a second operating state. The bootstrap capacitor is charged intermittently. When the operating state is the third operating state and the voltage state is undervoltage, the power transistor is turned on under the control of the refresh clock to charge the bootstrap capacitor. The first operating state is the maximum duty cycle operating state, the second operating state is the operating state within a specified time period after exiting sleep mode, and the third operating state is the normal operating state with a non-maximum duty cycle. The first set time is less than the standard time for fully charging the bootstrap capacitor, the second set time is greater than the standard time for fully charging, and the pulse width of the refresh clock is greater than or equal to the standard time for fully charging.

[0068] The voltage state includes an undervoltage state and a non-undervoltage state. When the voltage difference across the bootstrap capacitor is less than a first set voltage value, the voltage state is an undervoltage state. When the voltage difference across the bootstrap capacitor is greater than a second set voltage value, the voltage state is a non-undervoltage state. The first set voltage value is related to the operating limit voltage value of the power transistor drive on the DC-DC chip.

[0069] In some embodiments of this disclosure, the control module 920 is further configured to: when the operating state is the third operating state and the voltage state is not undervoltage state, control the upper power transistor and the lower power transistor to turn on alternately according to the internal control logic of the DC-DC chip.

[0070] In some embodiments of this disclosure, the standard time for the bootstrap capacitor to fully charge can be obtained in the following manner:

[0071] according to The standard time for fully charging the bootstrap capacitor is obtained, where t st For the standard time to fully charge, C Boot I is the capacitance of the bootstrap capacitor, ΔV is the standard voltage across the bootstrap capacitor, and I is the standard voltage across the bootstrap capacitor. Boot The current is provided by the DC voltage source on the DC-DC chip.

[0072] In some embodiments of this disclosure, the first set time is at least greater than the time required to charge the voltage difference across the bootstrap capacitor from the operating limit voltage value to the standard voltage value.

[0073] In some embodiments of this disclosure, the control module 920 is further configured to: control the upper power transistor to turn off when the working state is the first working state and the rising edge of the pulse width timing clock is obtained.

[0074] Embodiments of this disclosure also provide a DC-DC chip. This DC-DC chip includes a power supply device for the bootstrap capacitor according to embodiments of this disclosure.

[0075] Embodiments of this disclosure also provide an electronic device. This electronic device includes a DC-DC chip according to embodiments of this disclosure. This electronic device may be, for example, a mobile phone charging device, an automotive electronic device, a communication base station device, or a high-voltage to low-voltage converter.

[0076] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0077] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0078] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0079] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A method for replenishing the voltage of a bootstrap capacitor, characterized in that, include: The operating status of the DC-DC chip, the voltage state across the bootstrap capacitor on the DC-DC chip, and the pulse width timing clock of the power transistor on the DC-DC chip are obtained. When the operating state is the first operating state, the falling edge of the pulse width timing clock is obtained, and the voltage state is undervoltage, the lower power transistor on the DC-DC chip is controlled to turn on for a first set time to charge the bootstrap capacitor. When the operating state is the second operating state, the lower power transistor is controlled to turn on for a second set time to charge the bootstrap capacitor. When the operating state is the third operating state and the voltage state is undervoltage, the power transistor is turned on under the control of the refresh clock to charge the bootstrap capacitor. Wherein, the first working state is the maximum duty cycle working state, the second working state is the working state within a specified time period after exiting sleep mode, the third working state is the normal working state without maximum duty cycle, the first set time is less than the full charge standard time of the bootstrap capacitor, the second set time is greater than the full charge standard time, and the pulse width of the refresh clock is greater than or equal to the full charge standard time.

2. The method for replenishing the power of a bootstrap capacitor according to claim 1, characterized in that, The voltage state includes an undervoltage state and a non-undervoltage state. When the voltage difference across the bootstrap capacitor is less than a first set voltage value, the voltage state is an undervoltage state. When the voltage difference across the bootstrap capacitor is greater than a second set voltage value, the voltage state is a non-undervoltage state. The first set voltage value is related to the operating limit voltage value of the power transistor drive on the DC-DC chip.

3. The method for replenishing the power of a bootstrap capacitor according to claim 2, characterized in that, The method further includes: When the operating state is the third operating state and the voltage state is not undervoltage, the upper power transistor and the lower power transistor are alternately turned on according to the internal control logic of the DC-DC chip.

4. The method for replenishing the power of a bootstrap capacitor according to claim 1, characterized in that, The standard time for fully charging the bootstrap capacitor can be obtained in the following manner: according to The standard time for fully charging the bootstrap capacitor is obtained, where t st For the standard time to fully charge, C Boot I is the capacitance of the bootstrap capacitor, ΔV is the standard voltage across the bootstrap capacitor, and I is the standard voltage across the bootstrap capacitor. Boot The current is provided by the DC voltage source on the DC-DC chip.

5. The method for replenishing the power of a bootstrap capacitor according to claim 4, characterized in that, The first set time is at least greater than the time required to charge the voltage difference across the bootstrap capacitor from the operating limit voltage value to the standard voltage value.

6. The method for replenishing the power of a bootstrap capacitor according to claim 1, characterized in that, The method further includes: When the operating state is the first operating state and the rising edge of the pulse width timing clock is obtained, the upper power transistor is controlled to turn off.

7. The method for replenishing the power of a bootstrap capacitor according to any one of claims 1-6, characterized in that, The value of the bootstrap capacitor ranges from 2.2nF to 3.3nF.

8. A power supply device for a bootstrap capacitor, characterized in that, include: The acquisition module is used to acquire the operating status of the DC-DC chip, the voltage state across the bootstrap capacitor on the DC-DC chip, and the pulse width timing clock of the power transistor on the DC-DC chip. The control module is configured to, when the operating state is a first operating state, the falling edge of the pulse width timing clock is obtained, and the voltage state is undervoltage, control the lower power transistor on the DC-DC chip to turn on for a first set time to charge the bootstrap capacitor; when the operating state is a second operating state, control the lower power transistor to turn on for a second set time to charge the bootstrap capacitor; and when the operating state is a third operating state, and the voltage state is undervoltage, control the lower power transistor to turn on to charge the bootstrap capacitor using a refresh clock. Wherein, the first working state is the maximum duty cycle working state, the second working state is the working state within a specified time period after exiting sleep mode, the third working state is the normal working state without maximum duty cycle, the first set time is less than the full charge standard time of the bootstrap capacitor, the second set time is greater than the full charge standard time, and the pulse width of the refresh clock is greater than or equal to the full charge standard time.

9. A DC-DC chip, characterized in that, It includes a power supply device for a bootstrap capacitor as described in claim 8.

10. An electronic device, characterized in that, Includes the DC-DC chip according to claim 9.

Images